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parametrized-uart

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disabel1a / parametrized_UART

Fully parameterizable uart (data width, clock frequency, parity bit [ON/OFF];[ODD/EVEN], stop bit length, baud rate, seniority [DESC/ASC])

fpga hardware verilog systemverilog uart-protocol seniority baud-rate parity-check parametrized-uart stop-bit-length

Updated Jul 16, 2024
SystemVerilog

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