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Deduplicate ASM in sel4-runtime-common
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Signed-off-by: Nick Spinale <nick@nickspinale.com>
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nspin committed Jan 15, 2024
1 parent 9192129 commit 6d84a09
Showing 1 changed file with 37 additions and 31 deletions.
68 changes: 37 additions & 31 deletions crates/sel4-runtime-common/src/start.rs
Original file line number Diff line number Diff line change
Expand Up @@ -10,8 +10,17 @@
use core::arch::global_asm;
use core::cell::UnsafeCell;

// TODO alignment should depend on configuration
#[repr(C, align(16))]
#[repr(C)]
#[cfg_attr(
any(
target_arch = "aarch64",
target_arch = "riscv32",
target_arch = "riscv64",
target_arch = "x86_64",
),
repr(align(16))
)]
#[cfg_attr(target_arch = "arm", repr(align(4)))]
pub struct Stack<const N: usize>(UnsafeCell<[u8; N]>);

unsafe impl<const N: usize> Sync for Stack<N> {}
Expand All @@ -35,26 +44,35 @@ unsafe impl Sync for StackTop {}
macro_rules! declare_stack {
($size:expr) => {
#[no_mangle]
static __sel4_runtime_stack_top: $crate::_private::start::StackTop = {
static __sel4_runtime_common__stack_top: $crate::_private::start::StackTop = {
static STACK: $crate::_private::start::Stack<{ $size }> =
$crate::_private::start::Stack::new();
unsafe { STACK.top() }
};
};
}

macro_rules! common_asm_prefix {
() => {
r#"
.extern sel4_runtime_rust_entry
.extern __sel4_runtime_common__stack_top
.global _start
.section .text
_start:
"#
};
}

cfg_if::cfg_if! {
if #[cfg(target_arch = "aarch64")] {
global_asm! {
common_asm_prefix!(),
r#"
.extern sel4_runtime_rust_entry
.extern __sel4_runtime_stack_top
.section .text
.global _start
_start:
ldr x9, =__sel4_runtime_stack_top
ldr x9, =__sel4_runtime_common__stack_top
ldr x9, [x9]
mov sp, x9
b sel4_runtime_rust_entry
Expand All @@ -63,25 +81,17 @@ cfg_if::cfg_if! {
"#
}
} else if #[cfg(any(target_arch = "riscv64", target_arch = "riscv32"))] {
macro_rules! riscv_common {
macro_rules! riscv_common_asm_body {
() => {
r#"
.extern sel4_runtime_rust_entry
.extern __sel4_runtime_stack_top
.section .text
.global _start
_start:
# See https://www.sifive.com/blog/all-aboard-part-3-linker-relaxation-in-riscv-toolchain
.option push
.option norelax
1: auipc gp, %pcrel_hi(__global_pointer$)
addi gp, gp, %pcrel_lo(1b)
.option pop
la sp, __sel4_runtime_stack_top
la sp, __sel4_runtime_common__stack_top
lx sp, (sp)
jal sel4_runtime_rust_entry
Expand All @@ -97,7 +107,8 @@ cfg_if::cfg_if! {
ld \dst, \src
.endm
"#,
riscv_common!()
common_asm_prefix!(),
riscv_common_asm_body!()
}

#[cfg(target_arch = "riscv32")]
Expand All @@ -107,19 +118,14 @@ cfg_if::cfg_if! {
lw \dst, \src
.endm
"#,
riscv_common!()
common_asm_prefix!(),
riscv_common_asm_body!()
}
} else if #[cfg(target_arch = "x86_64")] {
global_asm! {
common_asm_prefix!(),
r#"
.extern sel4_runtime_rust_entry
.extern __sel4_runtime_stack_top
.section .text
.global _start
_start:
mov rsp, __sel4_runtime_stack_top
mov rsp, __sel4_runtime_common__stack_top
mov rbp, rsp
sub rsp, 0x8 // Stack must be 16-byte aligned before call
push rbp
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