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Require sel4_cfg attr in sel4_cfg_if macro
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Signed-off-by: Nick Spinale <nick@nickspinale.com>
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nspin committed Feb 12, 2024
1 parent 44d2835 commit 63ce236
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Showing 30 changed files with 119 additions and 104 deletions.
2 changes: 1 addition & 1 deletion crates/private/support/sel4-simple-task/runtime/src/lib.rs
Original file line number Diff line number Diff line change
Expand Up @@ -87,7 +87,7 @@ pub unsafe extern "C" fn cont_fn(cont_arg: *mut sel4_runtime_common::ContArg) ->
let endpoint = Endpoint::from_bits(thread_config.endpoint().unwrap());
let reply_authority = {
sel4::sel4_cfg_if! {
if #[cfg(KERNEL_MCS)] {
if #[sel4_cfg(KERNEL_MCS)] {
sel4::Reply::from_bits(thread_config.reply_authority().unwrap())
} else {
assert!(thread_config.reply_authority().is_none());
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2 changes: 1 addition & 1 deletion crates/private/tests/root-task/config/src/main.rs
Original file line number Diff line number Diff line change
Expand Up @@ -17,7 +17,7 @@ fn main(_: &sel4::BootInfoPtr) -> ! {
sel4::sel4_cfg_usize!(RETYPE_FAN_OUT_LIMIT),
);
sel4::sel4_cfg_if! {
if #[cfg(NUM_PRIORITIES = "0")] {
if #[sel4_cfg(NUM_PRIORITIES = "0")] {
compile_error!("uh oh");
} else {
debug_println!("NUM_PRIORITIES: {}", sel4::sel4_cfg_usize!(NUM_PRIORITIES));
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6 changes: 3 additions & 3 deletions crates/sel4-capdl-initializer/core/src/arch/mod.rs
Original file line number Diff line number Diff line change
Expand Up @@ -135,13 +135,13 @@ pub(crate) mod frame_types {
}

sel4::sel4_cfg_if! {
if #[cfg(ARCH_AARCH64)] {
if #[sel4_cfg(ARCH_AARCH64)] {
const CACHED: VmAttributes = VmAttributes::PAGE_CACHEABLE;
const UNCACHED: VmAttributes = VmAttributes::DEFAULT;
} else if #[cfg(ARCH_RISCV64)] {
} else if #[sel4_cfg(ARCH_RISCV64)] {
const CACHED: VmAttributes = VmAttributes::DEFAULT;
const UNCACHED: VmAttributes = VmAttributes::NONE;
} else if #[cfg(ARCH_X86_64)] {
} else if #[sel4_cfg(ARCH_X86_64)] {
const CACHED: VmAttributes = VmAttributes::DEFAULT;
const UNCACHED: VmAttributes = VmAttributes::CACHE_DISABLED;
}
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10 changes: 5 additions & 5 deletions crates/sel4-capdl-initializer/core/src/lib.rs
Original file line number Diff line number Diff line change
Expand Up @@ -108,7 +108,7 @@ impl<'a, N: ObjectName, D: Content, M: GetEmbeddedFrame, B: BorrowMut<[PerObject
self.init_vspaces()?;

sel4::sel4_cfg_if! {
if #[cfg(KERNEL_MCS)] {
if #[sel4_cfg(KERNEL_MCS)] {
self.init_sched_contexts()?;
}
}
Expand Down Expand Up @@ -343,7 +343,7 @@ impl<'a, N: ObjectName, D: Content, M: GetEmbeddedFrame, B: BorrowMut<[PerObject
#[sel4_cfg(any(ARCH_AARCH32, ARCH_AARCH64))]
Object::ArmIrq(obj) => {
sel4::sel4_cfg_if! {
if #[cfg(MAX_NUM_NODES = "1")] {
if #[sel4_cfg(MAX_NUM_NODES = "1")] {
init_thread::slot::IRQ_CONTROL.cap().irq_control_get_trigger(
*irq,
obj.extra.trigger,
Expand Down Expand Up @@ -581,7 +581,7 @@ impl<'a, N: ObjectName, D: Content, M: GetEmbeddedFrame, B: BorrowMut<[PerObject
}

sel4::sel4_cfg_if! {
if #[cfg(all(ARCH_AARCH64, ARM_HYPERVISOR_SUPPORT))] {
if #[sel4_cfg(all(ARCH_AARCH64, ARM_HYPERVISOR_SUPPORT))] {
if let Some(vcpu) = obj.vcpu() {
let vcpu = self.orig_cap::<cap_type::VCpu>(vcpu.object);
vcpu.vcpu_set_tcb(tcb)?;
Expand All @@ -607,7 +607,7 @@ impl<'a, N: ObjectName, D: Content, M: GetEmbeddedFrame, B: BorrowMut<[PerObject
let affinity: usize = obj.extra.affinity.try_into()?;

sel4::sel4_cfg_if! {
if #[cfg(KERNEL_MCS)] {
if #[sel4_cfg(KERNEL_MCS)] {
if let Some(sched_context_cap) = obj.sc() {
self.init_sched_context(sched_context_cap.object, affinity)?;
}
Expand Down Expand Up @@ -679,7 +679,7 @@ impl<'a, N: ObjectName, D: Content, M: GetEmbeddedFrame, B: BorrowMut<[PerObject
)?;

sel4::sel4_cfg_if! {
if #[cfg(not(MAX_NUM_NODES = "1"))] {
if #[sel4_cfg(not(MAX_NUM_NODES = "1"))] {
tcb.tcb_set_affinity(affinity.try_into().unwrap())?;
}
}
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6 changes: 3 additions & 3 deletions crates/sel4-capdl-initializer/types/src/when_sel4.rs
Original file line number Diff line number Diff line change
Expand Up @@ -134,13 +134,13 @@ impl HasVmAttributes for cap::PageTable {
}

sel4::sel4_cfg_if! {
if #[cfg(ARCH_AARCH64)] {
if #[sel4_cfg(ARCH_AARCH64)] {
const CACHED: VmAttributes = VmAttributes::PAGE_CACHEABLE;
const UNCACHED: VmAttributes = VmAttributes::DEFAULT;
} else if #[cfg(any(ARCH_RISCV64, ARCH_RISCV32))] {
} else if #[sel4_cfg(any(ARCH_RISCV64, ARCH_RISCV32))] {
const CACHED: VmAttributes = VmAttributes::DEFAULT;
const UNCACHED: VmAttributes = VmAttributes::NONE;
} else if #[cfg(ARCH_X86_64)] {
} else if #[sel4_cfg(ARCH_X86_64)] {
const CACHED: VmAttributes = VmAttributes::DEFAULT;
const UNCACHED: VmAttributes = VmAttributes::CACHE_DISABLED;
}
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16 changes: 8 additions & 8 deletions crates/sel4-kernel-loader/build.rs
Original file line number Diff line number Diff line change
Expand Up @@ -30,27 +30,27 @@ use sel4_rustfmt_helper::Rustfmt;
pub const SEL4_KERNEL_ENV: &str = "SEL4_KERNEL";

sel4_cfg_if! {
if #[cfg(WORD_SIZE = "64")] {
if #[sel4_cfg(WORD_SIZE = "64")] {
type FileHeader = object::elf::FileHeader64<Endianness>;
} else if #[cfg(WORD_SIZE = "32")] {
} else if #[sel4_cfg(WORD_SIZE = "32")] {
type FileHeader = object::elf::FileHeader32<Endianness>;
}
}

sel4_cfg_if! {
if #[cfg(SEL4_ARCH = "aarch64")] {
if #[sel4_cfg(SEL4_ARCH = "aarch64")] {
type SchemeImpl = schemes::AArch64;
} else if #[cfg(SEL4_ARCH = "aarch32")] {
} else if #[sel4_cfg(SEL4_ARCH = "aarch32")] {
type SchemeImpl = schemes::AArch32;
} else if #[cfg(SEL4_ARCH = "riscv64")] {
} else if #[sel4_cfg(SEL4_ARCH = "riscv64")] {
sel4_cfg_if! {
if #[cfg(PT_LEVELS = "3")] {
if #[sel4_cfg(PT_LEVELS = "3")] {
type SchemeImpl = schemes::RiscV64Sv39;
}
}
} else if #[cfg(SEL4_ARCH = "riscv32")] {
} else if #[sel4_cfg(SEL4_ARCH = "riscv32")] {
sel4_cfg_if! {
if #[cfg(PT_LEVELS = "2")] {
if #[sel4_cfg(PT_LEVELS = "2")] {
type SchemeImpl = schemes::RiscV32Sv32;
}
}
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4 changes: 2 additions & 2 deletions crates/sel4-kernel-loader/src/arch/arm/arch/mod.rs
Original file line number Diff line number Diff line change
Expand Up @@ -5,10 +5,10 @@
//

sel4_config::sel4_cfg_if! {
if #[cfg(ARCH_AARCH64)] {
if #[sel4_cfg(ARCH_AARCH64)] {
#[path = "aarch64/mod.rs"]
mod imp;
} else if #[cfg(ARCH_AARCH32)] {
} else if #[sel4_cfg(ARCH_AARCH32)] {
#[path = "aarch32/mod.rs"]
mod imp;
}
Expand Down
4 changes: 2 additions & 2 deletions crates/sel4-kernel-loader/src/arch/mod.rs
Original file line number Diff line number Diff line change
Expand Up @@ -8,10 +8,10 @@ use sel4_config::sel4_cfg_if;
use sel4_kernel_loader_payload_types::PayloadInfo;

sel4_cfg_if! {
if #[cfg(any(ARCH_AARCH64, ARCH_AARCH32))] {
if #[sel4_cfg(any(ARCH_AARCH64, ARCH_AARCH32))] {
#[path = "arm/mod.rs"]
mod imp;
} else if #[cfg(any(ARCH_RISCV64, ARCH_RISCV32))] {
} else if #[sel4_cfg(any(ARCH_RISCV64, ARCH_RISCV32))] {
#[path = "riscv/mod.rs"]
mod imp;
}
Expand Down
4 changes: 2 additions & 2 deletions crates/sel4-kernel-loader/src/arch/riscv/mod.rs
Original file line number Diff line number Diff line change
Expand Up @@ -77,7 +77,7 @@ impl Arch for ArchImpl {
switch_page_tables();

sel4_cfg_if! {
if #[cfg(MAX_NUM_NODES = "1")] {
if #[sel4_cfg(MAX_NUM_NODES = "1")] {
(kernel_entry)(
ui_p_reg_start,
ui_p_reg_end,
Expand All @@ -103,7 +103,7 @@ impl Arch for ArchImpl {
}

sel4_cfg_if! {
if #[cfg(MAX_NUM_NODES = "1")] {
if #[sel4_cfg(MAX_NUM_NODES = "1")] {
type KernelEntry = extern "C" fn(
ui_p_reg_start: usize,
ui_p_reg_end: usize,
Expand Down
6 changes: 3 additions & 3 deletions crates/sel4-kernel-loader/src/plat/mod.rs
Original file line number Diff line number Diff line change
Expand Up @@ -7,13 +7,13 @@
use sel4_config::sel4_cfg_if;

sel4_cfg_if! {
if #[cfg(all(any(ARCH_AARCH64, ARCH_AARCH32), PLAT_QEMU_ARM_VIRT))] {
if #[sel4_cfg(all(any(ARCH_AARCH64, ARCH_AARCH32), PLAT_QEMU_ARM_VIRT))] {
#[path = "qemu_arm_virt/mod.rs"]
mod imp;
} else if #[cfg(all(any(ARCH_AARCH64, ARCH_AARCH32), PLAT_BCM2711))] {
} else if #[sel4_cfg(all(any(ARCH_AARCH64, ARCH_AARCH32), PLAT_BCM2711))] {
#[path = "bcm2711/mod.rs"]
mod imp;
} else if #[cfg(all(any(ARCH_RISCV64, ARCH_RISCV32), any(PLAT_SPIKE, PLAT_QEMU_RISCV_VIRT)))] {
} else if #[sel4_cfg(all(any(ARCH_RISCV64, ARCH_RISCV32), any(PLAT_SPIKE, PLAT_QEMU_RISCV_VIRT)))] {
#[path = "riscv_generic/mod.rs"]
mod imp;
}
Expand Down
2 changes: 1 addition & 1 deletion crates/sel4-microkit/src/lib.rs
Original file line number Diff line number Diff line change
Expand Up @@ -111,7 +111,7 @@ pub mod _private {
}

sel4::config::sel4_cfg_if! {
if #[cfg(PRINTING)] {
if #[sel4_cfg(PRINTING)] {
pub use sel4_panicking_env::{debug_print, debug_println};
} else {
/// No-op for this configuration.
Expand Down
2 changes: 1 addition & 1 deletion crates/sel4-microkit/src/panicking.rs
Original file line number Diff line number Diff line change
Expand Up @@ -41,7 +41,7 @@ pub(crate) fn init_panicking() {

fn debug_put_char(c: u8) {
sel4::sel4_cfg_if! {
if #[cfg(PRINTING)] {
if #[sel4_cfg(PRINTING)] {
sel4::debug_put_char(c)
}
}
Expand Down
2 changes: 1 addition & 1 deletion crates/sel4-runtime-common/src/phdrs/tls.rs
Original file line number Diff line number Diff line change
Expand Up @@ -34,7 +34,7 @@ pub unsafe fn initialize_tls_on_stack_and_continue(cont_fn: ContFn, cont_arg: *m
}

sel4::sel4_cfg_if! {
if #[cfg(all(ARCH_X86_64, SET_TLS_BASE_SELF))] {
if #[sel4_cfg(all(ARCH_X86_64, SET_TLS_BASE_SELF))] {
const CHOSEN_SET_THREAD_POINTER_FN: SetThreadPointerFn = set_thread_pointer_via_syscall;

unsafe extern "C" fn set_thread_pointer_via_syscall(val: usize) {
Expand Down
81 changes: 48 additions & 33 deletions crates/sel4/config/generic/src/cfg_if.rs
Original file line number Diff line number Diff line change
Expand Up @@ -6,13 +6,25 @@

use proc_macro2::TokenStream;
use quote::{format_ident, quote};
use syn::{parse2, spanned::Spanned, Token};
use syn::{
parse::{ParseStream, Parser},
spanned::Spanned,
Token,
};

use crate::{parse_or_return, MacroImpls};
use crate::MacroImpls;

impl<'a> MacroImpls<'a> {
pub fn cfg_if_impl(&self, toks: TokenStream) -> TokenStream {
let input = parse_or_return!(toks as CfgIfInput);
let parser = move |parse_stream: ParseStream| {
parse_cfg_if_input(self.synthetic_attr(), parse_stream)
};
let input = match parser.parse2(toks) {
Ok(parsed) => parsed,
Err(err) => {
return err.to_compile_error();
}
};
for branch_with_condition in input.branches_with_conditions.iter() {
match self.eval_nested_meta(&branch_with_condition.condition) {
Ok(pass) => {
Expand All @@ -37,47 +49,47 @@ struct CfgIfInput {
trailing_branch_without_condition: Option<TokenStream>,
}

impl syn::parse::Parse for CfgIfInput {
fn parse(input: syn::parse::ParseStream) -> syn::Result<Self> {
let mut branches_with_conditions = vec![input.parse()?];
while input.peek(Token![else]) {
input.parse::<Token![else]>()?;
if input.peek(Token![if]) {
branches_with_conditions.push(input.parse()?);
} else {
break;
}
}
let trailing_branch_without_condition = if input.is_empty() {
None
fn parse_cfg_if_input(
synthetic_attr: &str,
input: syn::parse::ParseStream,
) -> syn::Result<CfgIfInput> {
let mut branches_with_conditions = vec![parse_branch_with_condition(synthetic_attr, input)?];
while input.peek(Token![else]) {
input.parse::<Token![else]>()?;
if input.peek(Token![if]) {
branches_with_conditions.push(parse_branch_with_condition(synthetic_attr, input)?);
} else {
Some(input.call(parse_branch)?)
};
Ok(Self {
branches_with_conditions,
trailing_branch_without_condition,
})
break;
}
}
let trailing_branch_without_condition = if input.is_empty() {
None
} else {
Some(input.call(parse_branch)?)
};
Ok(CfgIfInput {
branches_with_conditions,
trailing_branch_without_condition,
})
}

struct BranchWithCondition {
condition: syn::NestedMeta,
branch: TokenStream,
}

impl syn::parse::Parse for BranchWithCondition {
fn parse(input: syn::parse::ParseStream) -> syn::Result<Self> {
let condition = input.call(parse_condition)?;
let branch = input.call(parse_branch)?;
Ok(Self { condition, branch })
}
fn parse_branch_with_condition(
synthetic_attr: &str,
input: syn::parse::ParseStream,
) -> syn::Result<BranchWithCondition> {
let condition = parse_condition(synthetic_attr, input)?;
let branch = parse_branch(input)?;
Ok(BranchWithCondition { condition, branch })
}

type Condition = syn::NestedMeta;

const CFG: &str = "cfg";

fn parse_condition(input: syn::parse::ParseStream) -> syn::Result<Condition> {
fn parse_condition(synthetic_attr: &str, input: syn::parse::ParseStream) -> syn::Result<Condition> {
input.parse::<Token![if]>()?;
let attrs = syn::Attribute::parse_outer(input)?;
let attr = match attrs.len() {
Expand All @@ -90,8 +102,11 @@ fn parse_condition(input: syn::parse::ParseStream) -> syn::Result<Condition> {
))
}
};
if !attr.path.is_ident(&format_ident!("{}", CFG)) {
return Err(syn::Error::new(attr.span(), format!("expected '{CFG}'")));
if !attr.path.is_ident(&format_ident!("{}", synthetic_attr)) {
return Err(syn::Error::new(
attr.span(),
format!("expected '{synthetic_attr}'"),
));
}
attr.parse_args()
}
Expand Down
2 changes: 1 addition & 1 deletion crates/sel4/src/arch/arm/arch/aarch32/mod.rs
Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,7 @@ mod object;
mod user_context;

sel4_config::sel4_cfg_if! {
if #[cfg(ARM_HYPERVISOR_SUPPORT)] {
if #[sel4_cfg(ARM_HYPERVISOR_SUPPORT)] {
mod vcpu_reg;
}
}
Expand Down
2 changes: 1 addition & 1 deletion crates/sel4/src/arch/arm/arch/aarch64/mod.rs
Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,7 @@ mod object;
mod user_context;

sel4_config::sel4_cfg_if! {
if #[cfg(ARM_HYPERVISOR_SUPPORT)] {
if #[sel4_cfg(ARM_HYPERVISOR_SUPPORT)] {
mod vcpu_reg;
}
}
Expand Down
4 changes: 2 additions & 2 deletions crates/sel4/src/arch/arm/arch/mod.rs
Original file line number Diff line number Diff line change
Expand Up @@ -7,10 +7,10 @@
use sel4_config::sel4_cfg_if;

sel4_cfg_if! {
if #[cfg(ARCH_AARCH64)] {
if #[sel4_cfg(ARCH_AARCH64)] {
#[path = "aarch64/mod.rs"]
mod imp;
} else if #[cfg(ARCH_AARCH32)] {
} else if #[sel4_cfg(ARCH_AARCH32)] {
#[path = "aarch32/mod.rs"]
mod imp;
}
Expand Down
2 changes: 1 addition & 1 deletion crates/sel4/src/arch/arm/fault.rs
Original file line number Diff line number Diff line change
Expand Up @@ -19,7 +19,7 @@ declare_fault_newtype!(VmFault, sys::seL4_Fault_VMFault);
declare_fault_newtype!(Timeout, sys::seL4_Fault_Timeout);

sel4_cfg_if! {
if #[cfg(ARM_HYPERVISOR_SUPPORT)] {
if #[sel4_cfg(ARM_HYPERVISOR_SUPPORT)] {
declare_fault_newtype!(VGicMaintenance, sys::seL4_Fault_VGICMaintenance);
declare_fault_newtype!(VCpuFault, sys::seL4_Fault_VCPUFault);
declare_fault_newtype!(VPpiEvent, sys::seL4_Fault_VPPIEvent);
Expand Down
6 changes: 3 additions & 3 deletions crates/sel4/src/arch/mod.rs
Original file line number Diff line number Diff line change
Expand Up @@ -13,13 +13,13 @@ use sel4_config::sel4_cfg_if;
// - ARCH_X86

sel4_cfg_if! {
if #[cfg(any(ARCH_AARCH32, ARCH_AARCH64))] {
if #[sel4_cfg(any(ARCH_AARCH32, ARCH_AARCH64))] {
#[path = "arm/mod.rs"]
mod imp;
} else if #[cfg(any(ARCH_RISCV32, ARCH_RISCV64))] {
} else if #[sel4_cfg(any(ARCH_RISCV32, ARCH_RISCV64))] {
#[path = "riscv/mod.rs"]
mod imp;
} else if #[cfg(ARCH_X86_64)] {
} else if #[sel4_cfg(ARCH_X86_64)] {
#[path = "x86/mod.rs"]
mod imp;
}
Expand Down
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