Code

RISC-V support over CLINT#815

Code

Merged

korken89 merged 39 commits intortic-rs:masterrtic-rs/rtic:masterfrom romancardenas:masterromancardenas/rtic:masterCopy head branch name to clipboardMar 20, 2024

+2,308-301

Commits

Commits on Feb 27, 2024

• Rebase to master

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  59cde3e

• using interrupt_mod

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  a27bdbd

• bug fixes

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  e50bff6

• fix other backends

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  aa5c92b

• Add changelog

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  0b74452

• forgot about rtic-macros

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  bb78e98

• backend-specific configuration

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  79ec8a9

• core peripherals optional over macro argument

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  938cb9f

• pre_init_preprocessing binding

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  dcac6a1

• CI for RISC-V (WIP)

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  535570f

• separation of concerns

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  ee25c0a

• add targets for RISC-V examples

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  2319064

• remove qemu feature

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  ef91d0c

• prepare examples folder

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  dafd8f2

• move examples all together

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  123ab23

• move ci out of examples

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  02a34ae

• minor changes

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  4e4d0b7

• add cortex-m

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  e9a0ffc

• new xtask: proof of concept

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  e34bb5c

• fix build.yml

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  1493d1a

• feature typo

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  c68824d

• clean rtic examples

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  584461f

• reproduce weird issue

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  d8d731c

• remove unsafe code in user app

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  53dc2f1

• update dependencies

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  e3cfa2c

• allow builds on riscv32imc

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  e88d40f

• let's fix QEMU

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  3f9507c

• Update .github/workflows/build.yml

  Show description for 68fa940
  

  romancardenas

  and

  AfoHT

  committed
  68fa940

• New build.rs

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  045563e

• removing test features

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  84818d7

• adapt ui test to new version of clippy

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  6eacc13

• add more examples to RISC-V backend

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  b2428b8

• proper configuration of heapless for riscv32imc

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  5aff1e4

• opt-out examples for riscv32imc

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  bb17312

• point to new version of riscv-slic

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  da078d8

• adapt new macro bindings

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  dbcfe03

• adapt examples and CI to stable

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  1debe31

• fix cortex-m CI

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  27da4a2

Commits on Mar 7, 2024

• Review

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  97b434c