RTL correction for verilator (no added/removed lines).

Signed-off-by: Pascal Gouedo <pascal.gouedo@dolphin.fr>
pascalgouedo · Feb 28, 2024 · d9ef378 · d9ef378
1 parent c5bd3bd
commit d9ef378
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Showing 3 changed files with 8 additions and 8 deletions.
diff --git a/rtl/cv32e40p_core.sv b/rtl/cv32e40p_core.sv
@@ -1057,9 +1057,9 @@ module cv32e40p_core
   assign csr_addr_int = csr_num_e'(csr_access_ex ? alu_operand_b_ex[11:0] : '0);
 
   //  Floating-Point registers write
-  assign fregs_we     = (FPU & !ZFINX) ? ((regfile_alu_we_fw && regfile_alu_waddr_fw[5]) ||
-                                          (regfile_we_wb     && regfile_waddr_fw_wb_o[5]))
-                                       : 1'b0;
+  assign fregs_we     = (FPU == 1 & ZFINX == 0) ? ((regfile_alu_we_fw && regfile_alu_waddr_fw[5]) ||
+                                                   (regfile_we_wb     && regfile_waddr_fw_wb_o[5]))
+                                                : 1'b0;
 
   ///////////////////////////
   //   ____  __  __ ____   //

diff --git a/rtl/cv32e40p_cs_registers.sv b/rtl/cv32e40p_cs_registers.sv
@@ -509,7 +509,7 @@ module cv32e40p_cs_registers
 
         // mimpid, Machine Implementation ID
         CSR_MIMPID: begin
-          csr_rdata_int = (FPU || COREV_PULP || COREV_CLUSTER) ? 32'h1 : 'b0;
+          csr_rdata_int = (FPU == 1 || COREV_PULP == 1 || COREV_CLUSTER == 1) ? 32'h1 : 'b0;
         end
 
         // unimplemented, read 0 CSRs

diff --git a/rtl/cv32e40p_ex_stage.sv b/rtl/cv32e40p_ex_stage.sv
@@ -213,9 +213,9 @@ module cv32e40p_ex_stage
       end
     end else begin
       regfile_alu_we_fw_o = regfile_alu_we_i & ~apu_en_i;
-      regfile_alu_we_fw_power_o = !COREV_PULP ? regfile_alu_we_i & ~apu_en_i : 
-                                                regfile_alu_we_i & ~apu_en_i &
-                                                mult_ready & alu_ready & lsu_ready_ex_i;
+      regfile_alu_we_fw_power_o = (COREV_PULP == 0) ? regfile_alu_we_i & ~apu_en_i : 
+                                                     regfile_alu_we_i & ~apu_en_i &
+                                                     mult_ready & alu_ready & lsu_ready_ex_i;
       regfile_alu_waddr_fw_o = regfile_alu_waddr_i;
       if (alu_en_i) regfile_alu_wdata_fw_o = alu_result;
       if (mult_en_i) regfile_alu_wdata_fw_o = mult_result;
@@ -233,7 +233,7 @@ module cv32e40p_ex_stage
 
     if (regfile_we_lsu) begin
       regfile_we_wb_o       = 1'b1;
-      regfile_we_wb_power_o = !COREV_PULP ? 1'b1 : ~data_misaligned_ex_i & wb_ready_i;
+      regfile_we_wb_power_o = (COREV_PULP == 0) ? 1'b1 : ~data_misaligned_ex_i & wb_ready_i;
       if (apu_valid & (!apu_singlecycle & !apu_multicycle)) begin
         wb_contention_lsu = 1'b1;
       end