Merge pull request #1011 from davidharrishmc/dev

Fixed bug causing Issue 1010 and made some changes to Wally privileged fields to match ImperasDV
openhwgroup · Oct 14, 2024 · d8fe68b · d8fe68b
2 parents edd7e73 + 5e55055
commit d8fe68b
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Showing 4 changed files with 19 additions and 3 deletions.
diff --git a/config/rv64gc/imperas.ic b/config/rv64gc/imperas.ic
@@ -57,6 +57,17 @@
 #--override cpu/instret_undefined=T
 #--override cpu/hpmcounter_undefined=T
 
+--override cpu/scontext_undefined=T
+--override cpu/mcontext_undefined=T
+--override cpu/mnoise_undefined=T
+# *** how to override other undefined registers: seed, mphmevent, mseccfg, debugger registers
+#--override cpu/seed_undefined=T
+#--override mhpmevent3_undefined=T
+#--override cpu/mseccfg_undefined=T
+#--override cpu/tselect_undefined=T
+#--override cpu/tdata1_undefined=T
+
+
 --override cpu/reset_address=0x80000000
 
 --override cpu/unaligned=T  # Zicclsm (should be true)

diff --git a/src/privileged/csrm.sv b/src/privileged/csrm.sv
@@ -180,15 +180,18 @@ module csrm  import cvw::*;  #(parameter cvw_t P) (
   if (P.U_SUPPORTED) begin // menvcfg only exists if there is a lower privilege to control
     logic WriteMENVCFGM;
     logic [63:0] MENVCFG_PreWriteValM, MENVCFG_WriteValM;
+    logic [1:0] LegalizedCBIE;
     assign WriteMENVCFGM = CSRMWriteM & (CSRAdrM == MENVCFG);
+    assign LegalizedCBIE = MENVCFG_PreWriteValM[5:4] == 2'b10 ? MENVCFG_REGW[5:4] : MENVCFG_PreWriteValM[5:4]; // Assume WARL for reserved CBIE = 10, keeps old value
     // MENVCFG is always 64 bits even for RV32
     assign MENVCFG_WriteValM = {
       MENVCFG_PreWriteValM[63]  & P.SSTC_SUPPORTED,
       MENVCFG_PreWriteValM[62]  & P.SVPBMT_SUPPORTED,
       MENVCFG_PreWriteValM[61]  & P.SVADU_SUPPORTED,
       53'b0,
       MENVCFG_PreWriteValM[7]   & P.ZICBOZ_SUPPORTED,
-      MENVCFG_PreWriteValM[6:4] & {3{P.ZICBOM_SUPPORTED}},
+      MENVCFG_PreWriteValM[6]   & P.ZICBOM_SUPPORTED,
+      LegalizedCBIE             & {2{P.ZICBOM_SUPPORTED}},
       3'b0,
       MENVCFG_PreWriteValM[0]   & P.S_SUPPORTED & P.VIRTMEM_SUPPORTED
     };

diff --git a/src/privileged/csrsr.sv b/src/privileged/csrsr.sv
@@ -106,7 +106,8 @@ module csrsr import cvw::*;  #(parameter cvw_t P) (
   always_comb
     if      (CSRWriteValM[12:11] == P.U_MODE & P.U_SUPPORTED) STATUS_MPP_NEXT = P.U_MODE;
     else if (CSRWriteValM[12:11] == P.S_MODE & P.S_SUPPORTED) STATUS_MPP_NEXT = P.S_MODE;
-    else                                                    STATUS_MPP_NEXT = P.M_MODE;
+    else if (CSRWriteValM[12:11] == 2'b10)                    STATUS_MPP_NEXT = STATUS_MPP; // do not change MPP when trying to write reserved 10
+    else                                                      STATUS_MPP_NEXT = P.M_MODE;
 
   ///////////////////////////////////////////
   // Endianness logic Privileged Spec 3.1.6.4

diff --git a/tests/coverage/WALLY-init-lib.h b/tests/coverage/WALLY-init-lib.h
@@ -134,9 +134,10 @@ trap_return:            # return from trap handler
 setmsb:
     li a0, 0x80000000   # 1 in bit 31
     slli a1, a0, 1      # check if register is wider than 31 bits
-    beqz a1, 1f         # yes, a0 has 1 in bit 31
+    beqz a1, setmsbdone # yes, a0 has 1 in bit 31
     slli a0, a0, 16     # no: shift a0 to have 1 inn bit 63
     slli a0, a0, 16     # use two shifts of 16 bits each to be compatible with compiling either RV32 or 64
+setmsbdone:
     ret                 # return to calller
 
 .section .tohost