Fix regression-wally --fcov

openhwgroup · Dec 12, 2024 · 2d3ff20 · 2d3ff20
1 parent 2a3af54
commit 2d3ff20
Showing 1 changed file with 4 additions and 4 deletions.
diff --git a/sim/questa/wally.do b/sim/questa/wally.do
@@ -104,10 +104,10 @@ if {[lcheck lst "--ccov"]} {
 # if --fcov found set flag and remove from list
 if {[lcheck lst "--fcov"]} {
     set FunctCoverage 1
-    set FCvlog "+incdir+$env(WALLY)/addins/cvw-arch-verif/riscvISACOV/source \
-                +incdir+${FCRVVI}/rv32 +incdir+${FCRVVI}/rv64 \
+    set FCvlog "+incdir+${FCRVVI}/rv32 +incdir+${FCRVVI}/rv64 \
                 +incdir+${FCRVVI}/priv +incdir+${FCRVVI}/rv64_priv +incdir+${FCRVVI}/rv32_priv \
-                +incdir+${FCRVVI}/common +incdir+${FCRVVI}"
+                +incdir+${FCRVVI}/common +incdir+${FCRVVI} \
+                +incdir+$env(WALLY)/addins/cvw-arch-verif/riscvISACOV/source"
 }
 
 # if --lockstep or --fcov found set flag and remove from list
@@ -164,7 +164,7 @@ if {$DEBUG > 0} {
 # because vsim will run vopt
 set INC_DIRS "+incdir+${CONFIG}/${CFG} +incdir+${CONFIG}/deriv/${CFG} +incdir+${CONFIG}/shared"
 set SOURCES "${SRC}/cvw.sv ${TB}/${TESTBENCH}.sv ${TB}/common/*.sv ${SRC}/*/*.sv ${SRC}/*/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*/*/*.sv"
-vlog -permissive -lint -work ${WKDIR} {*}${INC_DIRS} {*}${DefineArgs} {*}${FCvlog} {*}${lockstepvlog} {*}${SOURCES} -suppress 2282,2583,7053,7063,2596,13286
+vlog -permissive -lint -work ${WKDIR} {*}${INC_DIRS} {*}${FCvlog} {*}${DefineArgs} {*}${lockstepvlog} {*}${SOURCES} -suppress 2282,2583,7053,7063,2596,13286
 
 # start and run simulation
 # remove +acc flag for faster sim during regressions if there is no need to access internal signals