vendorized common_cells

.gitmodules

@@ -1,6 +1,3 @@
-[submodule "src-sv/common_cells"]
-	path = src/common_cells
-	url = https://github.com/pulp-platform/common_cells.git
 [submodule "src-sv/fpu_div_sqrt_mvp"]
 	path = src/fpu_div_sqrt_mvp
 	url = https://github.com/pulp-platform/fpu_div_sqrt_mvp.git

Bender.yml

@@ -6,13 +6,15 @@ package:
   authors: ["Stefan Mach <smach@iis.ee.ethz.ch>"]
 
 dependencies:
-  common_cells: {git: "https://github.com/pulp-platform/common_cells.git",         version: 1.21.0}
   fpu_div_sqrt_mvp: {git: "https://github.com/pulp-platform/fpu_div_sqrt_mvp.git", version: 1.0.4}
 
 sources:
   - src/fpnew_pkg.sv
   - src/fpnew_cast_multi.sv
   - src/fpnew_classifier.sv
+  - vendor/common_cells/src/cf_math_pkg.sv
+  - vendor/common_cells/src/rr_arb_tree.sv
+  - vendor/common_cells/src/lzc.sv
   - vendor/opene906/E906_RTL_FACTORY/gen_rtl/clk/rtl/gated_clk_cell.v
   - vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_ctrl.v
   - vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_ff1.v

vendor/common_cells.lock.hjson

@@ -0,0 +1,14 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// This file is generated by the util/vendor script. Please do not modify it
+// manually.
+
+{
+  upstream:
+  {
+    url: https://github.com/pulp-platform/common_cells.git
+    rev: 6aeee85d0a34fedc06c14f04fd6363c9f7b4eeea
+  }
+}

vendor/common_cells.vendor.hjson

@@ -0,0 +1,32 @@
+// Copyright 2023 OpenHW Group
+// Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+{
+  name: "common_cells",
+  target_dir: "common_cells",
+
+  upstream: {
+    url: "https://github.com/pulp-platform/common_cells.git",
+    rev: "6aeee85d0a34fedc06c14f04fd6363c9f7b4eeea",
+  },
+
+  exclude_from_upstream: [
+    ".github",
+    ".gitignore",
+    ".gitlab-ci.yml",
+    ".travis.yml",
+    "ci/",
+    "Bender.yml",
+    "CHANGELOG.md",
+    "LICENSE",
+    "Makefile",
+    "README.md",
+    "ci",
+    "formal",
+    "ips_list.yml",
+    "lint",
+    "src_files.yml",
+    "test"
+  ]
+
+}

vendor/common_cells/common_cells.core

@@ -0,0 +1,99 @@
+CAPI=2:
+
+name : pulp-platform.org::common_cells:1.20.0
+
+filesets:
+  rtl:
+    files:
+      - include/common_cells/registers.svh : {is_include_file : true, include_path : include}
+      # Source files grouped in levels. Files in level 0 have no dependencies on files in this package.
+      # Files in level 1 only depend on files in level 0, files in level 2 on files in levels 1 and 0,
+      # etc. Files within a level are ordered alphabetically.
+      # Level 0
+      - src/binary_to_gray.sv
+      - src/cb_filter_pkg.sv
+      - src/cdc_2phase.sv
+      - src/cf_math_pkg.sv
+      - src/clk_div.sv
+      - src/delta_counter.sv
+      - src/ecc_pkg.sv
+      - src/edge_propagator_tx.sv
+      - src/exp_backoff.sv
+      - src/fifo_v3.sv
+      - src/gray_to_binary.sv
+      - src/isochronous_spill_register.sv
+      - src/lfsr.sv
+      - src/lfsr_16bit.sv
+      - src/lfsr_8bit.sv
+      - src/mv_filter.sv
+      - src/onehot_to_bin.sv
+      - src/plru_tree.sv
+      - src/popcount.sv
+      - src/rr_arb_tree.sv
+      - src/rstgen_bypass.sv
+      - src/serial_deglitch.sv
+      - src/shift_reg.sv
+      - src/spill_register.sv
+      - src/stream_demux.sv
+      - src/stream_filter.sv
+      - src/stream_fork.sv
+      - src/stream_intf.sv
+      - src/stream_join.sv
+      - src/stream_mux.sv
+      - src/sub_per_hash.sv
+      - src/sync.sv
+      - src/sync_wedge.sv
+      - src/unread.sv
+      # Level 1
+      - src/addr_decode.sv
+      - src/cb_filter.sv
+      - src/cdc_fifo_2phase.sv
+      - src/cdc_fifo_gray.sv
+      - src/counter.sv
+      - src/ecc_decode.sv
+      - src/ecc_encode.sv
+      - src/edge_detect.sv
+      - src/lzc.sv
+      - src/max_counter.sv
+      - src/rstgen.sv
+      - src/stream_delay.sv
+      - src/stream_fifo.sv
+      - src/stream_fork_dynamic.sv
+      - src/stream_xbar.sv
+      # Level 2
+      - src/fall_through_register.sv
+      - src/id_queue.sv
+      - src/stream_to_mem.sv
+      - src/stream_arbiter_flushable.sv
+      - src/stream_omega_net.sv
+      - src/stream_register.sv
+      # Level 3
+      - src/stream_arbiter.sv
+    file_type : systemVerilogSource
+
+  deprecated:
+    files:
+      # Deprecated modules
+      # Level 0
+      - src/deprecated/clock_divider_counter.sv
+      - src/deprecated/find_first_one.sv
+      - src/deprecated/generic_LFSR_8bit.sv
+      - src/deprecated/generic_fifo.sv
+      - src/deprecated/prioarbiter.sv
+      - src/deprecated/pulp_sync.sv
+      - src/deprecated/pulp_sync_wedge.sv
+      - src/deprecated/rrarbiter.sv
+      # Level 1
+      - src/deprecated/clock_divider.sv
+      - src/deprecated/fifo_v2.sv
+      # Level 2
+      - src/deprecated/fifo_v1.sv
+
+      # Depend on deprecated modules
+      - src/edge_propagator.sv
+      - src/edge_propagator_rx.sv
+    file_type : systemVerilogSource
+
+targets:
+  default:
+    filesets : [rtl, deprecated]

vendor/common_cells/include/common_cells/assertions.svh

@@ -0,0 +1,201 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// Macros and helper code for using assertions.
+//  - Provides default clk and rst options to simplify code
+//  - Provides boiler plate template for common assertions
+
+`ifndef PRIM_ASSERT_SV
+`define PRIM_ASSERT_SV
+
+`ifdef UVM
+  // report assertion error with UVM if compiled
+  package assert_rpt_pkg;
+    import uvm_pkg::*;
+    `include "uvm_macros.svh"
+    function void assert_rpt(string msg);
+      `uvm_error("ASSERT FAILED", msg)
+    endfunction
+  endpackage
+`endif
+
+///////////////////
+// Helper macros //
+///////////////////
+
+// local helper macro to reduce code clutter. undefined at the end of this file
+`ifndef VERILATOR
+`ifndef SYNTHESIS
+`ifndef XSIM
+`define INC_ASSERT
+`endif   
+`endif
+`endif
+
+// Converts an arbitrary block of code into a Verilog string
+`define PRIM_STRINGIFY(__x) `"__x`"
+
+// ASSERT_RPT is available to change the reporting mechanism when an assert fails
+`define ASSERT_RPT(__name)                                                  \
+`ifdef UVM                                                                  \
+  assert_rpt_pkg::assert_rpt($sformatf("[%m] %s (%s:%0d)",                  \
+                             __name, `__FILE__, `__LINE__));                \
+`else                                                                       \
+  $error("[ASSERT FAILED] [%m] %s (%s:%0d)", __name, `__FILE__, `__LINE__); \
+`endif
+
+///////////////////////////////////////
+// Simple assertion and cover macros //
+///////////////////////////////////////
+
+// Default clk and reset signals used by assertion macros below.
+`define ASSERT_DEFAULT_CLK clk_i
+`define ASSERT_DEFAULT_RST !rst_ni
+
+// Immediate assertion
+// Note that immediate assertions are sensitive to simulation glitches.
+`define ASSERT_I(__name, __prop)           \
+`ifdef INC_ASSERT                          \
+  __name: assert (__prop)                  \
+    else begin                             \
+      `ASSERT_RPT(`PRIM_STRINGIFY(__name)) \
+    end                                    \
+`endif
+
+// Assertion in initial block. Can be used for things like parameter checking.
+`define ASSERT_INIT(__name, __prop)          \
+`ifdef INC_ASSERT                            \
+  initial begin                              \
+    __name: assert (__prop)                  \
+      else begin                             \
+        `ASSERT_RPT(`PRIM_STRINGIFY(__name)) \
+      end                                    \
+  end                                        \
+`endif
+
+// Assertion in final block. Can be used for things like queues being empty
+// at end of sim, all credits returned at end of sim, state machines in idle
+// at end of sim.
+`define ASSERT_FINAL(__name, __prop)                                         \
+`ifdef INC_ASSERT                                                            \
+  final begin                                                                \
+    __name: assert (__prop || $test$plusargs("disable_assert_final_checks")) \
+      else begin                                                             \
+        `ASSERT_RPT(`PRIM_STRINGIFY(__name))                                 \
+      end                                                                    \
+  end                                                                        \
+`endif
+
+// Assert a concurrent property directly.
+// It can be called as a module (or interface) body item.
+`define ASSERT(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \
+`ifdef INC_ASSERT                                                                        \
+  __name: assert property (@(posedge __clk) disable iff ((__rst) !== '0) (__prop))       \
+    else begin                                                                           \
+      `ASSERT_RPT(`PRIM_STRINGIFY(__name))                                               \
+    end                                                                                  \
+`endif
+// Note: Above we use (__rst !== '0) in the disable iff statements instead of
+// (__rst == '1).  This properly disables the assertion in cases when reset is X at
+// the beginning of a simulation. For that case, (reset == '1) does not disable the
+// assertion.
+
+// Assert a concurrent property NEVER happens
+`define ASSERT_NEVER(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \
+`ifdef INC_ASSERT                                                                              \
+  __name: assert property (@(posedge __clk) disable iff ((__rst) !== '0) not (__prop))         \
+    else begin                                                                                 \
+      `ASSERT_RPT(`PRIM_STRINGIFY(__name))                                                     \
+    end                                                                                        \
+`endif
+
+// Assert that signal has a known value (each bit is either '0' or '1') after reset.
+// It can be called as a module (or interface) body item.
+`define ASSERT_KNOWN(__name, __sig, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \
+`ifdef INC_ASSERT                                                                             \
+  `ASSERT(__name, !$isunknown(__sig), __clk, __rst)                                           \
+`endif
+
+//  Cover a concurrent property
+`define COVER(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \
+`ifdef INC_ASSERT                                                                       \
+  __name: cover property (@(posedge __clk) disable iff ((__rst) !== '0) (__prop));      \
+`endif
+
+//////////////////////////////
+// Complex assertion macros //
+//////////////////////////////
+
+// Assert that signal is an active-high pulse with pulse length of 1 clock cycle
+`define ASSERT_PULSE(__name, __sig, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \
+`ifdef INC_ASSERT                                                                             \
+  `ASSERT(__name, $rose(__sig) |=> !(__sig), __clk, __rst)                                    \
+`endif
+
+// Assert that a property is true only when an enable signal is set.  It can be called as a module
+// (or interface) body item.
+`define ASSERT_IF(__name, __prop, __enable, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \
+`ifdef INC_ASSERT                                                                                     \
+  `ASSERT(__name, (__enable) |-> (__prop), __clk, __rst)                                              \
+`endif
+
+// Assert that signal has a known value (each bit is either '0' or '1') after reset if enable is
+// set.  It can be called as a module (or interface) body item.
+`define ASSERT_KNOWN_IF(__name, __sig, __enable, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \
+`ifdef INC_ASSERT                                                                                          \
+  `ASSERT_KNOWN(__name``KnownEnable, __enable, __clk, __rst)                                               \
+  `ASSERT_IF(__name, !$isunknown(__sig), __enable, __clk, __rst)                                           \
+`endif
+
+///////////////////////
+// Assumption macros //
+///////////////////////
+
+// Assume a concurrent property
+`define ASSUME(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \
+`ifdef INC_ASSERT                                                                        \
+  __name: assume property (@(posedge __clk) disable iff ((__rst) !== '0) (__prop))       \
+    else begin                                                                           \
+      `ASSERT_RPT(`PRIM_STRINGIFY(__name))                                               \
+    end                                                                                  \
+`endif
+
+// Assume an immediate property
+`define ASSUME_I(__name, __prop)           \
+`ifdef INC_ASSERT                          \
+  __name: assume (__prop)                  \
+    else begin                             \
+      `ASSERT_RPT(`PRIM_STRINGIFY(__name)) \
+    end                                    \
+`endif
+
+//////////////////////////////////
+// For formal verification only //
+//////////////////////////////////
+
+// Note that the existing set of ASSERT macros specified above shall be used for FPV,
+// thereby ensuring that the assertions are evaluated during DV simulations as well.
+
+// ASSUME_FPV
+// Assume a concurrent property during formal verification only.
+`define ASSUME_FPV(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \
+`ifdef FPV_ON                                                                                \
+   `ASSUME(__name, __prop, __clk, __rst)                                                     \
+`endif
+
+// ASSUME_I_FPV
+// Assume a concurrent property during formal verification only.
+`define ASSUME_I_FPV(__name, __prop) \
+`ifdef FPV_ON                        \
+   `ASSUME_I(__name, __prop)         \
+`endif
+
+// COVER_FPV
+// Cover a concurrent property during formal verification
+`define COVER_FPV(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \
+`ifdef FPV_ON                                                                               \
+   `COVER(__name, __prop, __clk, __rst)                                                     \
+`endif
+
+`endif // PRIM_ASSERT_SV