[ImportVerilog] add real literal support, refine real type, and add real format support #8020
+122
−14
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This PR is aimed to support systemverilog real, shortreal, realtime, and there conversion and operation.
One thing I'm not so sure about is that
why this opbase just support SimpleBitVectorType? is there any shortcoming to just convert it to a UnpackedType? I also want to use this OpBase support float point operation.