format + remove debug prints

intel · Dec 6, 2024 · efc8e2a · efc8e2a
1 parent 0563ba6
commit efc8e2a
Showing 1 changed file with 6 additions and 8 deletions.
diff --git a/third_party/intel/lib/TritonIntelGPUTransforms/AccelerateMatmul.cpp b/third_party/intel/lib/TritonIntelGPUTransforms/AccelerateMatmul.cpp
@@ -64,7 +64,6 @@ getWarpsPerTile(tt::DotOp dotOp,
       ceil<uint32_t>(dpasCap.repeatCount, dpasCap.executionSize);
   uint32_t colRowRatio =
       ceil<uint32_t>(dpasCap.executionSize, dpasCap.repeatCount);
-  llvm::errs() << "rowColRation: " << rowColRatio << ", colRowRatio: " << colRowRatio << ", ret: " << ret[0] << ", " << ret[1] << "\n";
 
   int rowDim = order[rank - 2], colDim = order[rank - 1];
   do {
@@ -119,20 +118,19 @@ class BlockedToDPAS : public OpRewritePattern<tt::DotOp> {
     unsigned opsPerChan =
         ttg::intel::DpasEncodingAttr::getOpsPerChannel(elemType);
 
-    SmallVector<unsigned> order = {0, 1}; 
+    SmallVector<unsigned> order = {0, 1};
     Operation *aOp = a.getDefiningOp();
     if (isa<ttg::ConvertLayoutOp>(aOp)) {
-        auto valueToConvert = aOp->getOperand(0);
-        aOp = valueToConvert.getDefiningOp();
+      auto valueToConvert = aOp->getOperand(0);
+      aOp = valueToConvert.getDefiningOp();
     }
     if (aOp && isa<tt::LoadOp>(aOp)) {
       Attribute layout;
-        assert(aOp->getNumResults() == 1);
-        layout =
-            cast<RankedTensorType>(aOp->getResult(0).getType()).getEncoding();
+      assert(aOp->getNumResults() == 1);
+      layout =
+          cast<RankedTensorType>(aOp->getResult(0).getType()).getEncoding();
       order = triton::gpu::getOrder(layout);
     }
-    llvm::errs() << "order: " << order[0] << ", " << order[1] << "\n";
 
     SmallVector<unsigned> warpsPerTile =
         getWarpsPerTile(dotOp, dpasCap, retShape, numWarps, order);