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FirstFPGA
sudo apt install openjdk-8-jdk
echo "deb https://dl.bintray.com/sbt/debian /" | sudo tee -a /etc/apt/sources.list.d/sbt.list
sudo apt-key adv --keyserver hkp://keyserver.ubuntu.com:80 --recv 2EE0EA64E40A89B84B2DF73499E82A75642AC823
sudo apt-get update
sudo apt-get install sbt
First, install packages which Verilator depends on. Run following command on Terminal.
sudo apt-get install git make autoconf g++ flex bison
Clone Git repository of Verilator, checkout 3.922.
git clone http://git.veripool.org/git/verilator
cd verilator
git pull
git checkout -b verilator_3_922 refs/tags/verilator_3_922
Build Verilator, and then install it.
unset VERILATOR_ROOT
autoconf
./configure
make
sudo make install
Download Vivado from Xilinx Downloads
make the installer executable, and run it as following example
cd ~/Downloads
chmod +x Xilinx_Vivado_SDK_Web_2018.2_0614_1954_Lin64.bin
sudo ./Xilinx_Vivado_SDK_Web_2018.2_0614_1954_Lin64.bin
When installation is completed, add the following to the ~ /.bachrc file.
source /opt/Xilinx/Vivado/2018.2/settings64.sh
alias xsdk='env SWT_GTK3=0 xsdk'
alias vivado='env SWT_GTK3=0 vivado'
Finally install the driver.
cd /opt/Xilinx/Vivado/2018.2/data/xicom/cable_drivers/lin64/install_script/install_drivers/
sudo ./install_drivers
There are the board files used by Vivado to add support for Digilent system boards. Download, and copy to the directory of Vivad board file difinition.
cd ~/Downloads/
unzip vivado-boards-master.zip
cd vivado-boards-master/new/board_files/
sudo cp -r * /opt/Xilinx/Vivado/2018.2/data/boards/board_files/
We need a constraint file that define mapping our configuration of FPGA circuite to the port of FPGA chip. We can get the template of it from GitHub of Digilent. Download Nexys-4-DDR-Master.xdc file.
There is a starter template for Chisel programing on GitHub. We clone and modify.
mkdir ~/ChiselProjects
cd ~/ChiselProjects
git clone https://github.com/ucb-bar/chisel-template.git LightLED
cd LightLED