initial commit

.project

@@ -0,0 +1,45 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>Mojo-Demo</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>net.sourceforge.veditor.simulateBuilder</name>
+			<arguments>
+				<dictionary>
+					<key>net.sourceforge.veditor.simulateBuilder.00000000Default.CleanCommand</key>
+					<value>echo &apos;Clean&apos;</value>
+				</dictionary>
+				<dictionary>
+					<key>net.sourceforge.veditor.simulateBuilder.00000000Default.buildOrder</key>
+					<value>0</value>
+				</dictionary>
+				<dictionary>
+					<key>net.sourceforge.veditor.simulateBuilder.00000000Default.command</key>
+					<value>echo &apos;No Build Configuration Specified&apos;</value>
+				</dictionary>
+				<dictionary>
+					<key>net.sourceforge.veditor.simulateBuilder.00000000Default.enable</key>
+					<value>false</value>
+				</dictionary>
+				<dictionary>
+					<key>net.sourceforge.veditor.simulateBuilder.00000000Default.name</key>
+					<value>Default</value>
+				</dictionary>
+				<dictionary>
+					<key>net.sourceforge.veditor.simulateBuilder.00000000Default.parser</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>net.sourceforge.veditor.simulateBuilder.00000000Default.workFolder</key>
+					<value></value>
+				</dictionary>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>net.sourceforge.veditor.HdlNature</nature>
+	</natures>
+</projectDescription>

LICENSE.txt

@@ -0,0 +1,22 @@
+The MIT License (MIT)
+
+Copyright (c) 2018 Dormando
+Copyright (c) 2015 Embedded Micro
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.

ipcore_dir/coregen.cgp

@@ -0,0 +1,9 @@
+SET busformat = BusFormatAngleBracketNotRipped
+SET designentry = Verilog
+SET device = xc6slx9
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET package = tqg144
+SET speedgrade = -2
+SET verilogsim = true
+SET vhdlsim = false

ipcore_dir/div_8_dot_8_nodsp.asy

@@ -0,0 +1,41 @@
+Version 4
+SymbolType BLOCK
+TEXT 32 32 LEFT 4 div_8_dot_8_nodsp
+RECTANGLE Normal 32 32 608 576
+LINE Normal 0 80 32 80
+PIN 0 80 LEFT 36
+PINATTR PinName s_axis_dividend_tvalid
+PINATTR Polarity IN
+LINE Normal 0 112 32 112
+PIN 0 112 LEFT 36
+PINATTR PinName s_axis_dividend_tready
+PINATTR Polarity OUT
+LINE Wide 0 144 32 144
+PIN 0 144 LEFT 36
+PINATTR PinName s_axis_dividend_tdata[23:0]
+PINATTR Polarity IN
+LINE Normal 0 272 32 272
+PIN 0 272 LEFT 36
+PINATTR PinName s_axis_divisor_tvalid
+PINATTR Polarity IN
+LINE Normal 0 304 32 304
+PIN 0 304 LEFT 36
+PINATTR PinName s_axis_divisor_tready
+PINATTR Polarity OUT
+LINE Wide 0 336 32 336
+PIN 0 336 LEFT 36
+PINATTR PinName s_axis_divisor_tdata[15:0]
+PINATTR Polarity IN
+LINE Normal 0 464 32 464
+PIN 0 464 LEFT 36
+PINATTR PinName aclk
+PINATTR Polarity IN
+LINE Normal 640 80 608 80
+PIN 640 80 RIGHT 36
+PINATTR PinName m_axis_dout_tvalid
+PINATTR Polarity OUT
+LINE Wide 640 144 608 144
+PIN 640 144 RIGHT 36
+PINATTR PinName m_axis_dout_tdata[39:0]
+PINATTR Polarity OUT
+

ipcore_dir/div_8_dot_8_nodsp.gise

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+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <!--                                                          -->
+
+  <!--             For tool use only. Do not edit.              -->
+
+  <!--                                                          -->
+
+  <!-- ProjectNavigator created generated project file.         -->
+
+  <!-- For use in tracking generated file and other information -->
+
+  <!-- allowing preservation of process status.                 -->
+
+  <!--                                                          -->
+
+  <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
+
+  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="div_8_dot_8_nodsp.xise"/>
+
+  <files xmlns="http://www.xilinx.com/XMLSchema">
+    <file xil_pn:fileType="FILE_ASY" xil_pn:name="div_8_dot_8_nodsp.asy" xil_pn:origination="imported"/>
+    <file xil_pn:fileType="FILE_VEO" xil_pn:name="div_8_dot_8_nodsp.veo" xil_pn:origination="imported"/>
+  </files>
+
+  <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+
+</generated_project>