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CHIPS Alliance

Common Hardware for Interfaces, Processors and Systems

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🔗 chipsalliance.org | 📫 info@chipsalliance.org

The CHIPS Alliance develops high-quality, open source hardware designs and tools relevant to ASICs and FPGAs. By creating an open and collaborative environment, CHIPS Alliance shares resources to lower the cost of development. Companies and individuals can work together to develop open source CPUs, various peripherals, and complex IP blocks, as well as open source hardware or software tools to accelerate the creation of more efficient and innovative chip designs.


The CHIPS Alliance hosts multiple open source Projects, which are Workgroups.

Popular repositories Loading

  1. chisel chisel Public

    Chisel: A Modern Hardware Design Language

    Scala 4.1k 609

  2. rocket-chip rocket-chip Public

    Rocket Chip Generator

    Scala 3.3k 1.1k

  3. verible verible Public

    Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

    C++ 1.4k 217

  4. riscv-dv riscv-dv Public

    Random instruction generator for RISC-V processor verification

    Python 1k 332

  5. Cores-VeeR-EH1 Cores-VeeR-EH1 Public

    VeeR EH1 core

    SystemVerilog 833 222

  6. firrtl firrtl Public archive

    Flexible Intermediate Representation for RTL

    Scala 732 177

Repositories

Showing 10 of 110 repositories
  • Cores-VeeR-EL2 Public

    VeeR EL2 Core

    chipsalliance/Cores-VeeR-EL2’s past year of commit activity
    SystemVerilog 255 Apache-2.0 76 21 10 Updated Jan 4, 2025
  • chisel Public

    Chisel: A Modern Hardware Design Language

    chipsalliance/chisel’s past year of commit activity
    Scala 4,069 Apache-2.0 609 315 (1 issue needs help) 166 Updated Jan 4, 2025
  • sv-tests-results Public

    Output of the sv-tests runs.

    chipsalliance/sv-tests-results’s past year of commit activity
    HTML 5 1 0 0 Updated Jan 4, 2025
  • caliptra-rtl Public

    HW Design Collateral for Caliptra RoT IP

    chipsalliance/caliptra-rtl’s past year of commit activity
    SystemVerilog 79 Apache-2.0 41 75 16 Updated Jan 4, 2025
  • sv-tests Public

    Test suite designed to check compliance with the SystemVerilog standard.

    chipsalliance/sv-tests’s past year of commit activity
    SystemVerilog 305 ISC 75 46 (5 issues need help) 22 Updated Jan 4, 2025
  • adams-bridge Public

    Post-Quantum Cryptography IP Core (Crystals-Dilithium)

    chipsalliance/adams-bridge’s past year of commit activity
    SystemVerilog 13 Apache-2.0 2 11 2 Updated Jan 3, 2025
  • caliptra-mcu-sw Public

    Caliptra MCU Software

    chipsalliance/caliptra-mcu-sw’s past year of commit activity
    Rust 5 Apache-2.0 1 2 5 Updated Jan 3, 2025
  • caliptra-sw Public

    Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test

    chipsalliance/caliptra-sw’s past year of commit activity
    Rust 99 Apache-2.0 46 109 56 Updated Jan 3, 2025
  • chipsalliance/website-experiments’s past year of commit activity
    HTML 0 1 0 0 Updated Jan 3, 2025
  • t1 Public
    chipsalliance/t1’s past year of commit activity
    Scala 125 Apache-2.0 23 16 24 Updated Jan 3, 2025