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abhijit-gadekar/README.md

Hi there, I'm Abhijit Gadekar 👋

Welcome to my GitHub profile! I'm a VLSI and Semiconductors Enthusiast with a strong interest in Digital Circuit Design. Here, you’ll find projects, resources, and insights focused on Digital Circuits, VHDL, Verilog and SystemVerilog

My goal is to provide valuable content that helps others learn and grow in digital design. Let’s connect, collaborate, and advance our skills in the fascinating world of digital hardware together!

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🛠 Technologies & Tools

Verilog VHDL FPGA Machine Learning Git C C++ Xilinx Vivado

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  1. RTL-Projects RTL-Projects Public

    "RTL-Projects" is a personal project to learn about digital design using hardware descriptive languages like VHDL, Verilog, and System Verilog.

    VHDL 1