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Added Testbench for main module
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Tiago-o-Oliveira authored Sep 3, 2023
1 parent 520d6e6 commit 0935160
Showing 1 changed file with 26 additions and 0 deletions.
26 changes: 26 additions & 0 deletions Quartus/Pwm_Modulator_TB.v
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`timescale 10ns/10ns
module Pwm_Modulator_TB();

reg ClkOsc,Rst;
wire Out_Pwm;

Pwm_Modulator DUT(
.ClkOsc(ClkOsc),
.Rst(Rst),
.Out_Pwm(Out_Pwm)
);

initial begin
Rst <= 1'b1;
ClkOsc <= 1'b0;
Rst <= 1'b0;
#2 Rst <= 1'b1;
#1000000000 $stop;
end

always begin
#100 ClkOsc <= ~ClkOsc;
end


endmodule

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