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fix(Unprivileged): wait a cycle to update time when nextV =/= v #4132

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Jan 5, 2025
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Original file line number Diff line number Diff line change
Expand Up @@ -153,7 +153,9 @@ trait Unprivileged { self: NewCSR with MachineLevel with SupervisorLevel =>

// Update when rtc clock tick and not dcsr.STOPTIME
// or virtual mode changed
when(mHPM.time.valid && !debugModeStopTime || this.nextV =/= this.v) {
// Note: we delay a cycle and use `v` for better timing
val virtModeChanged = RegNext(nextV =/= v, false.B)
when(mHPM.time.valid && !debugModeStopTime || virtModeChanged) {
reg.time := Mux(v, vstimeTmp, stimeTmp)
}.otherwise {
reg := reg
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