feat(TopDown): add TopDown PMU Events #4122
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linjuanZ
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Ivyfeather
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remember to merge the changes in submodules into their masters first a PR in XiangShan must have all its submodules checked-out to their masters (otherwise CI would fail) |
Tang-Haojin
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I don't understand. This PR does not distinguish frontend latency from bandwidth. Frontend latency is a counter that increases by 1 every time the decode bandwidth is not full. This does not make sense to me. |
* commit: 90aaf5935206ff322e461c3d021436c20dd0ac85 Including: * fix(ClockGate): avoid unused BlackBox modules (#184) * feat(TopDown): add l3Miss IO for Top-Down
* commmit: 0f9f93515853e66b8b1480fbe3f73508b1e270cc Including: * fix(MSHR): always clear meta.dirty on CMO Release (#313) * feat(MSHR): support WriteEvictOrEvict on eviction (#311) * style(Message): more robust issue isolation (#315) * feat(TopDown): add l2Miss IO for Top-Down * submodule(Huancun): bump Huancun
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[Generated by IPC robot]
master branch:
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This PR adds hardware synthesizable three-level categorized TopDown performance counters.
Level-1: Retiring, Frontend Bound, Bad Speculation, Backend Bound.
Level-2: Fetch Latency Bound, Fetch Bandwidth Bound, Branch Missprediction, machine clears, Core Bound, Memory Bound.
Leval-3: L1 Bound, L2 Bound, L3 Bound, Mem Bound, Store Bound.