submodule(CoupledL2): bump CoupledL2 (#4140)

1. OpenXiangShan/CoupledL2#309 2. OpenXiangShan/CoupledL2#312
OpenXiangShan · Jan 7, 2025 · 77733a7 · 77733a7
1 parent da51a7a
commit 77733a7
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Showing 2 changed files with 2 additions and 3 deletions.
diff --git a/coupledL2 b/coupledL2
diff --git a/src/main/scala/xiangshan/L2Top.scala b/src/main/scala/xiangshan/L2Top.scala
@@ -28,7 +28,7 @@ import coupledL2.{L2ParamKey, EnableCHI}
 import coupledL2.tl2tl.TL2TLCoupledL2
 import coupledL2.tl2chi.{TL2CHICoupledL2, PortIO, CHIIssue}
 import huancun.BankBitsKey
-import system.{HasSoCParameter, SoCParamsKey}
+import system.HasSoCParameter
 import top.BusPerfMonitor
 import utility._
 import xiangshan.cache.mmu.TlbRequestIO
@@ -105,7 +105,6 @@ class L2TopInlined()(implicit p: Parameters) extends LazyModule
     val config = new Config((_, _, _) => {
       case L2ParamKey => coreParams.L2CacheParamsOpt.get.copy(
         hartId = p(XSCoreParamsKey).HartId,
-        PmemRanges = p(SoCParamsKey).PmemRanges,
         FPGAPlatform = debugOpts.FPGAPlatform
       )
       case EnableCHI => p(EnableCHI)
+5 −2		src/main/scala/coupledL2/Common.scala
+0 −3		src/main/scala/coupledL2/CoupledL2.scala
+0 −2		src/main/scala/coupledL2/L2Param.scala
+23 −38		src/main/scala/coupledL2/prefetch/BestOffsetPrefetch.scala
+27 −9		src/main/scala/coupledL2/tl2chi/MSHR.scala
+3 −2		src/main/scala/coupledL2/tl2chi/MainPipe.scala
+5 −5		src/main/scala/coupledL2/tl2chi/RXSNP.scala
+8 −0		src/main/scala/coupledL2/tl2chi/chi/Opcode.scala
+1 −0		src/main/scala/coupledL2/tl2tl/MSHR.scala
+3 −2		src/main/scala/coupledL2/tl2tl/MainPipe.scala
+2 −2		src/main/scala/coupledL2/tl2tl/SinkB.scala