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timing(LoadUnit): fpWen and pdest reg out #9952

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timing(LoadUnit): fpWen and pdest reg out

timing(LoadUnit): fpWen and pdest reg out #9952

Triggered via pull request January 7, 2025 08:03
@cz4ecz4e
synchronize #4144
timing-fpwen-pdest-regout
Status Failure
Total duration 49m 58s
Artifacts –

emu.yml

on: pull_request
Changes Detection
6s
Changes Detection
Generate Verilog
41m 17s
Generate Verilog
EMU - Basics
49m 34s
EMU - Basics
EMU - CHI
25m 45s
EMU - CHI
EMU - Performance
48m 59s
EMU - Performance
EMU - MC
43m 52s
EMU - MC
SIMV - Basics
44m 44s
SIMV - Basics
Check Submodules
42s
Check Submodules
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6 errors and 3 warnings
EMU - CHI
Process completed with exit code 1.
Generate Verilog
Process completed with exit code 1.
EMU - MC
Process completed with exit code 2.
SIMV - Basics
Process completed with exit code 1.
EMU - Performance
Process completed with exit code 2.
EMU - Basics
Process completed with exit code 2.
Changes Detection
ubuntu-latest pipelines will use ubuntu-24.04 soon. For more details, see https://github.com/actions/runner-images/issues/10636
Changes Detection
Unexpected input(s) 'predicate-quantifier', valid inputs are ['token', 'working-directory', 'ref', 'base', 'filters', 'list-files', 'initial-fetch-depth']
Check Submodules
ubuntu-latest pipelines will use ubuntu-24.04 soon. For more details, see https://github.com/actions/runner-images/issues/10636