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timing(LoadUnit): fpWen and pdest reg out #9948

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timing(LoadUnit): fpWen and pdest reg out

timing(LoadUnit): fpWen and pdest reg out #9948

Re-run triggered January 7, 2025 06:56
@cz4ecz4e
#4144
timing-fpwen-pdest-regout
Status Failure
Total duration 2h 47m 31s
Artifacts –

emu.yml

on: pull_request
Changes Detection
4s
Changes Detection
Generate Verilog
37m 46s
Generate Verilog
EMU - Basics
1h 3m
EMU - Basics
EMU - CHI
42m 54s
EMU - CHI
EMU - Performance
2h 47m
EMU - Performance
EMU - MC
58m 19s
EMU - MC
SIMV - Basics
34m 59s
SIMV - Basics
Check Submodules
32s
Check Submodules
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6 errors and 3 warnings
SIMV - Basics
Process completed with exit code 1.
Generate Verilog
Process completed with exit code 1.
EMU - CHI
Process completed with exit code 1.
EMU - MC
Process completed with exit code 2.
EMU - Basics
Process completed with exit code 2.
EMU - Performance
Process completed with exit code 2.
Changes Detection
ubuntu-latest pipelines will use ubuntu-24.04 soon. For more details, see https://github.com/actions/runner-images/issues/10636
Changes Detection
Unexpected input(s) 'predicate-quantifier', valid inputs are ['token', 'working-directory', 'ref', 'base', 'filters', 'list-files', 'initial-fetch-depth']
Check Submodules
ubuntu-latest pipelines will use ubuntu-24.04 soon. For more details, see https://github.com/actions/runner-images/issues/10636