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Change instructions to 64-bit set
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@wkwiatek
wkwiatek committed Dec 10, 2024
1 parent 7bda3fb commit 15d9b91
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Showing 2 changed files with 162 additions and 108 deletions.
70 changes: 49 additions & 21 deletions src/packages/pvm/pvm/assemblify.ts
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Original file line number Diff line number Diff line change
Expand Up @@ -12,10 +12,13 @@ const instructionsWithoutArgs: InstructionTuple[] = [

const instructionsWithOneImmediate: InstructionTuple[] = [[Instruction.ECALLI, 1]];

const instructionsWithOneRegisterAndOneExtendedWidthImmediate: InstructionTuple[] = [[Instruction.LOAD_IMM_64, 1]];

const instructionsWithTwoImmediates: InstructionTuple[] = [
[Instruction.STORE_IMM_U8, 1],
[Instruction.STORE_IMM_U16, 1],
[Instruction.STORE_IMM_U32, 1],
[Instruction.STORE_IMM_U64, 1],
];

const instructionsWithOneOffset: InstructionTuple[] = [[Instruction.JUMP, 1]];
Expand All @@ -28,15 +31,19 @@ const instructionsWithOneRegisterAndOneImmediate: InstructionTuple[] = [
[Instruction.LOAD_U16, 1],
[Instruction.LOAD_I16, 1],
[Instruction.LOAD_U32, 1],
[Instruction.LOAD_I32, 1],
[Instruction.LOAD_U64, 1],
[Instruction.STORE_U8, 1],
[Instruction.STORE_U16, 1],
[Instruction.STORE_U32, 1],
[Instruction.STORE_U64, 1],
];

const instructionsWithOneRegisterAndTwoImmediate: InstructionTuple[] = [
[Instruction.STORE_IMM_IND_U8, 1],
[Instruction.STORE_IMM_IND_U16, 1],
[Instruction.STORE_IMM_IND_U32, 1],
[Instruction.STORE_IMM_IND_U64, 1],
];

const instructionsWithOneRegisterOneImmediateAndOneOffset: InstructionTuple[] = [
Expand All @@ -62,31 +69,41 @@ const instructionsWithTwoRegistersAndOneImmediate: InstructionTuple[] = [
[Instruction.STORE_IND_U8, 1],
[Instruction.STORE_IND_U16, 1],
[Instruction.STORE_IND_U32, 1],
[Instruction.STORE_IND_U64, 1],
[Instruction.LOAD_IND_U8, 1],
[Instruction.LOAD_IND_I8, 1],
[Instruction.LOAD_IND_U16, 1],
[Instruction.LOAD_IND_I16, 1],
[Instruction.LOAD_IND_U32, 1],
[Instruction.ADD_IMM, 1],
[Instruction.LOAD_IND_I32, 1],
[Instruction.LOAD_IND_U64, 1],
[Instruction.ADD_IMM_32, 1],
[Instruction.AND_IMM, 1],
[Instruction.XOR_IMM, 1],
[Instruction.OR_IMM, 1],
[Instruction.MUL_IMM, 1],
[Instruction.MUL_UPPER_S_S_IMM, 1],
[Instruction.MUL_UPPER_U_U_IMM, 1],
[Instruction.MUL_IMM_32, 1],
[Instruction.SET_LT_U_IMM, 1],
[Instruction.SET_LT_S_IMM, 1],
[Instruction.SHLO_L_IMM, 1],
[Instruction.SHLO_R_IMM, 1],
[Instruction.SHAR_R_IMM, 1],
[Instruction.NEG_ADD_IMM, 1],
[Instruction.SHLO_L_IMM_32, 1],
[Instruction.SHLO_R_IMM_32, 1],
[Instruction.SHAR_R_IMM_32, 1],
[Instruction.NEG_ADD_IMM_32, 1],
[Instruction.SET_GT_U_IMM, 1],
[Instruction.SET_GT_S_IMM, 1],
[Instruction.SHLO_L_IMM_ALT, 1],
[Instruction.SHLO_R_IMM_ALT, 1],
[Instruction.SHAR_R_IMM_ALT, 1],
[Instruction.SHLO_L_IMM_ALT_32, 1],
[Instruction.SHLO_R_IMM_ALT_32, 1],
[Instruction.SHAR_R_IMM_ALT_32, 1],
[Instruction.CMOV_IZ_IMM, 1],
[Instruction.CMOV_NZ_IMM, 1],
[Instruction.ADD_IMM_64, 1],
[Instruction.MUL_IMM_64, 1],
[Instruction.SHLO_L_IMM_64, 1],
[Instruction.SHLO_R_IMM_64, 1],
[Instruction.SHAR_R_IMM_64, 1],
[Instruction.NEG_ADD_IMM_64, 1],
[Instruction.SHLO_L_IMM_ALT_64, 1],
[Instruction.SHLO_R_IMM_ALT_64, 1],
[Instruction.SHAR_R_IMM_ALT_64, 1],
];

const instructionsWithTwoRegistersAndOneOffset: InstructionTuple[] = [
Expand All @@ -101,24 +118,34 @@ const instructionsWithTwoRegistersAndOneOffset: InstructionTuple[] = [
const instructionWithTwoRegistersAndTwoImmediates: InstructionTuple[] = [[Instruction.LOAD_IMM_JUMP_IND, 1]];

const instructionsWithThreeRegisters: InstructionTuple[] = [
[Instruction.ADD, 1],
[Instruction.SUB, 1],
[Instruction.ADD_32, 1],
[Instruction.SUB_32, 1],
[Instruction.MUL_32, 1],
[Instruction.DIV_U_32, 1],
[Instruction.DIV_S_32, 1],
[Instruction.REM_U_32, 1],
[Instruction.REM_S_32, 1],
[Instruction.SHLO_L_32, 1],
[Instruction.SHLO_R_32, 1],
[Instruction.SHAR_R_32, 1],
[Instruction.ADD_64, 1],
[Instruction.SUB_64, 1],
[Instruction.MUL_64, 1],
[Instruction.DIV_U_64, 1],
[Instruction.DIV_S_64, 1],
[Instruction.REM_U_64, 1],
[Instruction.REM_S_64, 1],
[Instruction.SHLO_L_64, 1],
[Instruction.SHLO_R_64, 1],
[Instruction.SHAR_R_64, 1],
[Instruction.AND, 1],
[Instruction.XOR, 1],
[Instruction.OR, 1],
[Instruction.MUL, 1],
[Instruction.MUL_UPPER_S_S, 1],
[Instruction.MUL_UPPER_U_U, 1],
[Instruction.MUL_UPPER_S_U, 1],
[Instruction.DIV_U, 1],
[Instruction.DIV_S, 1],
[Instruction.REM_U, 1],
[Instruction.REM_S, 1],
[Instruction.SET_LT_U, 1],
[Instruction.SET_LT_S, 1],
[Instruction.SHLO_L, 1],
[Instruction.SHLO_R, 1],
[Instruction.SHAR_R, 1],
[Instruction.CMOV_IZ, 1],
[Instruction.CMOV_NZ, 1],
];
Expand All @@ -136,6 +163,7 @@ const instructions: InstructionTuple[] = [
...instructionsWithTwoRegistersAndOneOffset,
...instructionWithTwoRegistersAndTwoImmediates,
...instructionsWithThreeRegisters,
...instructionsWithOneRegisterAndOneExtendedWidthImmediate,
];

type OpCode = {
Expand Down
200 changes: 113 additions & 87 deletions src/packages/pvm/pvm/instruction.ts
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Original file line number Diff line number Diff line change
@@ -1,92 +1,118 @@
export enum Instruction {
TRAP = 0,
FALLTHROUGH = 17,
JUMP = 5,
JUMP_IND = 19,
LOAD_IMM = 4,
LOAD_U8 = 60,
LOAD_I8 = 74,
LOAD_U16 = 76,
LOAD_I16 = 66,
LOAD_U32 = 10,
STORE_U8 = 71,
STORE_U16 = 69,
STORE_U32 = 22,
STORE_IMM_IND_U8 = 26,
STORE_IMM_IND_U16 = 54,
STORE_IMM_IND_U32 = 13,
LOAD_IMM_JUMP = 6,
BRANCH_EQ_IMM = 7,
BRANCH_NE_IMM = 15,
BRANCH_LT_U_IMM = 44,
BRANCH_LE_U_IMM = 59,
BRANCH_GE_U_IMM = 52,
BRANCH_GT_U_IMM = 50,
BRANCH_LT_S_IMM = 32,
BRANCH_LE_S_IMM = 46,
BRANCH_GE_S_IMM = 45,
BRANCH_GT_S_IMM = 53,
MOVE_REG = 82,
SBRK = 87,
STORE_IND_U8 = 16,
STORE_IND_U16 = 29,
STORE_IND_U32 = 3,
LOAD_IND_U8 = 11,
LOAD_IND_I8 = 21,
LOAD_IND_U16 = 37,
LOAD_IND_I16 = 33,
LOAD_IND_U32 = 1,
ADD_IMM = 2,
AND_IMM = 18,
XOR_IMM = 31,
OR_IMM = 49,
MUL_IMM = 35,
MUL_UPPER_S_S_IMM = 65,
MUL_UPPER_U_U_IMM = 63,
SET_LT_U_IMM = 27,
SET_LT_S_IMM = 56,
SHLO_L_IMM = 9,
SHLO_R_IMM = 14,
SHAR_R_IMM = 25,
NEG_ADD_IMM = 40,
SET_GT_U_IMM = 39,
SET_GT_S_IMM = 61,
SHLO_L_IMM_ALT = 75,
SHLO_R_IMM_ALT = 72,
SHAR_R_IMM_ALT = 80,
CMOV_IZ_IMM = 85,
CMOV_NZ_IMM = 86,
BRANCH_EQ = 24,
BRANCH_NE = 30,
BRANCH_LT_U = 47,
BRANCH_LT_S = 48,
BRANCH_GE_U = 41,
BRANCH_GE_S = 43,
LOAD_IMM_JUMP_IND = 42,
ADD = 8,
SUB = 20,
AND = 23,
XOR = 28,
OR = 12,
MUL = 34,
MUL_UPPER_S_S = 67,
MUL_UPPER_U_U = 57,
MUL_UPPER_S_U = 81,
DIV_U = 68,
DIV_S = 64,
REM_U = 73,
REM_S = 70,
SET_LT_U = 36,
SET_LT_S = 58,
SHLO_L = 55,
SHLO_R = 51,
SHAR_R = 77,
CMOV_IZ = 83,
CMOV_NZ = 84,
ECALLI = 78,
STORE_IMM_U8 = 62,
STORE_IMM_U16 = 79,
STORE_IMM_U32 = 38,
FALLTHROUGH = 1,
ECALLI = 10,
LOAD_IMM_64 = 20,
STORE_IMM_U8 = 30,
STORE_IMM_U16 = 31,
STORE_IMM_U32 = 32,
STORE_IMM_U64 = 33,
JUMP = 40,
JUMP_IND = 50,
LOAD_IMM = 51,
LOAD_U8 = 52,
LOAD_I8 = 53,
LOAD_U16 = 54,
LOAD_I16 = 55,
LOAD_U32 = 56,
LOAD_I32 = 57,
LOAD_U64 = 58,
STORE_U8 = 59,
STORE_U16 = 60,
STORE_U32 = 61,
STORE_U64 = 62,
STORE_IMM_IND_U8 = 70,
STORE_IMM_IND_U16 = 71,
STORE_IMM_IND_U32 = 72,
STORE_IMM_IND_U64 = 73,
LOAD_IMM_JUMP = 80,
BRANCH_EQ_IMM = 81,
BRANCH_NE_IMM = 82,
BRANCH_LT_U_IMM = 83,
BRANCH_LE_U_IMM = 84,
BRANCH_GE_U_IMM = 85,
BRANCH_GT_U_IMM = 86,
BRANCH_LT_S_IMM = 87,
BRANCH_LE_S_IMM = 88,
BRANCH_GE_S_IMM = 89,
BRANCH_GT_S_IMM = 90,
MOVE_REG = 100,
SBRK = 101,
STORE_IND_U8 = 110,
STORE_IND_U16 = 111,
STORE_IND_U32 = 112,
STORE_IND_U64 = 113,
LOAD_IND_U8 = 114,
LOAD_IND_I8 = 115,
LOAD_IND_U16 = 116,
LOAD_IND_I16 = 117,
LOAD_IND_U32 = 118,
LOAD_IND_I32 = 119,
LOAD_IND_U64 = 120,
ADD_IMM_32 = 121,
AND_IMM = 122,
XOR_IMM = 123,
OR_IMM = 124,
MUL_IMM_32 = 125,
SET_LT_U_IMM = 126,
SET_LT_S_IMM = 127,
SHLO_L_IMM_32 = 128,
SHLO_R_IMM_32 = 129,
SHAR_R_IMM_32 = 130,
NEG_ADD_IMM_32 = 131,
SET_GT_U_IMM = 132,
SET_GT_S_IMM = 133,
SHLO_L_IMM_ALT_32 = 134,
SHLO_R_IMM_ALT_32 = 135,
SHAR_R_IMM_ALT_32 = 136,
CMOV_IZ_IMM = 137,
CMOV_NZ_IMM = 138,
ADD_IMM_64 = 139,
MUL_IMM_64 = 140,
SHLO_L_IMM_64 = 141,
SHLO_R_IMM_64 = 142,
SHAR_R_IMM_64 = 143,
NEG_ADD_IMM_64 = 144,
SHLO_L_IMM_ALT_64 = 145,
SHLO_R_IMM_ALT_64 = 146,
SHAR_R_IMM_ALT_64 = 147,
BRANCH_EQ = 150,
BRANCH_NE = 151,
BRANCH_LT_U = 152,
BRANCH_LT_S = 153,
BRANCH_GE_U = 154,
BRANCH_GE_S = 155,
LOAD_IMM_JUMP_IND = 160,
ADD_32 = 170,
SUB_32 = 171,
MUL_32 = 172,
DIV_U_32 = 173,
DIV_S_32 = 174,
REM_U_32 = 175,
REM_S_32 = 176,
SHLO_L_32 = 177,
SHLO_R_32 = 178,
SHAR_R_32 = 179,
ADD_64 = 180,
SUB_64 = 181,
MUL_64 = 182,
DIV_U_64 = 183,
DIV_S_64 = 184,
REM_U_64 = 185,
REM_S_64 = 186,
SHLO_L_64 = 187,
SHLO_R_64 = 188,
SHAR_R_64 = 189,
AND = 190,
XOR = 191,
OR = 192,
MUL_UPPER_S_S = 193,
MUL_UPPER_U_U = 194,
MUL_UPPER_S_U = 195,
SET_LT_U = 196,
SET_LT_S = 197,
CMOV_IZ = 198,
CMOV_NZ = 199,
}

export const HIGHEST_INSTRUCTION_NUMBER = Instruction.SBRK;

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