Update register.v

Andreou-JHULabOrg · May 16, 2024 · 24df4f9 · 24df4f9
1 parent 0e28772
commit 24df4f9
Showing 1 changed file with 0 additions and 2 deletions.
diff --git a/src/register.v b/src/register.v
@@ -1,5 +1,3 @@
-`timescale 1ns / 1ps
-
 module register #(
     parameter WIDTH = 3  // Default width is 3 bits, but can be set when instantiated
 )(