From b811f294b62965c788b16e044a0fc528bb08620e Mon Sep 17 00:00:00 2001 From: David O'Connor Date: Mon, 1 Jun 2020 20:35:51 -0400 Subject: [PATCH 1/6] Implemented InputPin trait for output pins --- src/gpio.rs | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/src/gpio.rs b/src/gpio.rs index 1dd43ab62..aab8e6a66 100644 --- a/src/gpio.rs +++ b/src/gpio.rs @@ -398,6 +398,20 @@ macro_rules! gpio { } } + #[cfg(feature = "unproven")] + impl InputPin for $PXx> { + type Error = Infallible; + + fn is_high(&self) -> Result { + Ok(!self.is_low()?) + } + + fn is_low(&self) -> Result { + // NOTE(unsafe) atomic read with no side effects + Ok(unsafe { (*$GPIOX::ptr()).idr.read().bits() & (1 << self.i) == 0 }) + } + } + #[cfg(feature = "unproven")] impl InputPin for $PXx> { type Error = Infallible; @@ -584,6 +598,20 @@ macro_rules! gpio { } } + #[cfg(feature = "unproven")] + impl InputPin for $PXi> { + type Error = Infallible; + + fn is_high(&self) -> Result { + Ok(!self.is_low()?) + } + + fn is_low(&self) -> Result { + // NOTE(unsafe) atomic read with no side effects + Ok(unsafe { (*$GPIOX::ptr()).idr.read().bits() & (1 << $i) == 0 }) + } + } + #[cfg(feature = "unproven")] impl InputPin for $PXi> { type Error = Infallible; From 1083e2672b63781efdee41220ce4d28c193fce2d Mon Sep 17 00:00:00 2001 From: David O'Connor Date: Mon, 22 Jun 2020 01:06:57 -0400 Subject: [PATCH 2/6] Make APB1.enr public, so we can set wakeup --- src/rcc.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/rcc.rs b/src/rcc.rs index 1fb34cf11..c9cb6c690 100644 --- a/src/rcc.rs +++ b/src/rcc.rs @@ -66,7 +66,7 @@ pub struct APB1 { } impl APB1 { - pub(crate) fn enr(&mut self) -> &rcc::APB1ENR { + pub fn enr(&mut self) -> &rcc::APB1ENR { // NOTE(unsafe) this proxy grants exclusive access to this register unsafe { &(*RCC::ptr()).apb1enr } } From 2e41e92cc846d4b6996afc414ba89c3b23611d11 Mon Sep 17 00:00:00 2001 From: David O'Connor Date: Tue, 14 Jul 2020 18:18:05 -0400 Subject: [PATCH 3/6] Updated impl --- src/rcc.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/rcc.rs b/src/rcc.rs index c9cb6c690..1fb34cf11 100644 --- a/src/rcc.rs +++ b/src/rcc.rs @@ -66,7 +66,7 @@ pub struct APB1 { } impl APB1 { - pub fn enr(&mut self) -> &rcc::APB1ENR { + pub(crate) fn enr(&mut self) -> &rcc::APB1ENR { // NOTE(unsafe) this proxy grants exclusive access to this register unsafe { &(*RCC::ptr()).apb1enr } } From cad110e71f39e31cab1c0c5806a5a40904ae97c2 Mon Sep 17 00:00:00 2001 From: David O'Connor Date: Tue, 14 Jul 2020 18:20:05 -0400 Subject: [PATCH 4/6] Commit troubleshooting --- src/gpio.rs | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/src/gpio.rs b/src/gpio.rs index aab8e6a66..c88946458 100644 --- a/src/gpio.rs +++ b/src/gpio.rs @@ -206,6 +206,32 @@ macro_rules! gpio { } } + + #[cfg(feature = "unproven")] + impl InputPin for PXx> { + type Error = Infallible; + + fn is_high(&self) -> Result { + Ok(!self.is_low()?) + } + + fn is_low(&self) -> Result { + // NOTE(unsafe) atomic read with no side effects + Ok(unsafe { + match &self.gpio { + $( + #[cfg(all(any( + $(feature = $device,)+ + ), not(any( + $(feature = $device_except,)* + ))))] + Gpio::$GPIOX => (*$GPIOX::ptr()).idr.read().bits() & (1 << self.i) == 0, + )+ + } + }) + } + } + #[cfg(feature = "unproven")] impl StatefulOutputPin for PXx> { fn is_set_high(&self) -> Result { From fa02c5d5b51ca79de03cdf6ff78510a8ecacbbe2 Mon Sep 17 00:00:00 2001 From: Jan Teske Date: Fri, 17 Jul 2020 16:41:47 +0200 Subject: [PATCH 5/6] Cleanup InputPin impls for OutputPins This commit: - Makes the order of InputPin impls consistent - Impls InputPin only for Output, not the generic Output - Adjusts the register access in accordance with the recently merged GPIO refactoring (#42) - Makes rustfmt happy --- src/gpio.rs | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/src/gpio.rs b/src/gpio.rs index c88946458..4516645ae 100644 --- a/src/gpio.rs +++ b/src/gpio.rs @@ -206,9 +206,8 @@ macro_rules! gpio { } } - #[cfg(feature = "unproven")] - impl InputPin for PXx> { + impl InputPin for PXx> { type Error = Infallible; fn is_high(&self) -> Result { @@ -425,7 +424,7 @@ macro_rules! gpio { } #[cfg(feature = "unproven")] - impl InputPin for $PXx> { + impl InputPin for $PXx> { type Error = Infallible; fn is_high(&self) -> Result { @@ -439,7 +438,7 @@ macro_rules! gpio { } #[cfg(feature = "unproven")] - impl InputPin for $PXx> { + impl InputPin for $PXx> { type Error = Infallible; fn is_high(&self) -> Result { @@ -625,7 +624,7 @@ macro_rules! gpio { } #[cfg(feature = "unproven")] - impl InputPin for $PXi> { + impl InputPin for $PXi> { type Error = Infallible; fn is_high(&self) -> Result { @@ -634,12 +633,12 @@ macro_rules! gpio { fn is_low(&self) -> Result { // NOTE(unsafe) atomic read with no side effects - Ok(unsafe { (*$GPIOX::ptr()).idr.read().bits() & (1 << $i) == 0 }) + Ok(unsafe { (*$GPIOX::ptr()).idr.read().$idri().is_low()}) } } #[cfg(feature = "unproven")] - impl InputPin for $PXi> { + impl InputPin for $PXi> { type Error = Infallible; fn is_high(&self) -> Result { From 0e656a76655f3595f9a3a650721c5ef30afab8cd Mon Sep 17 00:00:00 2001 From: Jan Teske Date: Fri, 17 Jul 2020 16:52:19 +0200 Subject: [PATCH 6/6] Update changelog --- CHANGELOG.md | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 4162be2fb..513561b1e 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -7,6 +7,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/). ## [Unreleased] +### Added + +- Implement `InputPin` for `Output` pins ([#114](https://github.com/stm32-rs/stm32f3xx-hal/pull/114)) + ### Fixed - `PLL` was calculated wrong for devices, which do not divide `HSI` ([#67](https://github.com/stm32-rs/stm32f3xx-hal/pull/67)) @@ -28,7 +32,7 @@ let clocks = rcc .use_hse(32.mhz()) .sysclk(72.mhz()) ``` - This is possible through utilizing the divider, which can devide the + This is possible through utilizing the divider, which can divide the external oscillator clock on most devices. Some devices have even the possibility to divide the internal oscillator clock.