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Code coverage reports that many sections of code that are not tested are covered. For example, even if crypto tests are not run, the code coverage report shows >99% of the crypto unit being covered.
This is likely because many of the signals are toggling even when a different instruction is run. Most units are not gated based on the currently executing instruction, so this is not all that surprising. There are a few weird cases though. For example, the bit manipulation unit has the following that should keep its inputs to zero when not targeting a bit manipulation instruction, yet still has fairly high coverage without running any bit manip tests.
// gate data inputs to BMU to only operate when BMU is activeassign ABMU = A & {P.XLEN{BMUActive}};
assign BBMU = B & {P.XLEN{BMUActive}};
This might end up all being an inevitable result of how Questa collects coverage, but it is worth looking into.
The text was updated successfully, but these errors were encountered:
Code coverage was updated to use the cvw-arch-verif suite instead of riscv-arch-test. The same issue with unexpectedly high coverage is still occurring.
Code coverage reports that many sections of code that are not tested are covered. For example, even if crypto tests are not run, the code coverage report shows >99% of the crypto unit being covered.
This is likely because many of the signals are toggling even when a different instruction is run. Most units are not gated based on the currently executing instruction, so this is not all that surprising. There are a few weird cases though. For example, the bit manipulation unit has the following that should keep its inputs to zero when not targeting a bit manipulation instruction, yet still has fairly high coverage without running any bit manip tests.
This might end up all being an inevitable result of how Questa collects coverage, but it is worth looking into.
The text was updated successfully, but these errors were encountered: