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Hi Mats Brorsson. It shouldn't be too much effort to port Wally to the Genesys 2 board. I just got my hands on one of these boards last week and I am hoping to work on this later this week or next. If you are interested helping the main things which are required are as follows.
New device tree to define clock speed and memory size.
New pin mappings for all the I/O devices.
Creating a new script to generate the Xilinx IP memory controller. I think we will be able to share the same memory controller script between the Arty A7 and the Genesys 2 board by parameterizing the memory part, size, bus width, etc.
Would it be difficult to set upp support for the Genesys 2 board?
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