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target C; reactor Destination (bank_index:int = 0, name:string = "DST", n_inputs:int = 1) { input [n_inputs] req:int; output [n_inputs] rsp:int; reaction (req) -> rsp {= for (int i = 0; i < self->n_inputs; ++i) { if (req[i]->is_present) { printf ("(%lld, %u) physical_time:%lld " "%s [%d] Sending back response:%d\n", lf_time_logical_elapsed(), lf_tag().microstep, lf_time_physical_elapsed(), self->name, self->bank_index, req[i]->value ); lf_set (rsp[i], req[i]->value); } } =} } reactor Source (bank_index:int = 0, name:string = "Source") { output req:int; input rsp:int; state msg:int = 0; reaction (startup) -> req {= printf ("(%lld, %u) physical_time:%lld " "%s [%d] Scheduling request:%d\n", lf_time_logical_elapsed(), lf_tag().microstep, lf_time_physical_elapsed(), self->name, self->bank_index, self->msg ); lf_set (req, self->msg); =} reaction (rsp) {= printf ("(%lld, %u) physical_time:%lld " "%s [%d] Receiving response:%d\n", lf_time_logical_elapsed(), lf_tag().microstep, lf_time_physical_elapsed(), self->name, self->bank_index, rsp->value ); =} } reactor Selector (bank_index:int = 0, name:string = "Selector", n_ports:int = 1) { input [n_ports] in_req:int; output [n_ports] out_rsp:int; initial mode Init { reaction (startup) -> history (DST_1), history (DST_2) {= printf ("(%lld, %u) physical_time:%lld " "%s POP startup", lf_time_logical_elapsed(), lf_tag().microstep, lf_time_physical_elapsed(), self->name ); lf_set_mode(DST_1); =} } mode DST_1 { dst1 = new Destination(name = "DST_1"); in_req -> dst1.req; dst1.rsp -> out_rsp; } mode DST_2 { dst2 = new Destination(name = "DST_2"); in_req -> dst2.req; dst2.rsp -> out_rsp; } } main reactor { src = new Source(); sel = new Selector(); src.req -> sel.in_req; sel.out_rsp -> src.rsp; }
mode DST_1 and mode DST_2 have multiport destination reactor that doesn't compile.
However, if we make destination reactor single port, compilation goes fine.
target C; reactor Destination (bank_index:int = 0, name:string = "DST") { input req:int; output rsp:int; reaction (req) -> rsp {= printf ("(%lld, %u) physical_time:%lld " "%s [%d] Sending back response:%d\n", lf_time_logical_elapsed(), lf_tag().microstep, lf_time_physical_elapsed(), self->name, self->bank_index, req->value ); lf_set (rsp, req->value); =} } reactor Source (bank_index:int = 0, name:string = "Source") { output req:int; input rsp:int; state msg:int = 0; reaction (startup) -> req {= printf ("(%lld, %u) physical_time:%lld " "%s [%d] Scheduling request:%d\n", lf_time_logical_elapsed(), lf_tag().microstep, lf_time_physical_elapsed(), self->name, self->bank_index, self->msg ); lf_set (req, self->msg); =} reaction (rsp) {= printf ("(%lld, %u) physical_time:%lld " "%s [%d] Receiving response:%d\n", lf_time_logical_elapsed(), lf_tag().microstep, lf_time_physical_elapsed(), self->name, self->bank_index, rsp->value ); =} } reactor Selector (bank_index:int = 0, name:string = "Selector") { input in_req:int; output out_rsp:int; initial mode Init { reaction (startup) -> history (DST_1), history (DST_2) {= printf ("(%lld, %u) physical_time:%lld " "%s POP startup", lf_time_logical_elapsed(), lf_tag().microstep, lf_time_physical_elapsed(), self->name ); lf_set_mode(DST_1); =} } mode DST_1 { dst1 = new Destination(name = "DST_1"); in_req -> dst1.req; dst1.rsp -> out_rsp; } mode DST_2 { dst2 = new Destination(name = "DST_2"); in_req -> dst2.req; dst2.rsp -> out_rsp; } } main reactor { src = new Source(); sel = new Selector(); src.req -> sel.in_req; sel.out_rsp -> src.rsp; }
The text was updated successfully, but these errors were encountered:
Fixed in #2422.
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mode DST_1 and mode DST_2 have multiport destination reactor that doesn't compile.
However, if we make destination reactor single port, compilation goes fine.
The text was updated successfully, but these errors were encountered: