A complete memory management implementation in C.
The simulated hardware consists of a Direct-Mapped split L1 Cache (4KB, 32B block size) along with a Victim cache (8 blocks) and an 8-way Set-Associative L2 Cache (32KB, 32B block size), along with a Main Memory (32MB) module that supports multi-level paging with 2 segments. There is also an identifier based (32 Line) TLB (Translation Lookaside Buffer) associated with the core. A Working Set Strategy mechanism detects for thrashing in the system.
LRU Square Matrix method
No replacement policy since it's direct mapped.
LRU Counter method
First In First Out
LRU Sliding Window method