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Zynq Ultrascale+ (ARM Cortex A-53) Kernel 5.15.19 problem #94
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thank you for this precious issue. Please give me a little more time. I would like to ask you some questions |
I use Xilinx AXI DMA with scatter gather engine from user space. I create all data and descriptor buffers with u-dma-buf in the userspace. This space is cache coherent and dma makes cache coherent AXI bus transactions with proper port of Zynq MPSoC ps. In case of a problem with cache coherency it doesn't trigger when I send the data. It works well with previous kernel version 5.10. Only change is this system is kernel version. |
Thanks for your reply. Let me ask you a few more questions. Q1. How did you build the Linux Kernel? Petalinux? Yocto? Other? Q2. What is the output of dmesg when u-dma-buf is installed? I especially want to know the u-dma-buf version and physical address. Sorry for the inconvenience, but thank you in advance. |
Hello Q1. I build using Petalinux. [ 11.083838] u-dma-buf dma_data_buffer: driver version = 4.0.0 |
Everything compiled good with Petalinux kernel 5.15.19. I'm also creating device tree with dma-coherent property as shown below.
When i try to use it with succesfully working user DMA software with previous kernel 5.10 everything works well. However, with this 5.15.19 kernel it doesn't work. I suspect that it is caused by cache coherency because i'm using hw coherent bus of MPSOC and hardware flush or invalidates the cache over cache coherent bus. Can you help for this issue? I think proper support fr 5.15.19 will fix this issue.
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