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练习3.29 或门的延迟计算与练习3.30加法器的延迟计算 #59

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DL-85 opened this issue May 4, 2019 · 0 comments

DL-85 commented May 4, 2019 •

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这里的答案指出“整个 or-gate 共调用了三次 inverter ，一次 and-gate ，因此 or-gate 的延迟等于 3 * inverter-delay + and-gate-delay”

但前两个非门是并联关系的，它们的延迟应该不是叠加的，所以我认为or-gate的延迟等于2* inverter-delay + and-gate-delay

同理联系3.30的计算可能也有问题，半加器S的延迟为max(or, and+inverter)+and, C的延迟为and, 全加器S的延迟与半加器相同，C的延迟为max(or, and+inverter)+2and+or, 级联加法器的延迟为 n(全加器C的延迟)

不知道我的理解是否正确，望讨论下

DL-85 changed the title ~~练习3.29 或门的延迟计算~~ 练习3.29 或门的延迟计算与练习3.30加法器的延迟计算

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