From 37448d3139a7d74d943af0b002ffa9d20e9b5c97 Mon Sep 17 00:00:00 2001 From: dormando Date: Mon, 31 Dec 2018 16:37:27 -0800 Subject: [PATCH] initial commit --- .project | 45 + LICENSE.txt | 22 + Mojo-Base.xise | 511 + ipcore_dir/.gitignore | 0 ipcore_dir/coregen.cgp | 9 + ipcore_dir/div_8_dot_8_nodsp.asy | 41 + ipcore_dir/div_8_dot_8_nodsp.gise | 31 + ipcore_dir/div_8_dot_8_nodsp.ncf | 0 ipcore_dir/div_8_dot_8_nodsp.ngc | 3 + ipcore_dir/div_8_dot_8_nodsp.v | 14635 ++++++++++++++++ ipcore_dir/div_8_dot_8_nodsp.veo | 69 + ipcore_dir/div_8_dot_8_nodsp.xco | 70 + ipcore_dir/div_8_dot_8_nodsp.xise | 73 + .../doc/div_gen_v4_0_readme.txt | 164 + .../doc/div_gen_v4_0_vinfo.html | 175 + .../div_8_dot_8_nodsp/doc/ds819_div_gen.pdf | Bin 0 -> 698989 bytes ipcore_dir/div_8_dot_8_nodsp_flist.txt | 15 + ipcore_dir/div_8_dot_8_nodsp_xmdf.tcl | 83 + ipcore_dir/lcd_spi_clk.asy | 17 + ipcore_dir/lcd_spi_clk.gise | 52 + ipcore_dir/lcd_spi_clk.ncf | 59 + ipcore_dir/lcd_spi_clk.sym | 18 + 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-> 491 bytes 322 files changed, 28427 insertions(+) create mode 100644 .project create mode 100644 LICENSE.txt create mode 100644 Mojo-Base.xise create mode 100644 ipcore_dir/.gitignore create mode 100644 ipcore_dir/coregen.cgp create mode 100644 ipcore_dir/div_8_dot_8_nodsp.asy create mode 100644 ipcore_dir/div_8_dot_8_nodsp.gise create mode 100644 ipcore_dir/div_8_dot_8_nodsp.ncf create mode 100644 ipcore_dir/div_8_dot_8_nodsp.ngc create mode 100644 ipcore_dir/div_8_dot_8_nodsp.v create mode 100644 ipcore_dir/div_8_dot_8_nodsp.veo create mode 100644 ipcore_dir/div_8_dot_8_nodsp.xco create mode 100644 ipcore_dir/div_8_dot_8_nodsp.xise create mode 100644 ipcore_dir/div_8_dot_8_nodsp/doc/div_gen_v4_0_readme.txt create mode 100644 ipcore_dir/div_8_dot_8_nodsp/doc/div_gen_v4_0_vinfo.html create mode 100644 ipcore_dir/div_8_dot_8_nodsp/doc/ds819_div_gen.pdf create mode 100644 ipcore_dir/div_8_dot_8_nodsp_flist.txt create mode 100644 ipcore_dir/div_8_dot_8_nodsp_xmdf.tcl create mode 100644 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create mode 100644 texture/LAB/wall/tile126.png create mode 100644 texture/LAB/wall/tile127.png create mode 100644 texture/LAB/wall/tile128.png create mode 100644 texture/LAB/wall/tile129.png create mode 100644 texture/LAB/wall/tile130.png create mode 100644 texture/LAB/wall/tile131.png create mode 100644 texture/LAB/wall/tile132.png create mode 100644 texture/LAB/wall/tile133.png diff --git a/.project b/.project new file mode 100644 index 0000000..cc05a57 --- /dev/null +++ b/.project @@ -0,0 +1,45 @@ + + + Mojo-Demo + + + + + + net.sourceforge.veditor.simulateBuilder + + + net.sourceforge.veditor.simulateBuilder.00000000Default.CleanCommand + echo 'Clean' + + + net.sourceforge.veditor.simulateBuilder.00000000Default.buildOrder + 0 + + + net.sourceforge.veditor.simulateBuilder.00000000Default.command + echo 'No Build Configuration Specified' + + + net.sourceforge.veditor.simulateBuilder.00000000Default.enable + false + + + net.sourceforge.veditor.simulateBuilder.00000000Default.name + Default + + + net.sourceforge.veditor.simulateBuilder.00000000Default.parser + + + + net.sourceforge.veditor.simulateBuilder.00000000Default.workFolder + + + + + + + net.sourceforge.veditor.HdlNature + + diff --git a/LICENSE.txt b/LICENSE.txt new file mode 100644 index 0000000..b81449c --- /dev/null +++ b/LICENSE.txt @@ -0,0 +1,22 @@ +The MIT License (MIT) + +Copyright (c) 2018 Dormando +Copyright (c) 2015 Embedded Micro + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. diff --git a/Mojo-Base.xise b/Mojo-Base.xise new file mode 100644 index 0000000..72c3956 --- /dev/null +++ b/Mojo-Base.xise @@ -0,0 +1,511 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ipcore_dir/.gitignore b/ipcore_dir/.gitignore new file mode 100644 index 0000000..e69de29 diff --git a/ipcore_dir/coregen.cgp b/ipcore_dir/coregen.cgp new file mode 100644 index 0000000..d58f8d7 --- /dev/null +++ b/ipcore_dir/coregen.cgp @@ -0,0 +1,9 @@ +SET busformat = BusFormatAngleBracketNotRipped +SET designentry = Verilog +SET device = xc6slx9 +SET devicefamily = spartan6 +SET flowvendor = Other +SET package = tqg144 +SET speedgrade = -2 +SET verilogsim = true +SET vhdlsim = false diff --git a/ipcore_dir/div_8_dot_8_nodsp.asy b/ipcore_dir/div_8_dot_8_nodsp.asy new file mode 100644 index 0000000..1ab7337 --- /dev/null +++ b/ipcore_dir/div_8_dot_8_nodsp.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 div_8_dot_8_nodsp +RECTANGLE Normal 32 32 608 576 +LINE Normal 0 80 32 80 +PIN 0 80 LEFT 36 +PINATTR PinName s_axis_dividend_tvalid +PINATTR Polarity IN +LINE Normal 0 112 32 112 +PIN 0 112 LEFT 36 +PINATTR PinName s_axis_dividend_tready +PINATTR Polarity OUT +LINE Wide 0 144 32 144 +PIN 0 144 LEFT 36 +PINATTR PinName s_axis_dividend_tdata[23:0] +PINATTR Polarity IN +LINE Normal 0 272 32 272 +PIN 0 272 LEFT 36 +PINATTR PinName s_axis_divisor_tvalid +PINATTR Polarity IN +LINE Normal 0 304 32 304 +PIN 0 304 LEFT 36 +PINATTR PinName s_axis_divisor_tready +PINATTR Polarity OUT +LINE Wide 0 336 32 336 +PIN 0 336 LEFT 36 +PINATTR PinName s_axis_divisor_tdata[15:0] +PINATTR Polarity IN +LINE Normal 0 464 32 464 +PIN 0 464 LEFT 36 +PINATTR PinName aclk +PINATTR Polarity IN +LINE Normal 640 80 608 80 +PIN 640 80 RIGHT 36 +PINATTR PinName m_axis_dout_tvalid +PINATTR Polarity OUT +LINE Wide 640 144 608 144 +PIN 640 144 RIGHT 36 +PINATTR PinName m_axis_dout_tdata[39:0] +PINATTR Polarity OUT + diff --git a/ipcore_dir/div_8_dot_8_nodsp.gise b/ipcore_dir/div_8_dot_8_nodsp.gise new file mode 100644 index 0000000..7f86268 --- /dev/null +++ b/ipcore_dir/div_8_dot_8_nodsp.gise @@ -0,0 +1,31 @@ + + + + + + + + + + + + + + + + + + + + 11.1 + + + + + + + + + + + diff --git a/ipcore_dir/div_8_dot_8_nodsp.ncf b/ipcore_dir/div_8_dot_8_nodsp.ncf new file mode 100644 index 0000000..e69de29 diff --git a/ipcore_dir/div_8_dot_8_nodsp.ngc b/ipcore_dir/div_8_dot_8_nodsp.ngc new file mode 100644 index 0000000..2f58870 --- /dev/null +++ b/ipcore_dir/div_8_dot_8_nodsp.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e 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\ No newline at end of file diff --git a/ipcore_dir/div_8_dot_8_nodsp.v b/ipcore_dir/div_8_dot_8_nodsp.v new file mode 100644 index 0000000..2c1cd76 --- /dev/null +++ b/ipcore_dir/div_8_dot_8_nodsp.v @@ -0,0 +1,14635 @@ +//////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. +//////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: P.20131013 +// \ \ Application: netgen +// / / Filename: div_8_dot_8_nodsp.v +// /___/ /\ Timestamp: Thu Nov 29 22:48:08 2018 +// \ \ / \ +// \___\/\___\ +// +// Command : -w -sim -ofmt verilog /home/dormando/p/mojo/hello-world-v/ipcore_dir/tmp/_cg/div_8_dot_8_nodsp.ngc /home/dormando/p/mojo/hello-world-v/ipcore_dir/tmp/_cg/div_8_dot_8_nodsp.v +// Device : 6slx9tqg144-2 +// Input file : /home/dormando/p/mojo/hello-world-v/ipcore_dir/tmp/_cg/div_8_dot_8_nodsp.ngc +// Output file : /home/dormando/p/mojo/hello-world-v/ipcore_dir/tmp/_cg/div_8_dot_8_nodsp.v +// # of Modules : 1 +// Design Name : div_8_dot_8_nodsp +// Xilinx : /opt/Xilinx/14.7/ISE_DS/ISE/ +// +// Purpose: +// This verilog netlist is a verification model and uses simulation +// primitives which may not represent the true implementation of the +// device, however the netlist is functionally correct and should not +// be modified. This file cannot be synthesized and should only be used +// with supported simulation tools. +// +// Reference: +// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6 +// +//////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ns/1 ps + +module div_8_dot_8_nodsp ( + aclk, s_axis_divisor_tvalid, s_axis_dividend_tvalid, s_axis_divisor_tready, s_axis_dividend_tready, m_axis_dout_tvalid, s_axis_divisor_tdata, +s_axis_dividend_tdata, m_axis_dout_tdata +)/* synthesis syn_black_box syn_noprune=1 */; + input aclk; + input s_axis_divisor_tvalid; + input s_axis_dividend_tvalid; + output s_axis_divisor_tready; + output s_axis_dividend_tready; + output m_axis_dout_tvalid; + input [15 : 0] s_axis_divisor_tdata; + input [23 : 0] s_axis_dividend_tdata; + output [39 : 0] m_axis_dout_tdata; + + // synthesis translate_off + + wire NlwRenamedSig_OI_s_axis_dividend_tready; + wire \blk00000001/sig0000073a ; + wire \blk00000001/sig00000739 ; + wire \blk00000001/sig00000738 ; + wire \blk00000001/sig00000737 ; + wire \blk00000001/sig00000736 ; + wire \blk00000001/sig00000735 ; + wire \blk00000001/sig00000734 ; + wire \blk00000001/sig00000733 ; + wire \blk00000001/sig00000732 ; + wire \blk00000001/sig00000731 ; + wire \blk00000001/sig00000730 ; + wire \blk00000001/sig0000072f ; + wire \blk00000001/sig0000072e ; + wire \blk00000001/sig0000072d ; + wire \blk00000001/sig0000072c ; + wire \blk00000001/sig0000072b ; + wire \blk00000001/sig0000072a ; + wire \blk00000001/sig00000729 ; + wire \blk00000001/sig00000728 ; + wire \blk00000001/sig00000727 ; + wire \blk00000001/sig00000726 ; + wire \blk00000001/sig00000725 ; + wire \blk00000001/sig00000724 ; + wire \blk00000001/sig00000723 ; + wire \blk00000001/sig00000722 ; + wire \blk00000001/sig00000721 ; + wire \blk00000001/sig00000720 ; + wire \blk00000001/sig0000071f ; + wire \blk00000001/sig0000071e ; + wire \blk00000001/sig0000071d ; + wire \blk00000001/sig0000071c ; + wire \blk00000001/sig0000071b ; + wire \blk00000001/sig0000071a ; + wire \blk00000001/sig00000719 ; + wire \blk00000001/sig00000718 ; + wire \blk00000001/sig00000717 ; + wire \blk00000001/sig00000716 ; + wire \blk00000001/sig00000715 ; + wire \blk00000001/sig00000714 ; + wire \blk00000001/sig00000713 ; + wire \blk00000001/sig00000712 ; + wire \blk00000001/sig00000711 ; + wire \blk00000001/sig00000710 ; + wire \blk00000001/sig0000070f ; + wire \blk00000001/sig0000070e ; + wire \blk00000001/sig0000070d ; + wire \blk00000001/sig0000070c ; + wire \blk00000001/sig0000070b ; + wire \blk00000001/sig0000070a ; + wire \blk00000001/sig00000709 ; + wire \blk00000001/sig00000708 ; + wire \blk00000001/sig00000707 ; + wire \blk00000001/sig00000706 ; + wire \blk00000001/sig00000705 ; + wire \blk00000001/sig00000704 ; + wire \blk00000001/sig00000703 ; + wire \blk00000001/sig00000702 ; + wire \blk00000001/sig00000701 ; + wire \blk00000001/sig00000700 ; + wire \blk00000001/sig000006ff ; + wire \blk00000001/sig000006fe ; + wire \blk00000001/sig000006fd ; + wire \blk00000001/sig000006fc ; + wire \blk00000001/sig000006fb ; + wire \blk00000001/sig000006fa ; + wire \blk00000001/sig000006f9 ; + wire \blk00000001/sig000006f8 ; + wire \blk00000001/sig000006f7 ; + wire \blk00000001/sig000006f6 ; + wire \blk00000001/sig000006f5 ; + wire \blk00000001/sig000006f4 ; + wire \blk00000001/sig000006f3 ; + wire \blk00000001/sig000006f2 ; + wire \blk00000001/sig000006f1 ; + wire \blk00000001/sig000006f0 ; + wire \blk00000001/sig000006ef ; + wire \blk00000001/sig000006ee ; + wire \blk00000001/sig000006ed ; + wire \blk00000001/sig000006ec ; + wire \blk00000001/sig000006eb ; + wire \blk00000001/sig000006ea ; + wire \blk00000001/sig000006e9 ; + wire \blk00000001/sig000006e8 ; + wire \blk00000001/sig000006e7 ; + wire \blk00000001/sig000006e6 ; + wire \blk00000001/sig000006e5 ; + wire \blk00000001/sig000006e4 ; + wire \blk00000001/sig000006e3 ; + wire \blk00000001/sig000006e2 ; + wire \blk00000001/sig000006e1 ; + wire \blk00000001/sig000006e0 ; + wire \blk00000001/sig000006df ; + wire \blk00000001/sig000006de ; + wire \blk00000001/sig000006dd ; + wire \blk00000001/sig000006dc ; + wire \blk00000001/sig000006db ; + wire \blk00000001/sig000006da ; + wire \blk00000001/sig000006d9 ; + wire \blk00000001/sig000006d8 ; + wire \blk00000001/sig000006d7 ; + wire \blk00000001/sig000006d6 ; + wire \blk00000001/sig000006d5 ; + wire \blk00000001/sig000006d4 ; + wire \blk00000001/sig000006d3 ; + wire \blk00000001/sig000006d2 ; + wire \blk00000001/sig000006d1 ; + wire \blk00000001/sig000006d0 ; + wire \blk00000001/sig000006cf ; + wire \blk00000001/sig000006ce ; + wire \blk00000001/sig000006cd ; + wire \blk00000001/sig000006cc ; + wire \blk00000001/sig000006cb ; + wire \blk00000001/sig000006ca ; + wire \blk00000001/sig000006c9 ; + wire \blk00000001/sig000006c8 ; + wire \blk00000001/sig000006c7 ; + wire \blk00000001/sig000006c6 ; + wire \blk00000001/sig000006c5 ; + wire \blk00000001/sig000006c4 ; + wire \blk00000001/sig000006c3 ; + wire \blk00000001/sig000006c2 ; + wire \blk00000001/sig000006c1 ; + wire \blk00000001/sig000006c0 ; + wire \blk00000001/sig000006bf ; + wire \blk00000001/sig000006be ; + wire \blk00000001/sig000006bd ; + wire \blk00000001/sig000006bc ; + wire \blk00000001/sig000006bb ; + wire \blk00000001/sig000006ba ; + wire \blk00000001/sig000006b9 ; + wire \blk00000001/sig000006b8 ; + wire \blk00000001/sig000006b7 ; + wire \blk00000001/sig000006b6 ; + wire \blk00000001/sig000006b5 ; + wire \blk00000001/sig000006b4 ; + wire \blk00000001/sig000006b3 ; + wire \blk00000001/sig000006b2 ; + wire \blk00000001/sig000006b1 ; + wire \blk00000001/sig000006b0 ; + wire \blk00000001/sig000006af ; + wire \blk00000001/sig000006ae ; + wire \blk00000001/sig000006ad ; + wire \blk00000001/sig000006ac ; + wire \blk00000001/sig000006ab ; + wire \blk00000001/sig000006aa ; + wire \blk00000001/sig000006a9 ; + wire \blk00000001/sig000006a8 ; + wire \blk00000001/sig000006a7 ; + wire \blk00000001/sig000006a6 ; + wire \blk00000001/sig000006a5 ; + wire \blk00000001/sig000006a4 ; + wire \blk00000001/sig000006a3 ; + wire \blk00000001/sig000006a2 ; + wire \blk00000001/sig000006a1 ; + wire \blk00000001/sig000006a0 ; + wire \blk00000001/sig0000069f ; + wire \blk00000001/sig0000069e ; + wire \blk00000001/sig0000069d ; + wire \blk00000001/sig0000069c ; + wire \blk00000001/sig0000069b ; + wire \blk00000001/sig0000069a ; + wire \blk00000001/sig00000699 ; + wire \blk00000001/sig00000698 ; + wire \blk00000001/sig00000697 ; + wire \blk00000001/sig00000696 ; + wire \blk00000001/sig00000695 ; + wire \blk00000001/sig00000694 ; + wire \blk00000001/sig00000693 ; + wire \blk00000001/sig00000692 ; + wire \blk00000001/sig00000691 ; + wire \blk00000001/sig00000690 ; + wire \blk00000001/sig0000068f ; + wire \blk00000001/sig0000068e ; + wire \blk00000001/sig0000068d ; + wire \blk00000001/sig0000068c ; + wire \blk00000001/sig0000068b ; + wire \blk00000001/sig0000068a ; + wire \blk00000001/sig00000689 ; + wire \blk00000001/sig00000688 ; + wire \blk00000001/sig00000687 ; + wire \blk00000001/sig00000686 ; + wire \blk00000001/sig00000685 ; + wire \blk00000001/sig00000684 ; + wire \blk00000001/sig00000683 ; + wire \blk00000001/sig00000682 ; + wire \blk00000001/sig00000681 ; + wire \blk00000001/sig00000680 ; + wire \blk00000001/sig0000067f ; + wire \blk00000001/sig0000067e ; + wire \blk00000001/sig0000067d ; + wire \blk00000001/sig0000067c ; + wire \blk00000001/sig0000067b ; + wire \blk00000001/sig0000067a ; + wire \blk00000001/sig00000679 ; + wire \blk00000001/sig00000678 ; + wire \blk00000001/sig00000677 ; + wire \blk00000001/sig00000676 ; + wire \blk00000001/sig00000675 ; + wire \blk00000001/sig00000674 ; + wire \blk00000001/sig00000673 ; + wire \blk00000001/sig00000672 ; + wire \blk00000001/sig00000671 ; + wire \blk00000001/sig00000670 ; + wire \blk00000001/sig0000066f ; + wire \blk00000001/sig0000066e ; + wire \blk00000001/sig0000066d ; + wire \blk00000001/sig0000066c ; + wire \blk00000001/sig0000066b ; + wire \blk00000001/sig0000066a ; + wire \blk00000001/sig00000669 ; + wire \blk00000001/sig00000668 ; + wire \blk00000001/sig00000667 ; + wire \blk00000001/sig00000666 ; + wire \blk00000001/sig00000665 ; + wire \blk00000001/sig00000664 ; + wire \blk00000001/sig00000663 ; + wire \blk00000001/sig00000662 ; + wire \blk00000001/sig00000661 ; + wire \blk00000001/sig00000660 ; + wire \blk00000001/sig0000065f ; + wire \blk00000001/sig0000065e ; + wire \blk00000001/sig0000065d ; + wire \blk00000001/sig0000065c ; + wire \blk00000001/sig0000065b ; + wire \blk00000001/sig0000065a ; + wire \blk00000001/sig00000659 ; + wire \blk00000001/sig00000658 ; + wire \blk00000001/sig00000657 ; + wire \blk00000001/sig00000656 ; + wire \blk00000001/sig00000655 ; + wire \blk00000001/sig00000654 ; + wire \blk00000001/sig00000653 ; + wire \blk00000001/sig00000652 ; + wire \blk00000001/sig00000651 ; + wire \blk00000001/sig00000650 ; + wire \blk00000001/sig0000064f ; + wire \blk00000001/sig0000064e ; + wire \blk00000001/sig0000064d ; + wire \blk00000001/sig0000064c ; + wire \blk00000001/sig0000064b ; + wire \blk00000001/sig0000064a ; + wire \blk00000001/sig00000649 ; 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+ wire \blk00000001/sig00000102 ; + wire \blk00000001/sig00000101 ; + wire \blk00000001/sig00000100 ; + wire \blk00000001/sig000000ff ; + wire \blk00000001/sig000000fe ; + wire \blk00000001/sig000000fd ; + wire \blk00000001/sig000000fc ; + wire \blk00000001/sig000000fb ; + wire \blk00000001/sig000000fa ; + wire \blk00000001/sig000000f9 ; + wire \blk00000001/sig000000f8 ; + wire \blk00000001/sig000000f7 ; + wire \blk00000001/sig000000f6 ; + wire \blk00000001/sig000000f5 ; + wire \blk00000001/sig000000f4 ; + wire \blk00000001/sig000000f3 ; + wire \blk00000001/sig000000f2 ; + wire \blk00000001/sig000000f1 ; + wire \blk00000001/sig000000f0 ; + wire \blk00000001/sig000000ef ; + wire \blk00000001/sig000000ee ; + wire \blk00000001/sig000000ed ; + wire \blk00000001/sig000000ec ; + wire \blk00000001/sig000000eb ; + wire \blk00000001/sig000000ea ; + wire \blk00000001/sig000000e9 ; + wire \blk00000001/sig000000e8 ; + wire \blk00000001/sig000000e7 ; + wire \blk00000001/sig000000e6 ; + wire \blk00000001/sig000000e5 ; + wire \blk00000001/sig000000e4 ; + wire \blk00000001/sig000000e3 ; + wire \blk00000001/sig000000e2 ; + wire \blk00000001/sig000000e1 ; + wire \blk00000001/sig000000e0 ; + wire \blk00000001/sig000000df ; + wire \blk00000001/sig000000de ; + wire \blk00000001/sig000000dd ; + wire \blk00000001/sig000000dc ; + wire \blk00000001/sig000000db ; + wire \blk00000001/sig000000da ; + wire \blk00000001/sig000000d9 ; + wire \blk00000001/sig000000d8 ; + wire \blk00000001/sig000000d7 ; + wire \blk00000001/sig000000d6 ; + wire \blk00000001/sig000000d5 ; + wire \blk00000001/sig000000d4 ; + wire \blk00000001/sig000000d3 ; + wire \blk00000001/sig000000d2 ; + wire \blk00000001/sig000000d1 ; + wire \blk00000001/sig000000d0 ; + wire \blk00000001/sig000000cf ; + wire \blk00000001/sig000000ce ; + wire \blk00000001/sig000000cd ; + wire \blk00000001/sig000000cc ; + wire \blk00000001/sig000000cb ; + wire \blk00000001/sig000000ca ; + wire \blk00000001/sig000000c9 ; + wire \blk00000001/sig000000c8 ; + wire \blk00000001/sig000000c7 ; + wire \blk00000001/sig000000c6 ; + wire \blk00000001/sig000000c5 ; + wire \blk00000001/sig000000c4 ; + wire \blk00000001/sig000000c3 ; + wire \blk00000001/sig000000c2 ; + wire \blk00000001/sig000000c1 ; + wire \blk00000001/sig000000c0 ; + wire \blk00000001/sig000000bf ; + wire \blk00000001/sig000000be ; + wire \blk00000001/sig000000bd ; + wire \blk00000001/sig000000bc ; + wire \blk00000001/sig000000bb ; + wire \blk00000001/sig000000ba ; + wire \blk00000001/sig000000b9 ; + wire \blk00000001/sig000000b8 ; + wire \blk00000001/sig000000b7 ; + wire \blk00000001/sig000000b6 ; + wire \blk00000001/sig000000b5 ; + wire \blk00000001/sig000000b4 ; + wire \blk00000001/sig000000b3 ; + wire \blk00000001/sig000000b2 ; + wire \blk00000001/sig000000b1 ; + wire \blk00000001/sig000000b0 ; + wire \blk00000001/sig000000af ; + wire \blk00000001/sig000000ae ; + wire \blk00000001/sig000000ad ; + wire \blk00000001/sig000000ac ; + wire \blk00000001/sig000000ab ; + wire \blk00000001/sig000000aa ; + wire \blk00000001/sig000000a9 ; + wire \blk00000001/sig000000a8 ; + wire \blk00000001/sig000000a7 ; + wire \blk00000001/sig000000a6 ; + wire \blk00000001/sig000000a5 ; + wire \blk00000001/sig000000a4 ; + wire \blk00000001/sig000000a3 ; + wire \blk00000001/sig000000a2 ; + wire \blk00000001/sig000000a1 ; + wire \blk00000001/sig000000a0 ; + wire \blk00000001/sig0000009f ; + wire \blk00000001/sig0000009e ; + wire \blk00000001/sig0000009d ; + wire \blk00000001/sig0000009c ; + wire \blk00000001/sig0000009b ; + wire \blk00000001/sig0000009a ; + wire \blk00000001/sig00000099 ; + wire \blk00000001/sig00000098 ; + wire \blk00000001/sig00000097 ; + wire \blk00000001/sig00000096 ; + wire \blk00000001/sig00000095 ; + wire \blk00000001/sig00000094 ; + wire \blk00000001/sig00000093 ; + wire \blk00000001/sig00000092 ; + wire \blk00000001/sig00000091 ; + wire \blk00000001/sig00000090 ; + wire \blk00000001/sig0000008f ; + wire \blk00000001/sig0000008e ; + wire \blk00000001/sig0000008d ; + wire \blk00000001/sig0000008c ; + wire \blk00000001/sig0000008b ; + wire \blk00000001/sig0000008a ; + wire \blk00000001/sig00000089 ; + wire \blk00000001/sig00000088 ; + wire \blk00000001/sig00000087 ; + wire \blk00000001/sig00000086 ; + wire \blk00000001/sig00000085 ; + wire \blk00000001/sig00000084 ; + wire \blk00000001/sig00000083 ; + wire \blk00000001/sig00000082 ; + wire \blk00000001/sig00000081 ; + wire \blk00000001/sig00000080 ; + wire \blk00000001/sig0000007f ; + wire \blk00000001/sig0000007e ; + wire \blk00000001/sig0000007d ; + wire \blk00000001/sig0000007c ; + wire \blk00000001/sig0000007b ; + wire \blk00000001/sig0000007a ; + wire \blk00000001/sig00000079 ; + wire \blk00000001/sig00000078 ; + wire \blk00000001/sig00000077 ; + wire \blk00000001/sig00000076 ; + wire \blk00000001/sig00000075 ; + wire \blk00000001/sig00000074 ; + wire \blk00000001/sig00000073 ; + wire \blk00000001/sig00000072 ; + wire \blk00000001/sig00000071 ; + wire \blk00000001/sig00000070 ; + wire \blk00000001/sig0000006f ; + wire \blk00000001/sig0000006e ; + wire \blk00000001/sig0000006d ; + wire \blk00000001/sig0000006c ; + wire \blk00000001/sig0000006b ; + wire \blk00000001/sig0000006a ; + wire \blk00000001/sig00000069 ; + wire \blk00000001/sig00000068 ; + wire \blk00000001/sig00000067 ; + wire \blk00000001/sig00000066 ; + wire \blk00000001/sig00000065 ; + wire \blk00000001/sig00000064 ; + wire \blk00000001/sig00000063 ; + wire \blk00000001/sig00000062 ; + wire \blk00000001/sig00000061 ; + wire \blk00000001/sig00000060 ; + wire \blk00000001/sig0000005f ; + wire \blk00000001/sig0000005e ; + wire \blk00000001/sig0000005d ; + wire \blk00000001/sig0000005c ; + wire \blk00000001/sig0000005b ; + wire \blk00000001/sig0000005a ; + wire \blk00000001/sig00000059 ; + wire \blk00000001/sig00000058 ; + wire \blk00000001/sig00000057 ; + wire \blk00000001/sig00000056 ; + wire \NLW_blk00000001/blk00000719_Q31_UNCONNECTED ; + wire \NLW_blk00000001/blk00000718_Q_UNCONNECTED ; + wire \NLW_blk00000001/blk00000716_Q31_UNCONNECTED ; + wire \NLW_blk00000001/blk00000715_Q_UNCONNECTED ; + wire \NLW_blk00000001/blk00000713_Q31_UNCONNECTED ; + wire \NLW_blk00000001/blk00000712_Q_UNCONNECTED ; + wire \NLW_blk00000001/blk00000369_O_UNCONNECTED ; + wire \NLW_blk00000001/blk00000347_O_UNCONNECTED ; + wire \NLW_blk00000001/blk00000325_O_UNCONNECTED ; + wire \NLW_blk00000001/blk00000303_O_UNCONNECTED ; + wire \NLW_blk00000001/blk000002e1_O_UNCONNECTED ; + wire \NLW_blk00000001/blk000002bf_O_UNCONNECTED ; + wire \NLW_blk00000001/blk0000029d_O_UNCONNECTED ; + wire \NLW_blk00000001/blk0000027b_O_UNCONNECTED ; + wire \NLW_blk00000001/blk00000259_O_UNCONNECTED ; + wire \NLW_blk00000001/blk00000237_O_UNCONNECTED ; + assign + s_axis_divisor_tready = NlwRenamedSig_OI_s_axis_dividend_tready, + s_axis_dividend_tready = NlwRenamedSig_OI_s_axis_dividend_tready; + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk0000071a ( + .C(aclk), + .CE(\blk00000001/sig00000734 ), + .D(\blk00000001/sig0000073a ), + .Q(\blk00000001/sig00000080 ) + ); + SRLC32E #( + .INIT ( 32'h00000000 )) + \blk00000001/blk00000719 ( + .CLK(aclk), + .D(\blk00000001/sig00000739 ), + .CE(\blk00000001/sig00000734 ), + .Q(\blk00000001/sig0000073a ), + .Q31(\NLW_blk00000001/blk00000719_Q31_UNCONNECTED ), + .A({\blk00000001/sig00000363 , \blk00000001/sig00000363 , \blk00000001/sig00000734 , \blk00000001/sig00000734 , \blk00000001/sig00000734 }) + ); + SRLC32E #( + .INIT ( 32'h00000000 )) + \blk00000001/blk00000718 ( + .CLK(aclk), + .D(\blk00000001/sig00000120 ), + .CE(\blk00000001/sig00000734 ), + .Q(\NLW_blk00000001/blk00000718_Q_UNCONNECTED ), + .Q31(\blk00000001/sig00000739 ), + .A({\blk00000001/sig00000734 , \blk00000001/sig00000734 , \blk00000001/sig00000734 , \blk00000001/sig00000734 , \blk00000001/sig00000734 }) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk00000717 ( + .C(aclk), + .CE(\blk00000001/sig00000734 ), + .D(\blk00000001/sig00000738 ), + .Q(\blk00000001/sig00000081 ) + ); + SRLC32E #( + .INIT ( 32'h00000000 )) + \blk00000001/blk00000716 ( + .CLK(aclk), + .D(\blk00000001/sig00000737 ), + .CE(\blk00000001/sig00000734 ), + .Q(\blk00000001/sig00000738 ), + .Q31(\NLW_blk00000001/blk00000716_Q31_UNCONNECTED ), + .A({\blk00000001/sig00000363 , \blk00000001/sig00000363 , \blk00000001/sig00000734 , \blk00000001/sig00000734 , \blk00000001/sig00000734 }) + ); + SRLC32E #( + .INIT ( 32'h00000000 )) + \blk00000001/blk00000715 ( + .CLK(aclk), + .D(\blk00000001/sig00000121 ), + .CE(\blk00000001/sig00000734 ), + .Q(\NLW_blk00000001/blk00000715_Q_UNCONNECTED ), + .Q31(\blk00000001/sig00000737 ), + .A({\blk00000001/sig00000734 , \blk00000001/sig00000734 , \blk00000001/sig00000734 , \blk00000001/sig00000734 , \blk00000001/sig00000734 }) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk00000714 ( + .C(aclk), + .CE(\blk00000001/sig00000734 ), + .D(\blk00000001/sig00000736 ), + .Q(m_axis_dout_tvalid) + ); + SRLC32E #( + .INIT ( 32'h00000000 )) + \blk00000001/blk00000713 ( + .CLK(aclk), + .D(\blk00000001/sig00000735 ), + .CE(\blk00000001/sig00000734 ), + .Q(\blk00000001/sig00000736 ), + .Q31(\NLW_blk00000001/blk00000713_Q31_UNCONNECTED ), + .A({\blk00000001/sig00000363 , \blk00000001/sig00000734 , \blk00000001/sig00000363 , \blk00000001/sig00000734 , \blk00000001/sig00000363 }) + ); + SRLC32E #( + .INIT ( 32'h00000000 )) + \blk00000001/blk00000712 ( + .CLK(aclk), + .D(\blk00000001/sig0000072e ), + .CE(\blk00000001/sig00000734 ), + .Q(\NLW_blk00000001/blk00000712_Q_UNCONNECTED ), + .Q31(\blk00000001/sig00000735 ), + .A({\blk00000001/sig00000734 , \blk00000001/sig00000734 , \blk00000001/sig00000734 , \blk00000001/sig00000734 , \blk00000001/sig00000734 }) + ); + VCC \blk00000001/blk00000711 ( + .P(\blk00000001/sig00000734 ) + ); + INV \blk00000001/blk00000710 ( + .I(\blk00000001/sig00000232 ), + .O(\blk00000001/sig00000209 ) + ); + INV \blk00000001/blk0000070f ( + .I(\blk00000001/sig00000231 ), + .O(\blk00000001/sig00000208 ) + ); + INV \blk00000001/blk0000070e ( + .I(\blk00000001/sig00000230 ), + .O(\blk00000001/sig00000207 ) + ); + INV \blk00000001/blk0000070d ( + .I(\blk00000001/sig0000022f ), + .O(\blk00000001/sig00000206 ) + ); + INV \blk00000001/blk0000070c ( + .I(\blk00000001/sig0000022e ), + .O(\blk00000001/sig00000205 ) + ); + INV \blk00000001/blk0000070b ( + .I(\blk00000001/sig0000022d ), + .O(\blk00000001/sig00000204 ) + ); + INV \blk00000001/blk0000070a ( + .I(\blk00000001/sig0000022c ), + .O(\blk00000001/sig00000203 ) + ); + INV \blk00000001/blk00000709 ( + .I(\blk00000001/sig0000022b ), + .O(\blk00000001/sig00000202 ) + ); + INV \blk00000001/blk00000708 ( + .I(\blk00000001/sig0000022a ), + .O(\blk00000001/sig00000201 ) + ); + INV \blk00000001/blk00000707 ( + .I(\blk00000001/sig00000229 ), + .O(\blk00000001/sig00000200 ) + ); + INV \blk00000001/blk00000706 ( + .I(\blk00000001/sig00000228 ), + .O(\blk00000001/sig000001ff ) + ); + INV \blk00000001/blk00000705 ( + .I(\blk00000001/sig00000227 ), + .O(\blk00000001/sig000001fe ) + ); + INV \blk00000001/blk00000704 ( + .I(\blk00000001/sig00000226 ), + .O(\blk00000001/sig000001fd ) + ); + INV \blk00000001/blk00000703 ( + .I(\blk00000001/sig00000225 ), + .O(\blk00000001/sig000001fc ) + ); + INV \blk00000001/blk00000702 ( + .I(\blk00000001/sig00000224 ), + .O(\blk00000001/sig000001fb ) + ); + INV \blk00000001/blk00000701 ( + .I(\blk00000001/sig00000223 ), + .O(\blk00000001/sig000001fa ) + ); + INV \blk00000001/blk00000700 ( + .I(\blk00000001/sig00000222 ), + .O(\blk00000001/sig000001f9 ) + ); + INV \blk00000001/blk000006ff ( + .I(\blk00000001/sig00000221 ), + .O(\blk00000001/sig000001f8 ) + ); + INV \blk00000001/blk000006fe ( + .I(\blk00000001/sig00000220 ), + .O(\blk00000001/sig000001f7 ) + ); + INV \blk00000001/blk000006fd ( + .I(\blk00000001/sig0000021f ), + .O(\blk00000001/sig000001f6 ) + ); + INV \blk00000001/blk000006fc ( + .I(\blk00000001/sig0000021e ), + .O(\blk00000001/sig000001f5 ) + ); + INV \blk00000001/blk000006fb ( + .I(\blk00000001/sig0000021d ), + .O(\blk00000001/sig000001f4 ) + ); + INV \blk00000001/blk000006fa ( + .I(\blk00000001/sig0000021c ), + .O(\blk00000001/sig000001f3 ) + ); + INV \blk00000001/blk000006f9 ( + .I(\blk00000001/sig0000021b ), + .O(\blk00000001/sig000001f2 ) + ); + INV \blk00000001/blk000006f8 ( + .I(\blk00000001/sig0000021a ), + .O(\blk00000001/sig000001f1 ) + ); + INV \blk00000001/blk000006f7 ( + .I(\blk00000001/sig00000219 ), + .O(\blk00000001/sig000001f0 ) + ); + INV \blk00000001/blk000006f6 ( + .I(\blk00000001/sig00000218 ), + .O(\blk00000001/sig000001ef ) + ); + INV \blk00000001/blk000006f5 ( + .I(\blk00000001/sig00000217 ), + .O(\blk00000001/sig000001ee ) + ); + INV \blk00000001/blk000006f4 ( + .I(\blk00000001/sig00000216 ), + .O(\blk00000001/sig000001ed ) + ); + INV \blk00000001/blk000006f3 ( + .I(\blk00000001/sig00000215 ), + .O(\blk00000001/sig000001ec ) + ); + INV \blk00000001/blk000006f2 ( + .I(\blk00000001/sig00000214 ), + .O(\blk00000001/sig000001eb ) + ); + INV \blk00000001/blk000006f1 ( + .I(\blk00000001/sig00000213 ), + .O(\blk00000001/sig000001ea ) + ); + INV \blk00000001/blk000006f0 ( + .I(\blk00000001/sig00000212 ), + .O(\blk00000001/sig000001e9 ) + ); + INV \blk00000001/blk000006ef ( + .I(\blk00000001/sig00000211 ), + .O(\blk00000001/sig000001e8 ) + ); + INV \blk00000001/blk000006ee ( + .I(\blk00000001/sig00000210 ), + .O(\blk00000001/sig000001e7 ) + ); + INV \blk00000001/blk000006ed ( + .I(\blk00000001/sig0000020f ), + .O(\blk00000001/sig000001e6 ) + ); + INV \blk00000001/blk000006ec ( + .I(\blk00000001/sig0000020e ), + .O(\blk00000001/sig000001e5 ) + ); + INV \blk00000001/blk000006eb ( + .I(\blk00000001/sig0000020d ), + .O(\blk00000001/sig000001e4 ) + ); + INV \blk00000001/blk000006ea ( + .I(\blk00000001/sig0000020c ), + .O(\blk00000001/sig000001e3 ) + ); + INV \blk00000001/blk000006e9 ( + .I(\blk00000001/sig0000020b ), + .O(\blk00000001/sig000001e2 ) + ); + INV \blk00000001/blk000006e8 ( + .I(\blk00000001/sig00000123 ), + .O(\blk00000001/sig00000125 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000001/blk000006e7 ( + .I0(\blk00000001/sig00000059 ), + .O(\blk00000001/sig00000733 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000001/blk000006e6 ( + .I0(\blk00000001/sig00000068 ), + .O(\blk00000001/sig00000732 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000001/blk000006e5 ( + .I0(s_axis_divisor_tdata[0]), + .O(\blk00000001/sig00000731 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000001/blk000006e4 ( + .I0(s_axis_dividend_tdata[0]), + .O(\blk00000001/sig00000730 ) + ); + LUT3 #( + .INIT ( 8'h96 )) + \blk00000001/blk000006e3 ( + .I0(\blk00000001/sig0000007f ), + .I1(\blk00000001/sig00000080 ), + .I2(\blk00000001/sig00000081 ), + .O(\blk00000001/sig00000700 ) + ); + LUT3 #( + .INIT ( 8'h96 )) + \blk00000001/blk000006e2 ( + .I0(\blk00000001/sig00000067 ), + .I1(\blk00000001/sig00000080 ), + .I2(\blk00000001/sig00000081 ), + .O(\blk00000001/sig0000072d ) + ); + LUT3 #( + .INIT ( 8'h96 )) + \blk00000001/blk000006e1 ( + .I0(\blk00000001/sig0000007e ), + .I1(\blk00000001/sig00000080 ), + .I2(\blk00000001/sig00000081 ), + .O(\blk00000001/sig000006ff ) + ); + LUT3 #( + .INIT ( 8'h96 )) + \blk00000001/blk000006e0 ( + .I0(\blk00000001/sig00000066 ), + .I1(\blk00000001/sig00000080 ), + .I2(\blk00000001/sig00000081 ), + .O(\blk00000001/sig0000072c ) + ); + LUT3 #( + .INIT ( 8'h96 )) + \blk00000001/blk000006df ( + .I0(\blk00000001/sig0000007d ), + .I1(\blk00000001/sig00000080 ), + .I2(\blk00000001/sig00000081 ), + .O(\blk00000001/sig000006fe ) + ); + LUT3 #( + .INIT ( 8'h96 )) + \blk00000001/blk000006de ( + .I0(\blk00000001/sig00000065 ), + .I1(\blk00000001/sig00000080 ), + .I2(\blk00000001/sig00000081 ), + .O(\blk00000001/sig0000072b ) + ); + LUT3 #( + .INIT ( 8'h96 )) + \blk00000001/blk000006dd ( + .I0(\blk00000001/sig0000007c ), + .I1(\blk00000001/sig00000080 ), + .I2(\blk00000001/sig00000081 ), + .O(\blk00000001/sig000006fd ) + ); + LUT3 #( + .INIT ( 8'h96 )) + \blk00000001/blk000006dc ( + .I0(\blk00000001/sig00000064 ), + .I1(\blk00000001/sig00000080 ), + .I2(\blk00000001/sig00000081 ), + .O(\blk00000001/sig0000072a ) + ); + LUT3 #( + .INIT ( 8'h96 )) + \blk00000001/blk000006db ( + .I0(\blk00000001/sig0000007b ), + .I1(\blk00000001/sig00000080 ), + .I2(\blk00000001/sig00000081 ), + .O(\blk00000001/sig000006fc ) + ); + LUT3 #( + .INIT ( 8'h96 )) + \blk00000001/blk000006da ( + .I0(\blk00000001/sig00000063 ), + .I1(\blk00000001/sig00000080 ), + .I2(\blk00000001/sig00000081 ), + .O(\blk00000001/sig00000729 ) + ); + LUT3 #( + .INIT ( 8'h96 )) + \blk00000001/blk000006d9 ( + .I0(\blk00000001/sig0000007a ), + .I1(\blk00000001/sig00000080 ), + .I2(\blk00000001/sig00000081 ), + .O(\blk00000001/sig000006fb ) + ); + LUT3 #( + .INIT ( 8'h96 )) + \blk00000001/blk000006d8 ( + .I0(\blk00000001/sig00000062 ), + .I1(\blk00000001/sig00000080 ), + .I2(\blk00000001/sig00000081 ), + .O(\blk00000001/sig00000728 ) + ); + LUT3 #( + .INIT ( 8'h96 )) + \blk00000001/blk000006d7 ( + .I0(\blk00000001/sig00000079 ), + .I1(\blk00000001/sig00000080 ), + .I2(\blk00000001/sig00000081 ), + .O(\blk00000001/sig000006fa ) + ); + LUT3 #( + .INIT ( 8'h96 )) + \blk00000001/blk000006d6 ( + .I0(\blk00000001/sig00000061 ), + .I1(\blk00000001/sig00000080 ), + .I2(\blk00000001/sig00000081 ), + .O(\blk00000001/sig00000727 ) + ); + LUT3 #( + .INIT ( 8'h96 )) + \blk00000001/blk000006d5 ( + .I0(\blk00000001/sig00000078 ), + .I1(\blk00000001/sig00000080 ), + .I2(\blk00000001/sig00000081 ), + .O(\blk00000001/sig000006f9 ) + ); + LUT3 #( + .INIT ( 8'h96 )) + \blk00000001/blk000006d4 ( + .I0(\blk00000001/sig00000060 ), + .I1(\blk00000001/sig00000080 ), + .I2(\blk00000001/sig00000081 ), + .O(\blk00000001/sig00000726 ) + ); + LUT3 #( + .INIT ( 8'h96 )) + \blk00000001/blk000006d3 ( + .I0(\blk00000001/sig00000077 ), + .I1(\blk00000001/sig00000080 ), + .I2(\blk00000001/sig00000081 ), + .O(\blk00000001/sig000006f8 ) + ); + LUT3 #( + .INIT ( 8'h96 )) + \blk00000001/blk000006d2 ( + .I0(\blk00000001/sig0000005f ), + .I1(\blk00000001/sig00000080 ), + .I2(\blk00000001/sig00000081 ), + .O(\blk00000001/sig00000725 ) + ); + LUT3 #( + .INIT ( 8'h96 )) + \blk00000001/blk000006d1 ( + .I0(\blk00000001/sig00000076 ), + .I1(\blk00000001/sig00000080 ), + .I2(\blk00000001/sig00000081 ), + .O(\blk00000001/sig000006f7 ) + ); + LUT3 #( + .INIT ( 8'h96 )) + \blk00000001/blk000006d0 ( + .I0(\blk00000001/sig0000005e ), + .I1(\blk00000001/sig00000080 ), + .I2(\blk00000001/sig00000081 ), + .O(\blk00000001/sig00000724 ) + ); + LUT3 #( + .INIT ( 8'h96 )) + \blk00000001/blk000006cf ( + .I0(\blk00000001/sig00000075 ), + .I1(\blk00000001/sig00000080 ), + .I2(\blk00000001/sig00000081 ), + .O(\blk00000001/sig000006f6 ) + ); + LUT3 #( + .INIT ( 8'h96 )) + \blk00000001/blk000006ce ( + .I0(\blk00000001/sig0000005d ), + .I1(\blk00000001/sig00000080 ), + .I2(\blk00000001/sig00000081 ), + .O(\blk00000001/sig00000723 ) + ); + LUT3 #( + .INIT ( 8'h96 )) + \blk00000001/blk000006cd ( + .I0(\blk00000001/sig00000074 ), + .I1(\blk00000001/sig00000080 ), + .I2(\blk00000001/sig00000081 ), + .O(\blk00000001/sig000006f5 ) + ); + LUT3 #( + .INIT ( 8'h96 )) + \blk00000001/blk000006cc ( + .I0(\blk00000001/sig0000005c ), + .I1(\blk00000001/sig00000080 ), + .I2(\blk00000001/sig00000081 ), + .O(\blk00000001/sig00000722 ) + ); + LUT3 #( + .INIT ( 8'h96 )) + \blk00000001/blk000006cb ( + .I0(\blk00000001/sig00000073 ), + .I1(\blk00000001/sig00000080 ), + .I2(\blk00000001/sig00000081 ), + .O(\blk00000001/sig000006f4 ) + ); + LUT3 #( + .INIT ( 8'h96 )) + \blk00000001/blk000006ca ( + .I0(\blk00000001/sig0000005b ), + .I1(\blk00000001/sig00000080 ), + .I2(\blk00000001/sig00000081 ), + .O(\blk00000001/sig00000721 ) + ); + LUT3 #( + .INIT ( 8'h96 )) + \blk00000001/blk000006c9 ( + .I0(\blk00000001/sig00000072 ), + .I1(\blk00000001/sig00000080 ), + .I2(\blk00000001/sig00000081 ), + .O(\blk00000001/sig000006f3 ) + ); + LUT3 #( + .INIT ( 8'h96 )) + \blk00000001/blk000006c8 ( + .I0(\blk00000001/sig0000005a ), + .I1(\blk00000001/sig00000080 ), + .I2(\blk00000001/sig00000081 ), + .O(\blk00000001/sig00000720 ) + ); + LUT3 #( + .INIT ( 8'h96 )) + \blk00000001/blk000006c7 ( + .I0(\blk00000001/sig00000071 ), + .I1(\blk00000001/sig00000080 ), + .I2(\blk00000001/sig00000081 ), + .O(\blk00000001/sig000006f2 ) + ); + LUT3 #( + .INIT ( 8'h96 )) + \blk00000001/blk000006c6 ( + .I0(\blk00000001/sig00000070 ), + .I1(\blk00000001/sig00000080 ), + .I2(\blk00000001/sig00000081 ), + .O(\blk00000001/sig000006f1 ) + ); + LUT3 #( + .INIT ( 8'h96 )) + \blk00000001/blk000006c5 ( + .I0(\blk00000001/sig0000006f ), + .I1(\blk00000001/sig00000080 ), + .I2(\blk00000001/sig00000081 ), + .O(\blk00000001/sig000006f0 ) + ); + LUT3 #( + .INIT ( 8'h96 )) + \blk00000001/blk000006c4 ( + .I0(\blk00000001/sig0000006e ), + .I1(\blk00000001/sig00000080 ), + .I2(\blk00000001/sig00000081 ), + .O(\blk00000001/sig000006ef ) + ); + LUT3 #( + .INIT ( 8'h96 )) + \blk00000001/blk000006c3 ( + .I0(\blk00000001/sig0000006d ), + .I1(\blk00000001/sig00000080 ), + .I2(\blk00000001/sig00000081 ), + .O(\blk00000001/sig000006ee ) + ); + LUT3 #( + .INIT ( 8'h96 )) + \blk00000001/blk000006c2 ( + .I0(\blk00000001/sig0000006c ), + .I1(\blk00000001/sig00000080 ), + .I2(\blk00000001/sig00000081 ), + .O(\blk00000001/sig000006ed ) + ); + LUT3 #( + .INIT ( 8'h96 )) + \blk00000001/blk000006c1 ( + .I0(\blk00000001/sig0000006b ), + .I1(\blk00000001/sig00000080 ), + .I2(\blk00000001/sig00000081 ), + .O(\blk00000001/sig000006ec ) + ); + LUT3 #( + .INIT ( 8'h96 )) + \blk00000001/blk000006c0 ( + .I0(\blk00000001/sig0000006a ), + .I1(\blk00000001/sig00000080 ), + .I2(\blk00000001/sig00000081 ), + .O(\blk00000001/sig000006eb ) + ); + LUT3 #( + .INIT ( 8'h96 )) + \blk00000001/blk000006bf ( + .I0(\blk00000001/sig00000069 ), + .I1(\blk00000001/sig00000080 ), + .I2(\blk00000001/sig00000081 ), + .O(\blk00000001/sig000006ea ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000001/blk000006be ( + .I0(\blk00000001/sig00000080 ), + .I1(\blk00000001/sig00000081 ), + .O(\blk00000001/sig0000072f ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk000006bd ( + .I0(\blk00000001/sig00000275 ), + .I1(\blk00000001/sig00000286 ), + .I2(\blk00000001/sig0000026c ), + .O(\blk00000001/sig000006a0 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk000006bc ( + .I0(\blk00000001/sig00000274 ), + .I1(\blk00000001/sig00000285 ), + .I2(\blk00000001/sig0000026c ), + .O(\blk00000001/sig000006a1 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk000006bb ( + .I0(\blk00000001/sig00000273 ), + .I1(\blk00000001/sig00000284 ), + .I2(\blk00000001/sig0000026c ), + .O(\blk00000001/sig000006a2 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk000006ba ( + .I0(\blk00000001/sig00000272 ), + .I1(\blk00000001/sig00000283 ), + .I2(\blk00000001/sig0000026c ), + .O(\blk00000001/sig000006a3 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk000006b9 ( + .I0(\blk00000001/sig00000271 ), + .I1(\blk00000001/sig00000282 ), + .I2(\blk00000001/sig0000026c ), + .O(\blk00000001/sig000006a4 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk000006b8 ( + .I0(\blk00000001/sig00000270 ), + .I1(\blk00000001/sig00000281 ), + .I2(\blk00000001/sig0000026c ), + .O(\blk00000001/sig000006a5 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk000006b7 ( + .I0(\blk00000001/sig0000026f ), + .I1(\blk00000001/sig00000280 ), + .I2(\blk00000001/sig0000026c ), + .O(\blk00000001/sig000006a6 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk000006b6 ( + .I0(\blk00000001/sig0000026e ), + .I1(\blk00000001/sig0000027f ), + .I2(\blk00000001/sig0000026c ), + .O(\blk00000001/sig000006a7 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk000006b5 ( + .I0(\blk00000001/sig0000026d ), + .I1(\blk00000001/sig0000027e ), + .I2(\blk00000001/sig0000026c ), + .O(\blk00000001/sig000006a8 ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \blk00000001/blk000006b4 ( + .I0(\blk00000001/sig0000027c ), + .I1(\blk00000001/sig0000026c ), + .O(\blk00000001/sig000006a9 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk000006b3 ( + .I0(\blk00000001/sig0000027b ), + .I1(\blk00000001/sig0000028c ), + .I2(\blk00000001/sig0000026c ), + .O(\blk00000001/sig0000069a ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk000006b2 ( + .I0(\blk00000001/sig0000027a ), + .I1(\blk00000001/sig0000028b ), + .I2(\blk00000001/sig0000026c ), + .O(\blk00000001/sig0000069b ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk000006b1 ( + .I0(\blk00000001/sig00000279 ), + .I1(\blk00000001/sig0000028a ), + .I2(\blk00000001/sig0000026c ), + .O(\blk00000001/sig0000069c ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk000006b0 ( + .I0(\blk00000001/sig00000278 ), + .I1(\blk00000001/sig00000289 ), + .I2(\blk00000001/sig0000026c ), + .O(\blk00000001/sig0000069d ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk000006af ( + .I0(\blk00000001/sig00000277 ), + .I1(\blk00000001/sig00000288 ), + .I2(\blk00000001/sig0000026c ), + .O(\blk00000001/sig0000069e ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk000006ae ( + .I0(\blk00000001/sig00000276 ), + .I1(\blk00000001/sig00000287 ), + .I2(\blk00000001/sig0000026c ), + .O(\blk00000001/sig0000069f ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \blk00000001/blk000006ad ( + .I0(\blk00000001/sig0000027d ), + .I1(\blk00000001/sig0000026c ), + .O(\blk00000001/sig000006aa ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk000006ac ( + .I0(\blk00000001/sig000002cb ), + .I1(\blk00000001/sig000002dc ), + .I2(\blk00000001/sig000002c2 ), + .O(\blk00000001/sig0000067f ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk000006ab ( + .I0(\blk00000001/sig000002ca ), + .I1(\blk00000001/sig000002db ), + .I2(\blk00000001/sig000002c2 ), + .O(\blk00000001/sig00000680 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk000006aa ( + .I0(\blk00000001/sig000002c9 ), + .I1(\blk00000001/sig000002da ), + .I2(\blk00000001/sig000002c2 ), + .O(\blk00000001/sig00000681 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk000006a9 ( + .I0(\blk00000001/sig000002c8 ), + .I1(\blk00000001/sig000002d9 ), + .I2(\blk00000001/sig000002c2 ), + .O(\blk00000001/sig00000682 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk000006a8 ( + .I0(\blk00000001/sig000002c7 ), + .I1(\blk00000001/sig000002d8 ), + .I2(\blk00000001/sig000002c2 ), + .O(\blk00000001/sig00000683 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk000006a7 ( + .I0(\blk00000001/sig000002c6 ), + .I1(\blk00000001/sig000002d7 ), + .I2(\blk00000001/sig000002c2 ), + .O(\blk00000001/sig00000684 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk000006a6 ( + .I0(\blk00000001/sig000002c5 ), + .I1(\blk00000001/sig000002d6 ), + .I2(\blk00000001/sig000002c2 ), + .O(\blk00000001/sig00000685 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk000006a5 ( + .I0(\blk00000001/sig000002c4 ), + .I1(\blk00000001/sig000002d5 ), + .I2(\blk00000001/sig000002c2 ), + .O(\blk00000001/sig00000686 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk000006a4 ( + .I0(\blk00000001/sig000002c3 ), + .I1(\blk00000001/sig000002d4 ), + .I2(\blk00000001/sig000002c2 ), + .O(\blk00000001/sig00000687 ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \blk00000001/blk000006a3 ( + .I0(\blk00000001/sig000002d2 ), + .I1(\blk00000001/sig000002c2 ), + .O(\blk00000001/sig00000688 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk000006a2 ( + .I0(\blk00000001/sig000002d1 ), + .I1(\blk00000001/sig000002e2 ), + .I2(\blk00000001/sig000002c2 ), + .O(\blk00000001/sig00000679 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk000006a1 ( + .I0(\blk00000001/sig000002d0 ), + .I1(\blk00000001/sig000002e1 ), + .I2(\blk00000001/sig000002c2 ), + .O(\blk00000001/sig0000067a ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk000006a0 ( + .I0(\blk00000001/sig000002cf ), + .I1(\blk00000001/sig000002e0 ), + .I2(\blk00000001/sig000002c2 ), + .O(\blk00000001/sig0000067b ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk0000069f ( + .I0(\blk00000001/sig000002ce ), + .I1(\blk00000001/sig000002df ), + .I2(\blk00000001/sig000002c2 ), + .O(\blk00000001/sig0000067c ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk0000069e ( + .I0(\blk00000001/sig000002cd ), + .I1(\blk00000001/sig000002de ), + .I2(\blk00000001/sig000002c2 ), + .O(\blk00000001/sig0000067d ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk0000069d ( + .I0(\blk00000001/sig000002cc ), + .I1(\blk00000001/sig000002dd ), + .I2(\blk00000001/sig000002c2 ), + .O(\blk00000001/sig0000067e ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \blk00000001/blk0000069c ( + .I0(\blk00000001/sig000002d3 ), + .I1(\blk00000001/sig000002c2 ), + .O(\blk00000001/sig00000689 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk0000069b ( + .I0(\blk00000001/sig0000031d ), + .I1(\blk00000001/sig0000032e ), + .I2(\blk00000001/sig00000314 ), + .O(\blk00000001/sig0000065e ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk0000069a ( + .I0(\blk00000001/sig0000031c ), + .I1(\blk00000001/sig0000032d ), + .I2(\blk00000001/sig00000314 ), + .O(\blk00000001/sig0000065f ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000699 ( + .I0(\blk00000001/sig0000031b ), + .I1(\blk00000001/sig0000032c ), + .I2(\blk00000001/sig00000314 ), + .O(\blk00000001/sig00000660 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000698 ( + .I0(\blk00000001/sig0000031a ), + .I1(\blk00000001/sig0000032b ), + .I2(\blk00000001/sig00000314 ), + .O(\blk00000001/sig00000661 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000697 ( + .I0(\blk00000001/sig00000319 ), + .I1(\blk00000001/sig0000032a ), + .I2(\blk00000001/sig00000314 ), + .O(\blk00000001/sig00000662 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000696 ( + .I0(\blk00000001/sig00000318 ), + .I1(\blk00000001/sig00000329 ), + .I2(\blk00000001/sig00000314 ), + .O(\blk00000001/sig00000663 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000695 ( + .I0(\blk00000001/sig00000317 ), + .I1(\blk00000001/sig00000328 ), + .I2(\blk00000001/sig00000314 ), + .O(\blk00000001/sig00000664 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000694 ( + .I0(\blk00000001/sig00000316 ), + .I1(\blk00000001/sig00000327 ), + .I2(\blk00000001/sig00000314 ), + .O(\blk00000001/sig00000665 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000693 ( + .I0(\blk00000001/sig00000315 ), + .I1(\blk00000001/sig00000326 ), + .I2(\blk00000001/sig00000314 ), + .O(\blk00000001/sig00000666 ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \blk00000001/blk00000692 ( + .I0(\blk00000001/sig00000324 ), + .I1(\blk00000001/sig00000314 ), + .O(\blk00000001/sig00000667 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000691 ( + .I0(\blk00000001/sig00000323 ), + .I1(\blk00000001/sig00000334 ), + .I2(\blk00000001/sig00000314 ), + .O(\blk00000001/sig00000658 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000690 ( + .I0(\blk00000001/sig00000322 ), + .I1(\blk00000001/sig00000333 ), + .I2(\blk00000001/sig00000314 ), + .O(\blk00000001/sig00000659 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk0000068f ( + .I0(\blk00000001/sig00000321 ), + .I1(\blk00000001/sig00000332 ), + .I2(\blk00000001/sig00000314 ), + .O(\blk00000001/sig0000065a ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk0000068e ( + .I0(\blk00000001/sig00000320 ), + .I1(\blk00000001/sig00000331 ), + .I2(\blk00000001/sig00000314 ), + .O(\blk00000001/sig0000065b ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk0000068d ( + .I0(\blk00000001/sig0000031f ), + .I1(\blk00000001/sig00000330 ), + .I2(\blk00000001/sig00000314 ), + .O(\blk00000001/sig0000065c ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk0000068c ( + .I0(\blk00000001/sig0000031e ), + .I1(\blk00000001/sig0000032f ), + .I2(\blk00000001/sig00000314 ), + .O(\blk00000001/sig0000065d ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \blk00000001/blk0000068b ( + .I0(\blk00000001/sig00000325 ), + .I1(\blk00000001/sig00000314 ), + .O(\blk00000001/sig00000668 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk0000068a ( + .I0(\blk00000001/sig0000036c ), + .I1(\blk00000001/sig0000037d ), + .I2(\blk00000001/sig00000362 ), + .O(\blk00000001/sig0000063d ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000689 ( + .I0(\blk00000001/sig0000036b ), + .I1(\blk00000001/sig0000037c ), + .I2(\blk00000001/sig00000362 ), + .O(\blk00000001/sig0000063e ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000688 ( + .I0(\blk00000001/sig0000036a ), + .I1(\blk00000001/sig0000037b ), + .I2(\blk00000001/sig00000362 ), + .O(\blk00000001/sig0000063f ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000687 ( + .I0(\blk00000001/sig00000369 ), + .I1(\blk00000001/sig0000037a ), + .I2(\blk00000001/sig00000362 ), + .O(\blk00000001/sig00000640 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000686 ( + .I0(\blk00000001/sig00000368 ), + .I1(\blk00000001/sig00000379 ), + .I2(\blk00000001/sig00000362 ), + .O(\blk00000001/sig00000641 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000685 ( + .I0(\blk00000001/sig00000367 ), + .I1(\blk00000001/sig00000378 ), + .I2(\blk00000001/sig00000362 ), + .O(\blk00000001/sig00000642 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000684 ( + .I0(\blk00000001/sig00000366 ), + .I1(\blk00000001/sig00000377 ), + .I2(\blk00000001/sig00000362 ), + .O(\blk00000001/sig00000643 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000683 ( + .I0(\blk00000001/sig00000365 ), + .I1(\blk00000001/sig00000376 ), + .I2(\blk00000001/sig00000362 ), + .O(\blk00000001/sig00000644 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000682 ( + .I0(\blk00000001/sig00000364 ), + .I1(\blk00000001/sig00000375 ), + .I2(\blk00000001/sig00000362 ), + .O(\blk00000001/sig00000645 ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \blk00000001/blk00000681 ( + .I0(\blk00000001/sig00000373 ), + .I1(\blk00000001/sig00000362 ), + .O(\blk00000001/sig00000646 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000680 ( + .I0(\blk00000001/sig00000372 ), + .I1(\blk00000001/sig00000383 ), + .I2(\blk00000001/sig00000362 ), + .O(\blk00000001/sig00000637 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk0000067f ( + .I0(\blk00000001/sig00000371 ), + .I1(\blk00000001/sig00000382 ), + .I2(\blk00000001/sig00000362 ), + .O(\blk00000001/sig00000638 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk0000067e ( + .I0(\blk00000001/sig00000370 ), + .I1(\blk00000001/sig00000381 ), + .I2(\blk00000001/sig00000362 ), + .O(\blk00000001/sig00000639 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk0000067d ( + .I0(\blk00000001/sig0000036f ), + .I1(\blk00000001/sig00000380 ), + .I2(\blk00000001/sig00000362 ), + .O(\blk00000001/sig0000063a ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk0000067c ( + .I0(\blk00000001/sig0000036e ), + .I1(\blk00000001/sig0000037f ), + .I2(\blk00000001/sig00000362 ), + .O(\blk00000001/sig0000063b ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk0000067b ( + .I0(\blk00000001/sig0000036d ), + .I1(\blk00000001/sig0000037e ), + .I2(\blk00000001/sig00000362 ), + .O(\blk00000001/sig0000063c ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \blk00000001/blk0000067a ( + .I0(\blk00000001/sig00000374 ), + .I1(\blk00000001/sig00000362 ), + .O(\blk00000001/sig00000647 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000679 ( + .I0(\blk00000001/sig000003b7 ), + .I1(\blk00000001/sig000003c8 ), + .I2(\blk00000001/sig000003ad ), + .O(\blk00000001/sig0000061c ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000678 ( + .I0(\blk00000001/sig000003b6 ), + .I1(\blk00000001/sig000003c7 ), + .I2(\blk00000001/sig000003ad ), + .O(\blk00000001/sig0000061d ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000677 ( + .I0(\blk00000001/sig000003b5 ), + .I1(\blk00000001/sig000003c6 ), + .I2(\blk00000001/sig000003ad ), + .O(\blk00000001/sig0000061e ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000676 ( + .I0(\blk00000001/sig000003b4 ), + .I1(\blk00000001/sig000003c5 ), + .I2(\blk00000001/sig000003ad ), + .O(\blk00000001/sig0000061f ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000675 ( + .I0(\blk00000001/sig000003b3 ), + .I1(\blk00000001/sig000003c4 ), + .I2(\blk00000001/sig000003ad ), + .O(\blk00000001/sig00000620 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000674 ( + .I0(\blk00000001/sig000003b2 ), + .I1(\blk00000001/sig000003c3 ), + .I2(\blk00000001/sig000003ad ), + .O(\blk00000001/sig00000621 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000673 ( + .I0(\blk00000001/sig000003b1 ), + .I1(\blk00000001/sig000003c2 ), + .I2(\blk00000001/sig000003ad ), + .O(\blk00000001/sig00000622 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000672 ( + .I0(\blk00000001/sig000003b0 ), + .I1(\blk00000001/sig000003c1 ), + .I2(\blk00000001/sig000003ad ), + .O(\blk00000001/sig00000623 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000671 ( + .I0(\blk00000001/sig000003af ), + .I1(\blk00000001/sig000003c0 ), + .I2(\blk00000001/sig000003ad ), + .O(\blk00000001/sig00000624 ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \blk00000001/blk00000670 ( + .I0(\blk00000001/sig000003be ), + .I1(\blk00000001/sig000003ad ), + .O(\blk00000001/sig00000625 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk0000066f ( + .I0(\blk00000001/sig000003bd ), + .I1(\blk00000001/sig000003ce ), + .I2(\blk00000001/sig000003ad ), + .O(\blk00000001/sig00000616 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk0000066e ( + .I0(\blk00000001/sig000003bc ), + .I1(\blk00000001/sig000003cd ), + .I2(\blk00000001/sig000003ad ), + .O(\blk00000001/sig00000617 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk0000066d ( + .I0(\blk00000001/sig000003bb ), + .I1(\blk00000001/sig000003cc ), + .I2(\blk00000001/sig000003ad ), + .O(\blk00000001/sig00000618 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk0000066c ( + .I0(\blk00000001/sig000003ba ), + .I1(\blk00000001/sig000003cb ), + .I2(\blk00000001/sig000003ad ), + .O(\blk00000001/sig00000619 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk0000066b ( + .I0(\blk00000001/sig000003b9 ), + .I1(\blk00000001/sig000003ca ), + .I2(\blk00000001/sig000003ad ), + .O(\blk00000001/sig0000061a ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk0000066a ( + .I0(\blk00000001/sig000003b8 ), + .I1(\blk00000001/sig000003c9 ), + .I2(\blk00000001/sig000003ad ), + .O(\blk00000001/sig0000061b ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000669 ( + .I0(\blk00000001/sig000003ae ), + .I1(\blk00000001/sig000003bf ), + .I2(\blk00000001/sig000003ad ), + .O(\blk00000001/sig00000626 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000668 ( + .I0(\blk00000001/sig00000402 ), + .I1(\blk00000001/sig00000413 ), + .I2(\blk00000001/sig000003f8 ), + .O(\blk00000001/sig000005fb ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000667 ( + .I0(\blk00000001/sig00000401 ), + .I1(\blk00000001/sig00000412 ), + .I2(\blk00000001/sig000003f8 ), + .O(\blk00000001/sig000005fc ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000666 ( + .I0(\blk00000001/sig00000400 ), + .I1(\blk00000001/sig00000411 ), + .I2(\blk00000001/sig000003f8 ), + .O(\blk00000001/sig000005fd ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000665 ( + .I0(\blk00000001/sig000003ff ), + .I1(\blk00000001/sig00000410 ), + .I2(\blk00000001/sig000003f8 ), + .O(\blk00000001/sig000005fe ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000664 ( + .I0(\blk00000001/sig000003fe ), + .I1(\blk00000001/sig0000040f ), + .I2(\blk00000001/sig000003f8 ), + .O(\blk00000001/sig000005ff ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000663 ( + .I0(\blk00000001/sig000003fd ), + .I1(\blk00000001/sig0000040e ), + .I2(\blk00000001/sig000003f8 ), + .O(\blk00000001/sig00000600 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000662 ( + .I0(\blk00000001/sig000003fc ), + .I1(\blk00000001/sig0000040d ), + .I2(\blk00000001/sig000003f8 ), + .O(\blk00000001/sig00000601 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000661 ( + .I0(\blk00000001/sig000003fb ), + .I1(\blk00000001/sig0000040c ), + .I2(\blk00000001/sig000003f8 ), + .O(\blk00000001/sig00000602 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000660 ( + .I0(\blk00000001/sig000003fa ), + .I1(\blk00000001/sig0000040b ), + .I2(\blk00000001/sig000003f8 ), + .O(\blk00000001/sig00000603 ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \blk00000001/blk0000065f ( + .I0(\blk00000001/sig00000409 ), + .I1(\blk00000001/sig000003f8 ), + .O(\blk00000001/sig00000604 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk0000065e ( + .I0(\blk00000001/sig00000408 ), + .I1(\blk00000001/sig00000419 ), + .I2(\blk00000001/sig000003f8 ), + .O(\blk00000001/sig000005f5 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk0000065d ( + .I0(\blk00000001/sig00000407 ), + .I1(\blk00000001/sig00000418 ), + .I2(\blk00000001/sig000003f8 ), + .O(\blk00000001/sig000005f6 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk0000065c ( + .I0(\blk00000001/sig00000406 ), + .I1(\blk00000001/sig00000417 ), + .I2(\blk00000001/sig000003f8 ), + .O(\blk00000001/sig000005f7 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk0000065b ( + .I0(\blk00000001/sig00000405 ), + .I1(\blk00000001/sig00000416 ), + .I2(\blk00000001/sig000003f8 ), + .O(\blk00000001/sig000005f8 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk0000065a ( + .I0(\blk00000001/sig00000404 ), + .I1(\blk00000001/sig00000415 ), + .I2(\blk00000001/sig000003f8 ), + .O(\blk00000001/sig000005f9 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000659 ( + .I0(\blk00000001/sig00000403 ), + .I1(\blk00000001/sig00000414 ), + .I2(\blk00000001/sig000003f8 ), + .O(\blk00000001/sig000005fa ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000658 ( + .I0(\blk00000001/sig000003f9 ), + .I1(\blk00000001/sig0000040a ), + .I2(\blk00000001/sig000003f8 ), + .O(\blk00000001/sig00000605 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000657 ( + .I0(\blk00000001/sig0000044d ), + .I1(\blk00000001/sig0000045e ), + .I2(\blk00000001/sig00000443 ), + .O(\blk00000001/sig000005da ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000656 ( + .I0(\blk00000001/sig0000044c ), + .I1(\blk00000001/sig0000045d ), + .I2(\blk00000001/sig00000443 ), + .O(\blk00000001/sig000005db ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000655 ( + .I0(\blk00000001/sig0000044b ), + .I1(\blk00000001/sig0000045c ), + .I2(\blk00000001/sig00000443 ), + .O(\blk00000001/sig000005dc ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000654 ( + .I0(\blk00000001/sig0000044a ), + .I1(\blk00000001/sig0000045b ), + .I2(\blk00000001/sig00000443 ), + .O(\blk00000001/sig000005dd ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000653 ( + .I0(\blk00000001/sig00000449 ), + .I1(\blk00000001/sig0000045a ), + .I2(\blk00000001/sig00000443 ), + .O(\blk00000001/sig000005de ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000652 ( + .I0(\blk00000001/sig00000448 ), + .I1(\blk00000001/sig00000459 ), + .I2(\blk00000001/sig00000443 ), + .O(\blk00000001/sig000005df ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000651 ( + .I0(\blk00000001/sig00000447 ), + .I1(\blk00000001/sig00000458 ), + .I2(\blk00000001/sig00000443 ), + .O(\blk00000001/sig000005e0 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000650 ( + .I0(\blk00000001/sig00000446 ), + .I1(\blk00000001/sig00000457 ), + .I2(\blk00000001/sig00000443 ), + .O(\blk00000001/sig000005e1 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk0000064f ( + .I0(\blk00000001/sig00000445 ), + .I1(\blk00000001/sig00000456 ), + .I2(\blk00000001/sig00000443 ), + .O(\blk00000001/sig000005e2 ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \blk00000001/blk0000064e ( + .I0(\blk00000001/sig00000454 ), + .I1(\blk00000001/sig00000443 ), + .O(\blk00000001/sig000005e3 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk0000064d ( + .I0(\blk00000001/sig00000453 ), + .I1(\blk00000001/sig00000464 ), + .I2(\blk00000001/sig00000443 ), + .O(\blk00000001/sig000005d4 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk0000064c ( + .I0(\blk00000001/sig00000452 ), + .I1(\blk00000001/sig00000463 ), + .I2(\blk00000001/sig00000443 ), + .O(\blk00000001/sig000005d5 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk0000064b ( + .I0(\blk00000001/sig00000451 ), + .I1(\blk00000001/sig00000462 ), + .I2(\blk00000001/sig00000443 ), + .O(\blk00000001/sig000005d6 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk0000064a ( + .I0(\blk00000001/sig00000450 ), + .I1(\blk00000001/sig00000461 ), + .I2(\blk00000001/sig00000443 ), + .O(\blk00000001/sig000005d7 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000649 ( + .I0(\blk00000001/sig0000044f ), + .I1(\blk00000001/sig00000460 ), + .I2(\blk00000001/sig00000443 ), + .O(\blk00000001/sig000005d8 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000648 ( + .I0(\blk00000001/sig0000044e ), + .I1(\blk00000001/sig0000045f ), + .I2(\blk00000001/sig00000443 ), + .O(\blk00000001/sig000005d9 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000647 ( + .I0(\blk00000001/sig00000444 ), + .I1(\blk00000001/sig00000455 ), + .I2(\blk00000001/sig00000443 ), + .O(\blk00000001/sig000005e4 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000646 ( + .I0(\blk00000001/sig00000498 ), + .I1(\blk00000001/sig000004a9 ), + .I2(\blk00000001/sig0000048e ), + .O(\blk00000001/sig000005b9 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000645 ( + .I0(\blk00000001/sig00000497 ), + .I1(\blk00000001/sig000004a8 ), + .I2(\blk00000001/sig0000048e ), + .O(\blk00000001/sig000005ba ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000644 ( + .I0(\blk00000001/sig00000496 ), + .I1(\blk00000001/sig000004a7 ), + .I2(\blk00000001/sig0000048e ), + .O(\blk00000001/sig000005bb ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000643 ( + .I0(\blk00000001/sig00000495 ), + .I1(\blk00000001/sig000004a6 ), + .I2(\blk00000001/sig0000048e ), + .O(\blk00000001/sig000005bc ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000642 ( + .I0(\blk00000001/sig00000494 ), + .I1(\blk00000001/sig000004a5 ), + .I2(\blk00000001/sig0000048e ), + .O(\blk00000001/sig000005bd ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000641 ( + .I0(\blk00000001/sig00000493 ), + .I1(\blk00000001/sig000004a4 ), + .I2(\blk00000001/sig0000048e ), + .O(\blk00000001/sig000005be ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000640 ( + .I0(\blk00000001/sig00000492 ), + .I1(\blk00000001/sig000004a3 ), + .I2(\blk00000001/sig0000048e ), + .O(\blk00000001/sig000005bf ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk0000063f ( + .I0(\blk00000001/sig00000491 ), + .I1(\blk00000001/sig000004a2 ), + .I2(\blk00000001/sig0000048e ), + .O(\blk00000001/sig000005c0 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk0000063e ( + .I0(\blk00000001/sig00000490 ), + .I1(\blk00000001/sig000004a1 ), + .I2(\blk00000001/sig0000048e ), + .O(\blk00000001/sig000005c1 ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \blk00000001/blk0000063d ( + .I0(\blk00000001/sig0000049f ), + .I1(\blk00000001/sig0000048e ), + .O(\blk00000001/sig000005c2 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk0000063c ( + .I0(\blk00000001/sig0000049e ), + .I1(\blk00000001/sig000004af ), + .I2(\blk00000001/sig0000048e ), + .O(\blk00000001/sig000005b3 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk0000063b ( + .I0(\blk00000001/sig0000049d ), + .I1(\blk00000001/sig000004ae ), + .I2(\blk00000001/sig0000048e ), + .O(\blk00000001/sig000005b4 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk0000063a ( + .I0(\blk00000001/sig0000049c ), + .I1(\blk00000001/sig000004ad ), + .I2(\blk00000001/sig0000048e ), + .O(\blk00000001/sig000005b5 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000639 ( + .I0(\blk00000001/sig0000049b ), + .I1(\blk00000001/sig000004ac ), + .I2(\blk00000001/sig0000048e ), + .O(\blk00000001/sig000005b6 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000638 ( + .I0(\blk00000001/sig0000049a ), + .I1(\blk00000001/sig000004ab ), + .I2(\blk00000001/sig0000048e ), + .O(\blk00000001/sig000005b7 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000637 ( + .I0(\blk00000001/sig00000499 ), + .I1(\blk00000001/sig000004aa ), + .I2(\blk00000001/sig0000048e ), + .O(\blk00000001/sig000005b8 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000636 ( + .I0(\blk00000001/sig0000048f ), + .I1(\blk00000001/sig000004a0 ), + .I2(\blk00000001/sig0000048e ), + .O(\blk00000001/sig000005c3 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000635 ( + .I0(\blk00000001/sig000004e3 ), + .I1(\blk00000001/sig000004f4 ), + .I2(\blk00000001/sig000004d9 ), + .O(\blk00000001/sig00000598 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000634 ( + .I0(\blk00000001/sig000004e2 ), + .I1(\blk00000001/sig000004f3 ), + .I2(\blk00000001/sig000004d9 ), + .O(\blk00000001/sig00000599 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000633 ( + .I0(\blk00000001/sig000004e1 ), + .I1(\blk00000001/sig000004f2 ), + .I2(\blk00000001/sig000004d9 ), + .O(\blk00000001/sig0000059a ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000632 ( + .I0(\blk00000001/sig000004e0 ), + .I1(\blk00000001/sig000004f1 ), + .I2(\blk00000001/sig000004d9 ), + .O(\blk00000001/sig0000059b ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000631 ( + .I0(\blk00000001/sig000004df ), + .I1(\blk00000001/sig000004f0 ), + .I2(\blk00000001/sig000004d9 ), + .O(\blk00000001/sig0000059c ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000630 ( + .I0(\blk00000001/sig000004de ), + .I1(\blk00000001/sig000004ef ), + .I2(\blk00000001/sig000004d9 ), + .O(\blk00000001/sig0000059d ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk0000062f ( + .I0(\blk00000001/sig000004dd ), + .I1(\blk00000001/sig000004ee ), + .I2(\blk00000001/sig000004d9 ), + .O(\blk00000001/sig0000059e ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk0000062e ( + .I0(\blk00000001/sig000004dc ), + .I1(\blk00000001/sig000004ed ), + .I2(\blk00000001/sig000004d9 ), + .O(\blk00000001/sig0000059f ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk0000062d ( + .I0(\blk00000001/sig000004db ), + .I1(\blk00000001/sig000004ec ), + .I2(\blk00000001/sig000004d9 ), + .O(\blk00000001/sig000005a0 ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \blk00000001/blk0000062c ( + .I0(\blk00000001/sig000004ea ), + .I1(\blk00000001/sig000004d9 ), + .O(\blk00000001/sig000005a1 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk0000062b ( + .I0(\blk00000001/sig000004e9 ), + .I1(\blk00000001/sig000004fa ), + .I2(\blk00000001/sig000004d9 ), + .O(\blk00000001/sig00000592 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk0000062a ( + .I0(\blk00000001/sig000004e8 ), + .I1(\blk00000001/sig000004f9 ), + .I2(\blk00000001/sig000004d9 ), + .O(\blk00000001/sig00000593 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000629 ( + .I0(\blk00000001/sig000004e7 ), + .I1(\blk00000001/sig000004f8 ), + .I2(\blk00000001/sig000004d9 ), + .O(\blk00000001/sig00000594 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000628 ( + .I0(\blk00000001/sig000004e6 ), + .I1(\blk00000001/sig000004f7 ), + .I2(\blk00000001/sig000004d9 ), + .O(\blk00000001/sig00000595 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000627 ( + .I0(\blk00000001/sig000004e5 ), + .I1(\blk00000001/sig000004f6 ), + .I2(\blk00000001/sig000004d9 ), + .O(\blk00000001/sig00000596 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000626 ( + .I0(\blk00000001/sig000004e4 ), + .I1(\blk00000001/sig000004f5 ), + .I2(\blk00000001/sig000004d9 ), + .O(\blk00000001/sig00000597 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000625 ( + .I0(\blk00000001/sig000004da ), + .I1(\blk00000001/sig000004eb ), + .I2(\blk00000001/sig000004d9 ), + .O(\blk00000001/sig000005a2 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000624 ( + .I0(\blk00000001/sig0000052e ), + .I1(\blk00000001/sig0000053f ), + .I2(\blk00000001/sig00000524 ), + .O(\blk00000001/sig00000577 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000623 ( + .I0(\blk00000001/sig0000052d ), + .I1(\blk00000001/sig0000053e ), + .I2(\blk00000001/sig00000524 ), + .O(\blk00000001/sig00000578 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000622 ( + .I0(\blk00000001/sig0000052c ), + .I1(\blk00000001/sig0000053d ), + .I2(\blk00000001/sig00000524 ), + .O(\blk00000001/sig00000579 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000621 ( + .I0(\blk00000001/sig0000052b ), + .I1(\blk00000001/sig0000053c ), + .I2(\blk00000001/sig00000524 ), + .O(\blk00000001/sig0000057a ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000620 ( + .I0(\blk00000001/sig0000052a ), + .I1(\blk00000001/sig0000053b ), + .I2(\blk00000001/sig00000524 ), + .O(\blk00000001/sig0000057b ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk0000061f ( + .I0(\blk00000001/sig00000529 ), + .I1(\blk00000001/sig0000053a ), + .I2(\blk00000001/sig00000524 ), + .O(\blk00000001/sig0000057c ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk0000061e ( + .I0(\blk00000001/sig00000528 ), + .I1(\blk00000001/sig00000539 ), + .I2(\blk00000001/sig00000524 ), + .O(\blk00000001/sig0000057d ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk0000061d ( + .I0(\blk00000001/sig00000527 ), + .I1(\blk00000001/sig00000538 ), + .I2(\blk00000001/sig00000524 ), + .O(\blk00000001/sig0000057e ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk0000061c ( + .I0(\blk00000001/sig00000526 ), + .I1(\blk00000001/sig00000537 ), + .I2(\blk00000001/sig00000524 ), + .O(\blk00000001/sig0000057f ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \blk00000001/blk0000061b ( + .I0(\blk00000001/sig00000535 ), + .I1(\blk00000001/sig00000524 ), + .O(\blk00000001/sig00000580 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk0000061a ( + .I0(\blk00000001/sig00000534 ), + .I1(\blk00000001/sig00000545 ), + .I2(\blk00000001/sig00000524 ), + .O(\blk00000001/sig00000571 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000619 ( + .I0(\blk00000001/sig00000533 ), + .I1(\blk00000001/sig00000544 ), + .I2(\blk00000001/sig00000524 ), + .O(\blk00000001/sig00000572 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000618 ( + .I0(\blk00000001/sig00000532 ), + .I1(\blk00000001/sig00000543 ), + .I2(\blk00000001/sig00000524 ), + .O(\blk00000001/sig00000573 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000617 ( + .I0(\blk00000001/sig00000531 ), + .I1(\blk00000001/sig00000542 ), + .I2(\blk00000001/sig00000524 ), + .O(\blk00000001/sig00000574 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000616 ( + .I0(\blk00000001/sig00000530 ), + .I1(\blk00000001/sig00000541 ), + .I2(\blk00000001/sig00000524 ), + .O(\blk00000001/sig00000575 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000615 ( + .I0(\blk00000001/sig0000052f ), + .I1(\blk00000001/sig00000540 ), + .I2(\blk00000001/sig00000524 ), + .O(\blk00000001/sig00000576 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000001/blk00000614 ( + .I0(\blk00000001/sig00000525 ), + .I1(\blk00000001/sig00000536 ), + .I2(\blk00000001/sig00000524 ), + .O(\blk00000001/sig00000581 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000001/blk00000613 ( + .I0(\blk00000001/sig00000123 ), + .I1(\blk00000001/sig00000122 ), + .O(\blk00000001/sig00000127 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000001/blk00000612 ( + .I0(\blk00000001/sig00000122 ), + .I1(\blk00000001/sig00000123 ), + .O(\blk00000001/sig00000126 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000001/blk00000611 ( + .I0(\blk00000001/sig00000122 ), + .I1(\blk00000001/sig00000123 ), + .O(\blk00000001/sig00000124 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000001/blk00000610 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000519 ), + .O(\blk00000001/sig000001d8 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000001/blk0000060f ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000518 ), + .O(\blk00000001/sig000001d7 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000001/blk0000060e ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000517 ), + .O(\blk00000001/sig000001d6 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000001/blk0000060d ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000516 ), + .O(\blk00000001/sig000001d5 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000001/blk0000060c ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000515 ), + .O(\blk00000001/sig000001d4 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000001/blk0000060b ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000514 ), + .O(\blk00000001/sig000001d3 ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \blk00000001/blk0000060a ( + .I0(\blk00000001/sig00000513 ), + .I1(\blk00000001/sig00000560 ), + .O(\blk00000001/sig000001d2 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000001/blk00000609 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000512 ), + .O(\blk00000001/sig000001d0 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000001/blk00000608 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000522 ), + .O(\blk00000001/sig000001e1 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000001/blk00000607 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000521 ), + .O(\blk00000001/sig000001e0 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000001/blk00000606 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000520 ), + .O(\blk00000001/sig000001df ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000001/blk00000605 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig0000051f ), + .O(\blk00000001/sig000001de ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000001/blk00000604 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig0000051e ), + .O(\blk00000001/sig000001dd ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000001/blk00000603 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig0000051d ), + .O(\blk00000001/sig000001dc ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000001/blk00000602 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig0000051c ), + .O(\blk00000001/sig000001db ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000001/blk00000601 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig0000051b ), + .O(\blk00000001/sig000001da ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000001/blk00000600 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig0000051a ), + .O(\blk00000001/sig000001d9 ) + ); + LUT2 #( + .INIT ( 4'hB )) + \blk00000001/blk000005ff ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000512 ), + .O(\blk00000001/sig000001cf ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005fe ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000519 ), + .I2(\blk00000001/sig000004ce ), + .O(\blk00000001/sig000001c5 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005fd ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000518 ), + .I2(\blk00000001/sig000004cd ), + .O(\blk00000001/sig000001c4 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005fc ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000517 ), + .I2(\blk00000001/sig000004cc ), + .O(\blk00000001/sig000001c3 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005fb ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000516 ), + .I2(\blk00000001/sig000004cb ), + .O(\blk00000001/sig000001c2 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005fa ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000515 ), + .I2(\blk00000001/sig000004ca ), + .O(\blk00000001/sig000001c1 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005f9 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000514 ), + .I2(\blk00000001/sig000004c9 ), + .O(\blk00000001/sig000001c0 ) + ); + LUT3 #( + .INIT ( 8'hCA )) + \blk00000001/blk000005f8 ( + .I0(\blk00000001/sig000004c8 ), + .I1(\blk00000001/sig00000513 ), + .I2(\blk00000001/sig00000560 ), + .O(\blk00000001/sig000001bf ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005f7 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000512 ), + .I2(\blk00000001/sig000004c7 ), + .O(\blk00000001/sig000001bd ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005f6 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000522 ), + .I2(\blk00000001/sig000004d7 ), + .O(\blk00000001/sig000001ce ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005f5 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000521 ), + .I2(\blk00000001/sig000004d6 ), + .O(\blk00000001/sig000001cd ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005f4 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000520 ), + .I2(\blk00000001/sig000004d5 ), + .O(\blk00000001/sig000001cc ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005f3 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig0000051f ), + .I2(\blk00000001/sig000004d4 ), + .O(\blk00000001/sig000001cb ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005f2 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig0000051e ), + .I2(\blk00000001/sig000004d3 ), + .O(\blk00000001/sig000001ca ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005f1 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig0000051d ), + .I2(\blk00000001/sig000004d2 ), + .O(\blk00000001/sig000001c9 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005f0 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig0000051c ), + .I2(\blk00000001/sig000004d1 ), + .O(\blk00000001/sig000001c8 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005ef ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig0000051b ), + .I2(\blk00000001/sig000004d0 ), + .O(\blk00000001/sig000001c7 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005ee ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig0000051a ), + .I2(\blk00000001/sig000004cf ), + .O(\blk00000001/sig000001c6 ) + ); + LUT3 #( + .INIT ( 8'h27 )) + \blk00000001/blk000005ed ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000512 ), + .I2(\blk00000001/sig000004c7 ), + .O(\blk00000001/sig000001bc ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005ec ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig000004ce ), + .I2(\blk00000001/sig00000483 ), + .O(\blk00000001/sig000001b2 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005eb ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig000004cd ), + .I2(\blk00000001/sig00000482 ), + .O(\blk00000001/sig000001b1 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005ea ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig000004cc ), + .I2(\blk00000001/sig00000481 ), + .O(\blk00000001/sig000001b0 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005e9 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig000004cb ), + .I2(\blk00000001/sig00000480 ), + .O(\blk00000001/sig000001af ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005e8 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig000004ca ), + .I2(\blk00000001/sig0000047f ), + .O(\blk00000001/sig000001ae ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005e7 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig000004c9 ), + .I2(\blk00000001/sig0000047e ), + .O(\blk00000001/sig000001ad ) + ); + LUT3 #( + .INIT ( 8'hCA )) + \blk00000001/blk000005e6 ( + .I0(\blk00000001/sig0000047d ), + .I1(\blk00000001/sig000004c8 ), + .I2(\blk00000001/sig00000560 ), + .O(\blk00000001/sig000001ac ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005e5 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig000004c7 ), + .I2(\blk00000001/sig0000047c ), + .O(\blk00000001/sig000001aa ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005e4 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig000004d7 ), + .I2(\blk00000001/sig0000048c ), + .O(\blk00000001/sig000001bb ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005e3 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig000004d6 ), + .I2(\blk00000001/sig0000048b ), + .O(\blk00000001/sig000001ba ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005e2 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig000004d5 ), + .I2(\blk00000001/sig0000048a ), + .O(\blk00000001/sig000001b9 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005e1 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig000004d4 ), + .I2(\blk00000001/sig00000489 ), + .O(\blk00000001/sig000001b8 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005e0 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig000004d3 ), + .I2(\blk00000001/sig00000488 ), + .O(\blk00000001/sig000001b7 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005df ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig000004d2 ), + .I2(\blk00000001/sig00000487 ), + .O(\blk00000001/sig000001b6 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005de ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig000004d1 ), + .I2(\blk00000001/sig00000486 ), + .O(\blk00000001/sig000001b5 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005dd ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig000004d0 ), + .I2(\blk00000001/sig00000485 ), + .O(\blk00000001/sig000001b4 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005dc ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig000004cf ), + .I2(\blk00000001/sig00000484 ), + .O(\blk00000001/sig000001b3 ) + ); + LUT3 #( + .INIT ( 8'h27 )) + \blk00000001/blk000005db ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig000004c7 ), + .I2(\blk00000001/sig0000047c ), + .O(\blk00000001/sig000001a9 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005da ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000483 ), + .I2(\blk00000001/sig00000438 ), + .O(\blk00000001/sig0000019f ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005d9 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000482 ), + .I2(\blk00000001/sig00000437 ), + .O(\blk00000001/sig0000019e ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005d8 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000481 ), + .I2(\blk00000001/sig00000436 ), + .O(\blk00000001/sig0000019d ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005d7 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000480 ), + .I2(\blk00000001/sig00000435 ), + .O(\blk00000001/sig0000019c ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005d6 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig0000047f ), + .I2(\blk00000001/sig00000434 ), + .O(\blk00000001/sig0000019b ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005d5 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig0000047e ), + .I2(\blk00000001/sig00000433 ), + .O(\blk00000001/sig0000019a ) + ); + LUT3 #( + .INIT ( 8'hCA )) + \blk00000001/blk000005d4 ( + .I0(\blk00000001/sig00000432 ), + .I1(\blk00000001/sig0000047d ), + .I2(\blk00000001/sig00000560 ), + .O(\blk00000001/sig00000199 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005d3 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig0000047c ), + .I2(\blk00000001/sig00000431 ), + .O(\blk00000001/sig00000197 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005d2 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig0000048c ), + .I2(\blk00000001/sig00000441 ), + .O(\blk00000001/sig000001a8 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005d1 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig0000048b ), + .I2(\blk00000001/sig00000440 ), + .O(\blk00000001/sig000001a7 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005d0 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig0000048a ), + .I2(\blk00000001/sig0000043f ), + .O(\blk00000001/sig000001a6 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005cf ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000489 ), + .I2(\blk00000001/sig0000043e ), + .O(\blk00000001/sig000001a5 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005ce ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000488 ), + .I2(\blk00000001/sig0000043d ), + .O(\blk00000001/sig000001a4 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005cd ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000487 ), + .I2(\blk00000001/sig0000043c ), + .O(\blk00000001/sig000001a3 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005cc ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000486 ), + .I2(\blk00000001/sig0000043b ), + .O(\blk00000001/sig000001a2 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005cb ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000485 ), + .I2(\blk00000001/sig0000043a ), + .O(\blk00000001/sig000001a1 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005ca ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000484 ), + .I2(\blk00000001/sig00000439 ), + .O(\blk00000001/sig000001a0 ) + ); + LUT3 #( + .INIT ( 8'h27 )) + \blk00000001/blk000005c9 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig0000047c ), + .I2(\blk00000001/sig00000431 ), + .O(\blk00000001/sig00000196 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005c8 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000438 ), + .I2(\blk00000001/sig000003ed ), + .O(\blk00000001/sig0000018c ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005c7 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000437 ), + .I2(\blk00000001/sig000003ec ), + .O(\blk00000001/sig0000018b ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005c6 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000436 ), + .I2(\blk00000001/sig000003eb ), + .O(\blk00000001/sig0000018a ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005c5 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000435 ), + .I2(\blk00000001/sig000003ea ), + .O(\blk00000001/sig00000189 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005c4 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000434 ), + .I2(\blk00000001/sig000003e9 ), + .O(\blk00000001/sig00000188 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005c3 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000433 ), + .I2(\blk00000001/sig000003e8 ), + .O(\blk00000001/sig00000187 ) + ); + LUT3 #( + .INIT ( 8'hCA )) + \blk00000001/blk000005c2 ( + .I0(\blk00000001/sig000003e7 ), + .I1(\blk00000001/sig00000432 ), + .I2(\blk00000001/sig00000560 ), + .O(\blk00000001/sig00000186 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005c1 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000431 ), + .I2(\blk00000001/sig000003e6 ), + .O(\blk00000001/sig00000184 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005c0 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000441 ), + .I2(\blk00000001/sig000003f6 ), + .O(\blk00000001/sig00000195 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005bf ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000440 ), + .I2(\blk00000001/sig000003f5 ), + .O(\blk00000001/sig00000194 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005be ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig0000043f ), + .I2(\blk00000001/sig000003f4 ), + .O(\blk00000001/sig00000193 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005bd ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig0000043e ), + .I2(\blk00000001/sig000003f3 ), + .O(\blk00000001/sig00000192 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005bc ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig0000043d ), + .I2(\blk00000001/sig000003f2 ), + .O(\blk00000001/sig00000191 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005bb ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig0000043c ), + .I2(\blk00000001/sig000003f1 ), + .O(\blk00000001/sig00000190 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005ba ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig0000043b ), + .I2(\blk00000001/sig000003f0 ), + .O(\blk00000001/sig0000018f ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005b9 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig0000043a ), + .I2(\blk00000001/sig000003ef ), + .O(\blk00000001/sig0000018e ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005b8 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000439 ), + .I2(\blk00000001/sig000003ee ), + .O(\blk00000001/sig0000018d ) + ); + LUT3 #( + .INIT ( 8'h27 )) + \blk00000001/blk000005b7 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000431 ), + .I2(\blk00000001/sig000003e6 ), + .O(\blk00000001/sig00000183 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005b6 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig000003ed ), + .I2(\blk00000001/sig000003a2 ), + .O(\blk00000001/sig00000179 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005b5 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig000003ec ), + .I2(\blk00000001/sig000003a1 ), + .O(\blk00000001/sig00000178 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005b4 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig000003eb ), + .I2(\blk00000001/sig000003a0 ), + .O(\blk00000001/sig00000177 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005b3 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig000003ea ), + .I2(\blk00000001/sig0000039f ), + .O(\blk00000001/sig00000176 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005b2 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig000003e9 ), + .I2(\blk00000001/sig0000039e ), + .O(\blk00000001/sig00000175 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005b1 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig000003e8 ), + .I2(\blk00000001/sig0000039d ), + .O(\blk00000001/sig00000174 ) + ); + LUT3 #( + .INIT ( 8'hCA )) + \blk00000001/blk000005b0 ( + .I0(\blk00000001/sig0000039c ), + .I1(\blk00000001/sig000003e7 ), + .I2(\blk00000001/sig00000560 ), + .O(\blk00000001/sig00000173 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005af ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig000003e6 ), + .I2(\blk00000001/sig0000039b ), + .O(\blk00000001/sig00000171 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005ae ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig000003f6 ), + .I2(\blk00000001/sig000003ab ), + .O(\blk00000001/sig00000182 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005ad ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig000003f5 ), + .I2(\blk00000001/sig000003aa ), + .O(\blk00000001/sig00000181 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005ac ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig000003f4 ), + .I2(\blk00000001/sig000003a9 ), + .O(\blk00000001/sig00000180 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005ab ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig000003f3 ), + .I2(\blk00000001/sig000003a8 ), + .O(\blk00000001/sig0000017f ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005aa ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig000003f2 ), + .I2(\blk00000001/sig000003a7 ), + .O(\blk00000001/sig0000017e ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005a9 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig000003f1 ), + .I2(\blk00000001/sig000003a6 ), + .O(\blk00000001/sig0000017d ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005a8 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig000003f0 ), + .I2(\blk00000001/sig000003a5 ), + .O(\blk00000001/sig0000017c ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005a7 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig000003ef ), + .I2(\blk00000001/sig000003a4 ), + .O(\blk00000001/sig0000017b ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005a6 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig000003ee ), + .I2(\blk00000001/sig000003a3 ), + .O(\blk00000001/sig0000017a ) + ); + LUT3 #( + .INIT ( 8'h27 )) + \blk00000001/blk000005a5 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig000003e6 ), + .I2(\blk00000001/sig0000039b ), + .O(\blk00000001/sig00000170 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005a4 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig000003a2 ), + .I2(\blk00000001/sig00000357 ), + .O(\blk00000001/sig00000166 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005a3 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig000003a1 ), + .I2(\blk00000001/sig00000356 ), + .O(\blk00000001/sig00000165 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005a2 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig000003a0 ), + .I2(\blk00000001/sig00000355 ), + .O(\blk00000001/sig00000164 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005a1 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig0000039f ), + .I2(\blk00000001/sig00000354 ), + .O(\blk00000001/sig00000163 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk000005a0 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig0000039e ), + .I2(\blk00000001/sig00000353 ), + .O(\blk00000001/sig00000162 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk0000059f ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig0000039d ), + .I2(\blk00000001/sig00000352 ), + .O(\blk00000001/sig00000161 ) + ); + LUT3 #( + .INIT ( 8'hCA )) + \blk00000001/blk0000059e ( + .I0(\blk00000001/sig00000351 ), + .I1(\blk00000001/sig0000039c ), + .I2(\blk00000001/sig00000560 ), + .O(\blk00000001/sig00000160 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk0000059d ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig0000039b ), + .I2(\blk00000001/sig00000350 ), + .O(\blk00000001/sig0000015f ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk0000059c ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig000003ab ), + .I2(\blk00000001/sig00000360 ), + .O(\blk00000001/sig0000016f ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk0000059b ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig000003aa ), + .I2(\blk00000001/sig0000035f ), + .O(\blk00000001/sig0000016e ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk0000059a ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig000003a9 ), + .I2(\blk00000001/sig0000035e ), + .O(\blk00000001/sig0000016d ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk00000599 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig000003a8 ), + .I2(\blk00000001/sig0000035d ), + .O(\blk00000001/sig0000016c ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk00000598 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig000003a7 ), + .I2(\blk00000001/sig0000035c ), + .O(\blk00000001/sig0000016b ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk00000597 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig000003a6 ), + .I2(\blk00000001/sig0000035b ), + .O(\blk00000001/sig0000016a ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk00000596 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig000003a5 ), + .I2(\blk00000001/sig0000035a ), + .O(\blk00000001/sig00000169 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk00000595 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig000003a4 ), + .I2(\blk00000001/sig00000359 ), + .O(\blk00000001/sig00000168 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk00000594 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig000003a3 ), + .I2(\blk00000001/sig00000358 ), + .O(\blk00000001/sig00000167 ) + ); + LUT3 #( + .INIT ( 8'h27 )) + \blk00000001/blk00000593 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig0000039b ), + .I2(\blk00000001/sig00000350 ), + .O(\blk00000001/sig0000015e ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk00000592 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000357 ), + .I2(\blk00000001/sig00000309 ), + .O(\blk00000001/sig00000154 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk00000591 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000356 ), + .I2(\blk00000001/sig00000308 ), + .O(\blk00000001/sig00000153 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk00000590 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000355 ), + .I2(\blk00000001/sig00000307 ), + .O(\blk00000001/sig00000152 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk0000058f ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000354 ), + .I2(\blk00000001/sig00000306 ), + .O(\blk00000001/sig00000151 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk0000058e ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000353 ), + .I2(\blk00000001/sig00000305 ), + .O(\blk00000001/sig00000150 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk0000058d ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000352 ), + .I2(\blk00000001/sig00000304 ), + .O(\blk00000001/sig0000014f ) + ); + LUT3 #( + .INIT ( 8'hCA )) + \blk00000001/blk0000058c ( + .I0(\blk00000001/sig00000303 ), + .I1(\blk00000001/sig00000351 ), + .I2(\blk00000001/sig00000560 ), + .O(\blk00000001/sig0000014e ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk0000058b ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000350 ), + .I2(\blk00000001/sig00000302 ), + .O(\blk00000001/sig0000014d ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk0000058a ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000360 ), + .I2(\blk00000001/sig00000312 ), + .O(\blk00000001/sig0000015d ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk00000589 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig0000035f ), + .I2(\blk00000001/sig00000311 ), + .O(\blk00000001/sig0000015c ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk00000588 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig0000035e ), + .I2(\blk00000001/sig00000310 ), + .O(\blk00000001/sig0000015b ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk00000587 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig0000035d ), + .I2(\blk00000001/sig0000030f ), + .O(\blk00000001/sig0000015a ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk00000586 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig0000035c ), + .I2(\blk00000001/sig0000030e ), + .O(\blk00000001/sig00000159 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk00000585 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig0000035b ), + .I2(\blk00000001/sig0000030d ), + .O(\blk00000001/sig00000158 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk00000584 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig0000035a ), + .I2(\blk00000001/sig0000030c ), + .O(\blk00000001/sig00000157 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk00000583 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000359 ), + .I2(\blk00000001/sig0000030b ), + .O(\blk00000001/sig00000156 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk00000582 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000358 ), + .I2(\blk00000001/sig0000030a ), + .O(\blk00000001/sig00000155 ) + ); + LUT3 #( + .INIT ( 8'h27 )) + \blk00000001/blk00000581 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000350 ), + .I2(\blk00000001/sig00000302 ), + .O(\blk00000001/sig0000014c ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk00000580 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000309 ), + .I2(\blk00000001/sig000002b7 ), + .O(\blk00000001/sig00000142 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk0000057f ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000308 ), + .I2(\blk00000001/sig000002b6 ), + .O(\blk00000001/sig00000141 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk0000057e ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000307 ), + .I2(\blk00000001/sig000002b5 ), + .O(\blk00000001/sig00000140 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk0000057d ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000306 ), + .I2(\blk00000001/sig000002b4 ), + .O(\blk00000001/sig0000013f ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk0000057c ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000305 ), + .I2(\blk00000001/sig000002b3 ), + .O(\blk00000001/sig0000013e ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk0000057b ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000304 ), + .I2(\blk00000001/sig000002b2 ), + .O(\blk00000001/sig0000013d ) + ); + LUT3 #( + .INIT ( 8'hCA )) + \blk00000001/blk0000057a ( + .I0(\blk00000001/sig000002b1 ), + .I1(\blk00000001/sig00000303 ), + .I2(\blk00000001/sig00000560 ), + .O(\blk00000001/sig0000013c ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk00000579 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000302 ), + .I2(\blk00000001/sig000002b0 ), + .O(\blk00000001/sig0000013b ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk00000578 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000312 ), + .I2(\blk00000001/sig000002c0 ), + .O(\blk00000001/sig0000014b ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk00000577 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000311 ), + .I2(\blk00000001/sig000002bf ), + .O(\blk00000001/sig0000014a ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk00000576 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000310 ), + .I2(\blk00000001/sig000002be ), + .O(\blk00000001/sig00000149 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk00000575 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig0000030f ), + .I2(\blk00000001/sig000002bd ), + .O(\blk00000001/sig00000148 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk00000574 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig0000030e ), + .I2(\blk00000001/sig000002bc ), + .O(\blk00000001/sig00000147 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk00000573 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig0000030d ), + .I2(\blk00000001/sig000002bb ), + .O(\blk00000001/sig00000146 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk00000572 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig0000030c ), + .I2(\blk00000001/sig000002ba ), + .O(\blk00000001/sig00000145 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk00000571 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig0000030b ), + .I2(\blk00000001/sig000002b9 ), + .O(\blk00000001/sig00000144 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000001/blk00000570 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig0000030a ), + .I2(\blk00000001/sig000002b8 ), + .O(\blk00000001/sig00000143 ) + ); + LUT3 #( + .INIT ( 8'h27 )) + \blk00000001/blk0000056f ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000302 ), + .I2(\blk00000001/sig000002b0 ), + .O(\blk00000001/sig0000013a ) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \blk00000001/blk0000056e ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000261 ), + .I2(\blk00000001/sig000002b7 ), + .O(\blk00000001/sig00000130 ) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \blk00000001/blk0000056d ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000260 ), + .I2(\blk00000001/sig000002b6 ), + .O(\blk00000001/sig0000012f ) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \blk00000001/blk0000056c ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig0000025f ), + .I2(\blk00000001/sig000002b5 ), + .O(\blk00000001/sig0000012e ) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \blk00000001/blk0000056b ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig0000025e ), + .I2(\blk00000001/sig000002b4 ), + .O(\blk00000001/sig0000012d ) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \blk00000001/blk0000056a ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig0000025d ), + .I2(\blk00000001/sig000002b3 ), + .O(\blk00000001/sig0000012c ) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \blk00000001/blk00000569 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig0000025c ), + .I2(\blk00000001/sig000002b2 ), + .O(\blk00000001/sig0000012b ) + ); + LUT3 #( + .INIT ( 8'hCA )) + \blk00000001/blk00000568 ( + .I0(\blk00000001/sig0000025b ), + .I1(\blk00000001/sig000002b1 ), + .I2(\blk00000001/sig00000560 ), + .O(\blk00000001/sig0000012a ) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \blk00000001/blk00000567 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig0000025a ), + .I2(\blk00000001/sig000002b0 ), + .O(\blk00000001/sig00000129 ) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \blk00000001/blk00000566 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig0000026a ), + .I2(\blk00000001/sig000002c0 ), + .O(\blk00000001/sig00000139 ) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \blk00000001/blk00000565 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000269 ), + .I2(\blk00000001/sig000002bf ), + .O(\blk00000001/sig00000138 ) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \blk00000001/blk00000564 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000268 ), + .I2(\blk00000001/sig000002be ), + .O(\blk00000001/sig00000137 ) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \blk00000001/blk00000563 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000267 ), + .I2(\blk00000001/sig000002bd ), + .O(\blk00000001/sig00000136 ) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \blk00000001/blk00000562 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000266 ), + .I2(\blk00000001/sig000002bc ), + .O(\blk00000001/sig00000135 ) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \blk00000001/blk00000561 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000265 ), + .I2(\blk00000001/sig000002bb ), + .O(\blk00000001/sig00000134 ) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \blk00000001/blk00000560 ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000264 ), + .I2(\blk00000001/sig000002ba ), + .O(\blk00000001/sig00000133 ) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \blk00000001/blk0000055f ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000263 ), + .I2(\blk00000001/sig000002b9 ), + .O(\blk00000001/sig00000132 ) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \blk00000001/blk0000055e ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig00000262 ), + .I2(\blk00000001/sig000002b8 ), + .O(\blk00000001/sig00000131 ) + ); + LUT3 #( + .INIT ( 8'h1B )) + \blk00000001/blk0000055d ( + .I0(\blk00000001/sig00000560 ), + .I1(\blk00000001/sig0000025a ), + .I2(\blk00000001/sig000002b0 ), + .O(\blk00000001/sig00000128 ) + ); + LUT6 #( + .INIT ( 64'hFD75B931EC64A820 )) + \blk00000001/blk0000055c ( + .I0(\blk00000001/sig0000055e ), + .I1(\blk00000001/sig0000055f ), + .I2(\blk00000001/sig0000055c ), + .I3(\blk00000001/sig0000055a ), + .I4(\blk00000001/sig0000055b ), + .I5(\blk00000001/sig0000055d ), + .O(\blk00000001/sig000001d1 ) + ); + LUT6 #( + .INIT ( 64'hFD75B931EC64A820 )) + \blk00000001/blk0000055b ( + .I0(\blk00000001/sig0000055e ), + .I1(\blk00000001/sig0000055f ), + .I2(\blk00000001/sig0000046f ), + .I3(\blk00000001/sig0000046d ), + .I4(\blk00000001/sig0000046e ), + .I5(\blk00000001/sig00000470 ), + .O(\blk00000001/sig00000198 ) + ); + LUT6 #( + .INIT ( 64'hFD75B931EC64A820 )) + \blk00000001/blk0000055a ( + .I0(\blk00000001/sig0000055e ), + .I1(\blk00000001/sig0000055f ), + .I2(\blk00000001/sig00000420 ), + .I3(\blk00000001/sig0000041e ), + .I4(\blk00000001/sig0000041f ), + .I5(\blk00000001/sig00000421 ), + .O(\blk00000001/sig00000185 ) + ); + LUT6 #( + .INIT ( 64'hFD75B931EC64A820 )) + \blk00000001/blk00000559 ( + .I0(\blk00000001/sig0000055e ), + .I1(\blk00000001/sig0000055f ), + .I2(\blk00000001/sig000003d1 ), + .I3(\blk00000001/sig000003cf ), + .I4(\blk00000001/sig000003d0 ), + .I5(\blk00000001/sig000003d2 ), + .O(\blk00000001/sig00000172 ) + ); + LUT6 #( + .INIT ( 64'hFD75B931EC64A820 )) + \blk00000001/blk00000558 ( + .I0(\blk00000001/sig0000055e ), + .I1(\blk00000001/sig0000055f ), + .I2(\blk00000001/sig0000050d ), + .I3(\blk00000001/sig0000050b ), + .I4(\blk00000001/sig0000050c ), + .I5(\blk00000001/sig0000050e ), + .O(\blk00000001/sig000001be ) + ); + LUT6 #( + .INIT ( 64'hFD75B931EC64A820 )) + \blk00000001/blk00000557 ( + .I0(\blk00000001/sig0000055e ), + .I1(\blk00000001/sig0000055f ), + .I2(\blk00000001/sig000004be ), + .I3(\blk00000001/sig000004bc ), + .I4(\blk00000001/sig000004bd ), + .I5(\blk00000001/sig000004bf ), + .O(\blk00000001/sig000001ab ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000001/blk00000556 ( + .I0(s_axis_divisor_tdata[9]), + .I1(s_axis_divisor_tdata[15]), + .O(\blk00000001/sig0000011a ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000001/blk00000555 ( + .I0(s_axis_divisor_tdata[8]), + .I1(s_axis_divisor_tdata[15]), + .O(\blk00000001/sig00000119 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000001/blk00000554 ( + .I0(s_axis_divisor_tdata[7]), + .I1(s_axis_divisor_tdata[15]), + .O(\blk00000001/sig00000118 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000001/blk00000553 ( + .I0(s_axis_divisor_tdata[6]), + .I1(s_axis_divisor_tdata[15]), + .O(\blk00000001/sig00000117 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000001/blk00000552 ( + .I0(s_axis_divisor_tdata[5]), + .I1(s_axis_divisor_tdata[15]), + .O(\blk00000001/sig00000116 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000001/blk00000551 ( + .I0(s_axis_divisor_tdata[4]), + .I1(s_axis_divisor_tdata[15]), + .O(\blk00000001/sig00000115 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000001/blk00000550 ( + .I0(s_axis_divisor_tdata[3]), + .I1(s_axis_divisor_tdata[15]), + .O(\blk00000001/sig00000114 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000001/blk0000054f ( + .I0(s_axis_divisor_tdata[2]), + .I1(s_axis_divisor_tdata[15]), + .O(\blk00000001/sig00000113 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000001/blk0000054e ( + .I0(s_axis_divisor_tdata[1]), + .I1(s_axis_divisor_tdata[15]), + .O(\blk00000001/sig00000112 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000001/blk0000054d ( + .I0(s_axis_divisor_tdata[14]), + .I1(s_axis_divisor_tdata[15]), + .O(\blk00000001/sig0000011f ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000001/blk0000054c ( + .I0(s_axis_divisor_tdata[13]), + .I1(s_axis_divisor_tdata[15]), + .O(\blk00000001/sig0000011e ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000001/blk0000054b ( + .I0(s_axis_divisor_tdata[12]), + .I1(s_axis_divisor_tdata[15]), + .O(\blk00000001/sig0000011d ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000001/blk0000054a ( + .I0(s_axis_divisor_tdata[11]), + .I1(s_axis_divisor_tdata[15]), + .O(\blk00000001/sig0000011c ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000001/blk00000549 ( + .I0(s_axis_divisor_tdata[10]), + .I1(s_axis_divisor_tdata[15]), + .O(\blk00000001/sig0000011b ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000001/blk00000548 ( + .I0(s_axis_dividend_tdata[9]), + .I1(s_axis_dividend_tdata[23]), + .O(\blk00000001/sig000000e5 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000001/blk00000547 ( + .I0(s_axis_dividend_tdata[8]), + .I1(s_axis_dividend_tdata[23]), + .O(\blk00000001/sig000000e4 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000001/blk00000546 ( + .I0(s_axis_dividend_tdata[7]), + .I1(s_axis_dividend_tdata[23]), + .O(\blk00000001/sig000000e3 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000001/blk00000545 ( + .I0(s_axis_dividend_tdata[6]), + .I1(s_axis_dividend_tdata[23]), + .O(\blk00000001/sig000000e2 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000001/blk00000544 ( + .I0(s_axis_dividend_tdata[5]), + .I1(s_axis_dividend_tdata[23]), + .O(\blk00000001/sig000000e1 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000001/blk00000543 ( + .I0(s_axis_dividend_tdata[4]), + .I1(s_axis_dividend_tdata[23]), + .O(\blk00000001/sig000000e0 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000001/blk00000542 ( + .I0(s_axis_dividend_tdata[3]), + .I1(s_axis_dividend_tdata[23]), + .O(\blk00000001/sig000000df ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000001/blk00000541 ( + .I0(s_axis_dividend_tdata[2]), + .I1(s_axis_dividend_tdata[23]), + .O(\blk00000001/sig000000de ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000001/blk00000540 ( + .I0(s_axis_dividend_tdata[22]), + .I1(s_axis_dividend_tdata[23]), + .O(\blk00000001/sig000000f2 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000001/blk0000053f ( + .I0(s_axis_dividend_tdata[21]), + .I1(s_axis_dividend_tdata[23]), + .O(\blk00000001/sig000000f1 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000001/blk0000053e ( + .I0(s_axis_dividend_tdata[20]), + .I1(s_axis_dividend_tdata[23]), + .O(\blk00000001/sig000000f0 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000001/blk0000053d ( + .I0(s_axis_dividend_tdata[1]), + .I1(s_axis_dividend_tdata[23]), + .O(\blk00000001/sig000000dd ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000001/blk0000053c ( + .I0(s_axis_dividend_tdata[19]), + .I1(s_axis_dividend_tdata[23]), + .O(\blk00000001/sig000000ef ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000001/blk0000053b ( + .I0(s_axis_dividend_tdata[18]), + .I1(s_axis_dividend_tdata[23]), + .O(\blk00000001/sig000000ee ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000001/blk0000053a ( + .I0(s_axis_dividend_tdata[17]), + .I1(s_axis_dividend_tdata[23]), + .O(\blk00000001/sig000000ed ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000001/blk00000539 ( + .I0(s_axis_dividend_tdata[16]), + .I1(s_axis_dividend_tdata[23]), + .O(\blk00000001/sig000000ec ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000001/blk00000538 ( + .I0(s_axis_dividend_tdata[15]), + .I1(s_axis_dividend_tdata[23]), + .O(\blk00000001/sig000000eb ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000001/blk00000537 ( + .I0(s_axis_dividend_tdata[14]), + .I1(s_axis_dividend_tdata[23]), + .O(\blk00000001/sig000000ea ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000001/blk00000536 ( + .I0(s_axis_dividend_tdata[13]), + .I1(s_axis_dividend_tdata[23]), + .O(\blk00000001/sig000000e9 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000001/blk00000535 ( + .I0(s_axis_dividend_tdata[12]), + .I1(s_axis_dividend_tdata[23]), + .O(\blk00000001/sig000000e8 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000001/blk00000534 ( + .I0(s_axis_dividend_tdata[11]), + .I1(s_axis_dividend_tdata[23]), + .O(\blk00000001/sig000000e7 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000001/blk00000533 ( + .I0(s_axis_dividend_tdata[10]), + .I1(s_axis_dividend_tdata[23]), + .O(\blk00000001/sig000000e6 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000001/blk00000532 ( + .I0(\blk00000001/sig00000080 ), + .I1(\blk00000001/sig00000081 ), + .O(\blk00000001/sig00000057 ) + ); + LUT3 #( + .INIT ( 8'h80 )) + \blk00000001/blk00000531 ( + .I0(NlwRenamedSig_OI_s_axis_dividend_tready), + .I1(s_axis_dividend_tvalid), + .I2(s_axis_divisor_tvalid), + .O(\blk00000001/sig00000056 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000530 ( + .C(aclk), + .D(\blk00000001/sig00000056 ), + .Q(\blk00000001/sig0000072e ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk0000052f ( + .C(aclk), + .D(\blk00000001/sig00000710 ), + .Q(m_axis_dout_tdata[0]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk0000052e ( + .C(aclk), + .D(\blk00000001/sig00000711 ), + .Q(m_axis_dout_tdata[1]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk0000052d ( + .C(aclk), + .D(\blk00000001/sig00000712 ), + .Q(m_axis_dout_tdata[2]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk0000052c ( + .C(aclk), + .D(\blk00000001/sig00000713 ), + .Q(m_axis_dout_tdata[3]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk0000052b ( + .C(aclk), + .D(\blk00000001/sig00000714 ), + .Q(m_axis_dout_tdata[4]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk0000052a ( + .C(aclk), + .D(\blk00000001/sig00000715 ), + .Q(m_axis_dout_tdata[5]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000529 ( + .C(aclk), + .D(\blk00000001/sig00000716 ), + .Q(m_axis_dout_tdata[6]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000528 ( + .C(aclk), + .D(\blk00000001/sig00000717 ), + .Q(m_axis_dout_tdata[7]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000527 ( + .C(aclk), + .D(\blk00000001/sig00000718 ), + .Q(m_axis_dout_tdata[8]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000526 ( + .C(aclk), + .D(\blk00000001/sig00000719 ), + .Q(m_axis_dout_tdata[9]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000525 ( + .C(aclk), + .D(\blk00000001/sig0000071a ), + .Q(m_axis_dout_tdata[10]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000524 ( + .C(aclk), + .D(\blk00000001/sig0000071b ), + .Q(m_axis_dout_tdata[11]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000523 ( + .C(aclk), + .D(\blk00000001/sig0000071c ), + .Q(m_axis_dout_tdata[12]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000522 ( + .C(aclk), + .D(\blk00000001/sig0000071d ), + .Q(m_axis_dout_tdata[13]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000521 ( + .C(aclk), + .D(\blk00000001/sig0000071e ), + .Q(m_axis_dout_tdata[14]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000520 ( + .C(aclk), + .D(\blk00000001/sig0000071f ), + .Q(m_axis_dout_tdata[15]) + ); + MUXCY \blk00000001/blk0000051f ( + .CI(\blk00000001/sig00000363 ), + .DI(\blk00000001/sig00000057 ), + .S(\blk00000001/sig00000733 ), + .O(\blk00000001/sig0000070f ) + ); + XORCY \blk00000001/blk0000051e ( + .CI(\blk00000001/sig00000363 ), + .LI(\blk00000001/sig00000733 ), + .O(\blk00000001/sig00000710 ) + ); + MUXCY \blk00000001/blk0000051d ( + .CI(\blk00000001/sig0000070f ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig00000720 ), + .O(\blk00000001/sig0000070e ) + ); + XORCY \blk00000001/blk0000051c ( + .CI(\blk00000001/sig0000070f ), + .LI(\blk00000001/sig00000720 ), + .O(\blk00000001/sig00000711 ) + ); + MUXCY \blk00000001/blk0000051b ( + .CI(\blk00000001/sig0000070e ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig00000721 ), + .O(\blk00000001/sig0000070d ) + ); + XORCY \blk00000001/blk0000051a ( + .CI(\blk00000001/sig0000070e ), + .LI(\blk00000001/sig00000721 ), + .O(\blk00000001/sig00000712 ) + ); + MUXCY \blk00000001/blk00000519 ( + .CI(\blk00000001/sig0000070d ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig00000722 ), + .O(\blk00000001/sig0000070c ) + ); + XORCY \blk00000001/blk00000518 ( + .CI(\blk00000001/sig0000070d ), + .LI(\blk00000001/sig00000722 ), + .O(\blk00000001/sig00000713 ) + ); + MUXCY \blk00000001/blk00000517 ( + .CI(\blk00000001/sig0000070c ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig00000723 ), + .O(\blk00000001/sig0000070b ) + ); + XORCY \blk00000001/blk00000516 ( + .CI(\blk00000001/sig0000070c ), + .LI(\blk00000001/sig00000723 ), + .O(\blk00000001/sig00000714 ) + ); + MUXCY \blk00000001/blk00000515 ( + .CI(\blk00000001/sig0000070b ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig00000724 ), + .O(\blk00000001/sig0000070a ) + ); + XORCY \blk00000001/blk00000514 ( + .CI(\blk00000001/sig0000070b ), + .LI(\blk00000001/sig00000724 ), + .O(\blk00000001/sig00000715 ) + ); + MUXCY \blk00000001/blk00000513 ( + .CI(\blk00000001/sig0000070a ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig00000725 ), + .O(\blk00000001/sig00000709 ) + ); + XORCY \blk00000001/blk00000512 ( + .CI(\blk00000001/sig0000070a ), + .LI(\blk00000001/sig00000725 ), + .O(\blk00000001/sig00000716 ) + ); + MUXCY \blk00000001/blk00000511 ( + .CI(\blk00000001/sig00000709 ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig00000726 ), + .O(\blk00000001/sig00000708 ) + ); + XORCY \blk00000001/blk00000510 ( + .CI(\blk00000001/sig00000709 ), + .LI(\blk00000001/sig00000726 ), + .O(\blk00000001/sig00000717 ) + ); + MUXCY \blk00000001/blk0000050f ( + .CI(\blk00000001/sig00000708 ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig00000727 ), + .O(\blk00000001/sig00000707 ) + ); + XORCY \blk00000001/blk0000050e ( + .CI(\blk00000001/sig00000708 ), + .LI(\blk00000001/sig00000727 ), + .O(\blk00000001/sig00000718 ) + ); + MUXCY \blk00000001/blk0000050d ( + .CI(\blk00000001/sig00000707 ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig00000728 ), + .O(\blk00000001/sig00000706 ) + ); + XORCY \blk00000001/blk0000050c ( + .CI(\blk00000001/sig00000707 ), + .LI(\blk00000001/sig00000728 ), + .O(\blk00000001/sig00000719 ) + ); + MUXCY \blk00000001/blk0000050b ( + .CI(\blk00000001/sig00000706 ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig00000729 ), + .O(\blk00000001/sig00000705 ) + ); + XORCY \blk00000001/blk0000050a ( + .CI(\blk00000001/sig00000706 ), + .LI(\blk00000001/sig00000729 ), + .O(\blk00000001/sig0000071a ) + ); + MUXCY \blk00000001/blk00000509 ( + .CI(\blk00000001/sig00000705 ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig0000072a ), + .O(\blk00000001/sig00000704 ) + ); + XORCY \blk00000001/blk00000508 ( + .CI(\blk00000001/sig00000705 ), + .LI(\blk00000001/sig0000072a ), + .O(\blk00000001/sig0000071b ) + ); + MUXCY \blk00000001/blk00000507 ( + .CI(\blk00000001/sig00000704 ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig0000072b ), + .O(\blk00000001/sig00000703 ) + ); + XORCY \blk00000001/blk00000506 ( + .CI(\blk00000001/sig00000704 ), + .LI(\blk00000001/sig0000072b ), + .O(\blk00000001/sig0000071c ) + ); + MUXCY \blk00000001/blk00000505 ( + .CI(\blk00000001/sig00000703 ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig0000072c ), + .O(\blk00000001/sig00000702 ) + ); + XORCY \blk00000001/blk00000504 ( + .CI(\blk00000001/sig00000703 ), + .LI(\blk00000001/sig0000072c ), + .O(\blk00000001/sig0000071d ) + ); + MUXCY \blk00000001/blk00000503 ( + .CI(\blk00000001/sig00000702 ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig0000072d ), + .O(\blk00000001/sig00000701 ) + ); + XORCY \blk00000001/blk00000502 ( + .CI(\blk00000001/sig00000702 ), + .LI(\blk00000001/sig0000072d ), + .O(\blk00000001/sig0000071e ) + ); + XORCY \blk00000001/blk00000501 ( + .CI(\blk00000001/sig00000701 ), + .LI(\blk00000001/sig0000072f ), + .O(\blk00000001/sig0000071f ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000500 ( + .C(aclk), + .D(\blk00000001/sig000006d2 ), + .Q(m_axis_dout_tdata[16]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk000004ff ( + .C(aclk), + .D(\blk00000001/sig000006d3 ), + .Q(m_axis_dout_tdata[17]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk000004fe ( + .C(aclk), + .D(\blk00000001/sig000006d4 ), + .Q(m_axis_dout_tdata[18]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk000004fd ( + .C(aclk), + .D(\blk00000001/sig000006d5 ), + .Q(m_axis_dout_tdata[19]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk000004fc ( + .C(aclk), + .D(\blk00000001/sig000006d6 ), + .Q(m_axis_dout_tdata[20]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk000004fb ( + .C(aclk), + .D(\blk00000001/sig000006d7 ), + .Q(m_axis_dout_tdata[21]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk000004fa ( + .C(aclk), + .D(\blk00000001/sig000006d8 ), + .Q(m_axis_dout_tdata[22]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk000004f9 ( + .C(aclk), + .D(\blk00000001/sig000006d9 ), + .Q(m_axis_dout_tdata[23]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk000004f8 ( + .C(aclk), + .D(\blk00000001/sig000006da ), + .Q(m_axis_dout_tdata[24]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk000004f7 ( + .C(aclk), + .D(\blk00000001/sig000006db ), + .Q(m_axis_dout_tdata[25]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk000004f6 ( + .C(aclk), + .D(\blk00000001/sig000006dc ), + .Q(m_axis_dout_tdata[26]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk000004f5 ( + .C(aclk), + .D(\blk00000001/sig000006dd ), + .Q(m_axis_dout_tdata[27]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk000004f4 ( + .C(aclk), + .D(\blk00000001/sig000006de ), + .Q(m_axis_dout_tdata[28]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk000004f3 ( + .C(aclk), + .D(\blk00000001/sig000006df ), + .Q(m_axis_dout_tdata[29]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk000004f2 ( + .C(aclk), + .D(\blk00000001/sig000006e0 ), + .Q(m_axis_dout_tdata[30]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk000004f1 ( + .C(aclk), + .D(\blk00000001/sig000006e1 ), + .Q(m_axis_dout_tdata[31]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk000004f0 ( + .C(aclk), + .D(\blk00000001/sig000006e2 ), + .Q(m_axis_dout_tdata[32]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk000004ef ( + .C(aclk), + .D(\blk00000001/sig000006e3 ), + .Q(m_axis_dout_tdata[33]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk000004ee ( + .C(aclk), + .D(\blk00000001/sig000006e4 ), + .Q(m_axis_dout_tdata[34]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk000004ed ( + .C(aclk), + .D(\blk00000001/sig000006e5 ), + .Q(m_axis_dout_tdata[35]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk000004ec ( + .C(aclk), + .D(\blk00000001/sig000006e6 ), + .Q(m_axis_dout_tdata[36]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk000004eb ( + .C(aclk), + .D(\blk00000001/sig000006e7 ), + .Q(m_axis_dout_tdata[37]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk000004ea ( + .C(aclk), + .D(\blk00000001/sig000006e8 ), + .Q(m_axis_dout_tdata[38]) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk000004e9 ( + .C(aclk), + .D(\blk00000001/sig000006e9 ), + .Q(m_axis_dout_tdata[39]) + ); + MUXCY \blk00000001/blk000004e8 ( + .CI(\blk00000001/sig00000363 ), + .DI(\blk00000001/sig00000057 ), + .S(\blk00000001/sig00000732 ), + .O(\blk00000001/sig000006d1 ) + ); + XORCY \blk00000001/blk000004e7 ( + .CI(\blk00000001/sig00000363 ), + .LI(\blk00000001/sig00000732 ), + .O(\blk00000001/sig000006d2 ) + ); + MUXCY \blk00000001/blk000004e6 ( + .CI(\blk00000001/sig000006d1 ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig000006ea ), + .O(\blk00000001/sig000006d0 ) + ); + XORCY \blk00000001/blk000004e5 ( + .CI(\blk00000001/sig000006d1 ), + .LI(\blk00000001/sig000006ea ), + .O(\blk00000001/sig000006d3 ) + ); + MUXCY \blk00000001/blk000004e4 ( + .CI(\blk00000001/sig000006d0 ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig000006eb ), + .O(\blk00000001/sig000006cf ) + ); + XORCY \blk00000001/blk000004e3 ( + .CI(\blk00000001/sig000006d0 ), + .LI(\blk00000001/sig000006eb ), + .O(\blk00000001/sig000006d4 ) + ); + MUXCY \blk00000001/blk000004e2 ( + .CI(\blk00000001/sig000006cf ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig000006ec ), + .O(\blk00000001/sig000006ce ) + ); + XORCY \blk00000001/blk000004e1 ( + .CI(\blk00000001/sig000006cf ), + .LI(\blk00000001/sig000006ec ), + .O(\blk00000001/sig000006d5 ) + ); + MUXCY \blk00000001/blk000004e0 ( + .CI(\blk00000001/sig000006ce ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig000006ed ), + .O(\blk00000001/sig000006cd ) + ); + XORCY \blk00000001/blk000004df ( + .CI(\blk00000001/sig000006ce ), + .LI(\blk00000001/sig000006ed ), + .O(\blk00000001/sig000006d6 ) + ); + MUXCY \blk00000001/blk000004de ( + .CI(\blk00000001/sig000006cd ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig000006ee ), + .O(\blk00000001/sig000006cc ) + ); + XORCY \blk00000001/blk000004dd ( + .CI(\blk00000001/sig000006cd ), + .LI(\blk00000001/sig000006ee ), + .O(\blk00000001/sig000006d7 ) + ); + MUXCY \blk00000001/blk000004dc ( + .CI(\blk00000001/sig000006cc ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig000006ef ), + .O(\blk00000001/sig000006cb ) + ); + XORCY \blk00000001/blk000004db ( + .CI(\blk00000001/sig000006cc ), + .LI(\blk00000001/sig000006ef ), + .O(\blk00000001/sig000006d8 ) + ); + MUXCY \blk00000001/blk000004da ( + .CI(\blk00000001/sig000006cb ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig000006f0 ), + .O(\blk00000001/sig000006ca ) + ); + XORCY \blk00000001/blk000004d9 ( + .CI(\blk00000001/sig000006cb ), + .LI(\blk00000001/sig000006f0 ), + .O(\blk00000001/sig000006d9 ) + ); + MUXCY \blk00000001/blk000004d8 ( + .CI(\blk00000001/sig000006ca ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig000006f1 ), + .O(\blk00000001/sig000006c9 ) + ); + XORCY \blk00000001/blk000004d7 ( + .CI(\blk00000001/sig000006ca ), + .LI(\blk00000001/sig000006f1 ), + .O(\blk00000001/sig000006da ) + ); + MUXCY \blk00000001/blk000004d6 ( + .CI(\blk00000001/sig000006c9 ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig000006f2 ), + .O(\blk00000001/sig000006c8 ) + ); + XORCY \blk00000001/blk000004d5 ( + .CI(\blk00000001/sig000006c9 ), + .LI(\blk00000001/sig000006f2 ), + .O(\blk00000001/sig000006db ) + ); + MUXCY \blk00000001/blk000004d4 ( + .CI(\blk00000001/sig000006c8 ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig000006f3 ), + .O(\blk00000001/sig000006c7 ) + ); + XORCY \blk00000001/blk000004d3 ( + .CI(\blk00000001/sig000006c8 ), + .LI(\blk00000001/sig000006f3 ), + .O(\blk00000001/sig000006dc ) + ); + MUXCY \blk00000001/blk000004d2 ( + .CI(\blk00000001/sig000006c7 ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig000006f4 ), + .O(\blk00000001/sig000006c6 ) + ); + XORCY \blk00000001/blk000004d1 ( + .CI(\blk00000001/sig000006c7 ), + .LI(\blk00000001/sig000006f4 ), + .O(\blk00000001/sig000006dd ) + ); + MUXCY \blk00000001/blk000004d0 ( + .CI(\blk00000001/sig000006c6 ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig000006f5 ), + .O(\blk00000001/sig000006c5 ) + ); + XORCY \blk00000001/blk000004cf ( + .CI(\blk00000001/sig000006c6 ), + .LI(\blk00000001/sig000006f5 ), + .O(\blk00000001/sig000006de ) + ); + MUXCY \blk00000001/blk000004ce ( + .CI(\blk00000001/sig000006c5 ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig000006f6 ), + .O(\blk00000001/sig000006c4 ) + ); + XORCY \blk00000001/blk000004cd ( + .CI(\blk00000001/sig000006c5 ), + .LI(\blk00000001/sig000006f6 ), + .O(\blk00000001/sig000006df ) + ); + MUXCY \blk00000001/blk000004cc ( + .CI(\blk00000001/sig000006c4 ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig000006f7 ), + .O(\blk00000001/sig000006c3 ) + ); + XORCY \blk00000001/blk000004cb ( + .CI(\blk00000001/sig000006c4 ), + .LI(\blk00000001/sig000006f7 ), + .O(\blk00000001/sig000006e0 ) + ); + MUXCY \blk00000001/blk000004ca ( + .CI(\blk00000001/sig000006c3 ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig000006f8 ), + .O(\blk00000001/sig000006c2 ) + ); + XORCY \blk00000001/blk000004c9 ( + .CI(\blk00000001/sig000006c3 ), + .LI(\blk00000001/sig000006f8 ), + .O(\blk00000001/sig000006e1 ) + ); + MUXCY \blk00000001/blk000004c8 ( + .CI(\blk00000001/sig000006c2 ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig000006f9 ), + .O(\blk00000001/sig000006c1 ) + ); + XORCY \blk00000001/blk000004c7 ( + .CI(\blk00000001/sig000006c2 ), + .LI(\blk00000001/sig000006f9 ), + .O(\blk00000001/sig000006e2 ) + ); + MUXCY \blk00000001/blk000004c6 ( + .CI(\blk00000001/sig000006c1 ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig000006fa ), + .O(\blk00000001/sig000006c0 ) + ); + XORCY \blk00000001/blk000004c5 ( + .CI(\blk00000001/sig000006c1 ), + .LI(\blk00000001/sig000006fa ), + .O(\blk00000001/sig000006e3 ) + ); + MUXCY \blk00000001/blk000004c4 ( + .CI(\blk00000001/sig000006c0 ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig000006fb ), + .O(\blk00000001/sig000006bf ) + ); + XORCY \blk00000001/blk000004c3 ( + .CI(\blk00000001/sig000006c0 ), + .LI(\blk00000001/sig000006fb ), + .O(\blk00000001/sig000006e4 ) + ); + MUXCY \blk00000001/blk000004c2 ( + .CI(\blk00000001/sig000006bf ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig000006fc ), + .O(\blk00000001/sig000006be ) + ); + XORCY \blk00000001/blk000004c1 ( + .CI(\blk00000001/sig000006bf ), + .LI(\blk00000001/sig000006fc ), + .O(\blk00000001/sig000006e5 ) + ); + MUXCY \blk00000001/blk000004c0 ( + .CI(\blk00000001/sig000006be ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig000006fd ), + .O(\blk00000001/sig000006bd ) + ); + XORCY \blk00000001/blk000004bf ( + .CI(\blk00000001/sig000006be ), + .LI(\blk00000001/sig000006fd ), + .O(\blk00000001/sig000006e6 ) + ); + MUXCY \blk00000001/blk000004be ( + .CI(\blk00000001/sig000006bd ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig000006fe ), + .O(\blk00000001/sig000006bc ) + ); + XORCY \blk00000001/blk000004bd ( + .CI(\blk00000001/sig000006bd ), + .LI(\blk00000001/sig000006fe ), + .O(\blk00000001/sig000006e7 ) + ); + MUXCY \blk00000001/blk000004bc ( + .CI(\blk00000001/sig000006bc ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig000006ff ), + .O(\blk00000001/sig000006bb ) + ); + XORCY \blk00000001/blk000004bb ( + .CI(\blk00000001/sig000006bc ), + .LI(\blk00000001/sig000006ff ), + .O(\blk00000001/sig000006e8 ) + ); + XORCY \blk00000001/blk000004ba ( + .CI(\blk00000001/sig000006bb ), + .LI(\blk00000001/sig00000700 ), + .O(\blk00000001/sig000006e9 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk000004b9 ( + .C(aclk), + .D(\blk00000001/sig000001e2 ), + .Q(\blk00000001/sig0000020a ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk000004b8 ( + .C(aclk), + .D(\blk00000001/sig000001e3 ), + .Q(\blk00000001/sig00000059 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk000004b7 ( + .C(aclk), + .D(\blk00000001/sig000001e4 ), + .Q(\blk00000001/sig0000005a ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk000004b6 ( + .C(aclk), + .D(\blk00000001/sig000001e5 ), + .Q(\blk00000001/sig0000005b ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk000004b5 ( + .C(aclk), + .D(\blk00000001/sig000001e6 ), + .Q(\blk00000001/sig0000005c ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk000004b4 ( + .C(aclk), + .D(\blk00000001/sig000001e7 ), + .Q(\blk00000001/sig0000005d ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk000004b3 ( + .C(aclk), + .D(\blk00000001/sig000001e8 ), + .Q(\blk00000001/sig0000005e ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk000004b2 ( + .C(aclk), + .D(\blk00000001/sig000001e9 ), + .Q(\blk00000001/sig0000005f ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk000004b1 ( + .C(aclk), + .D(\blk00000001/sig000001ea ), + .Q(\blk00000001/sig00000060 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk000004b0 ( + .C(aclk), + .D(\blk00000001/sig000001eb ), + .Q(\blk00000001/sig00000061 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk000004af ( + .C(aclk), + .D(\blk00000001/sig000001ec ), + .Q(\blk00000001/sig00000062 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk000004ae ( + .C(aclk), + .D(\blk00000001/sig000001ed ), + .Q(\blk00000001/sig00000063 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk000004ad ( + .C(aclk), + .D(\blk00000001/sig000001ee ), + .Q(\blk00000001/sig00000064 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk000004ac ( + .C(aclk), + .D(\blk00000001/sig000001ef ), + .Q(\blk00000001/sig00000065 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk000004ab ( + .C(aclk), + .D(\blk00000001/sig000001f0 ), + .Q(\blk00000001/sig00000066 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk000004aa ( + .C(aclk), + .D(\blk00000001/sig000001f1 ), + .Q(\blk00000001/sig00000067 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk000004a9 ( + .C(aclk), + .D(\blk00000001/sig000001f2 ), + .Q(\blk00000001/sig00000068 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk000004a8 ( + .C(aclk), + .D(\blk00000001/sig000001f3 ), + .Q(\blk00000001/sig00000069 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk000004a7 ( + .C(aclk), + .D(\blk00000001/sig000001f4 ), + .Q(\blk00000001/sig0000006a ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk000004a6 ( + .C(aclk), + .D(\blk00000001/sig000001f5 ), + .Q(\blk00000001/sig0000006b ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk000004a5 ( + .C(aclk), + .D(\blk00000001/sig000001f6 ), + .Q(\blk00000001/sig0000006c ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk000004a4 ( + .C(aclk), + .D(\blk00000001/sig000001f7 ), + .Q(\blk00000001/sig0000006d ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk000004a3 ( + .C(aclk), + .D(\blk00000001/sig000001f8 ), + .Q(\blk00000001/sig0000006e ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk000004a2 ( + .C(aclk), + .D(\blk00000001/sig000001f9 ), + .Q(\blk00000001/sig0000006f ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk000004a1 ( + .C(aclk), + .D(\blk00000001/sig000001fa ), + .Q(\blk00000001/sig00000070 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk000004a0 ( + .C(aclk), + .D(\blk00000001/sig000001fb ), + .Q(\blk00000001/sig00000071 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk0000049f ( + .C(aclk), + .D(\blk00000001/sig000001fc ), + .Q(\blk00000001/sig00000072 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk0000049e ( + .C(aclk), + .D(\blk00000001/sig000001fd ), + .Q(\blk00000001/sig00000073 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk0000049d ( + .C(aclk), + .D(\blk00000001/sig000001fe ), + .Q(\blk00000001/sig00000074 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk0000049c ( + .C(aclk), + .D(\blk00000001/sig000001ff ), + .Q(\blk00000001/sig00000075 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk0000049b ( + .C(aclk), + .D(\blk00000001/sig00000200 ), + .Q(\blk00000001/sig00000076 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk0000049a ( + .C(aclk), + .D(\blk00000001/sig00000201 ), + .Q(\blk00000001/sig00000077 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000499 ( + .C(aclk), + .D(\blk00000001/sig00000202 ), + .Q(\blk00000001/sig00000078 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000498 ( + .C(aclk), + .D(\blk00000001/sig00000203 ), + .Q(\blk00000001/sig00000079 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000497 ( + .C(aclk), + .D(\blk00000001/sig00000204 ), + .Q(\blk00000001/sig0000007a ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000496 ( + .C(aclk), + .D(\blk00000001/sig00000205 ), + .Q(\blk00000001/sig0000007b ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000495 ( + .C(aclk), + .D(\blk00000001/sig00000206 ), + .Q(\blk00000001/sig0000007c ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000494 ( + .C(aclk), + .D(\blk00000001/sig00000207 ), + .Q(\blk00000001/sig0000007d ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000493 ( + .C(aclk), + .D(\blk00000001/sig00000208 ), + .Q(\blk00000001/sig0000007e ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000492 ( + .C(aclk), + .D(\blk00000001/sig00000209 ), + .Q(\blk00000001/sig0000007f ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000491 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000025a ), + .Q(\blk00000001/sig0000020b ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000490 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000235 ), + .Q(\blk00000001/sig0000020c ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000048f ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000234 ), + .Q(\blk00000001/sig0000020d ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000048e ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000233 ), + .Q(\blk00000001/sig0000020e ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000048d ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000236 ), + .Q(\blk00000001/sig0000020f ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000048c ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000237 ), + .Q(\blk00000001/sig00000210 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000048b ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000238 ), + .Q(\blk00000001/sig00000211 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000048a ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000239 ), + .Q(\blk00000001/sig00000212 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000489 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000023a ), + .Q(\blk00000001/sig00000213 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000488 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000023b ), + .Q(\blk00000001/sig00000214 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000487 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000023c ), + .Q(\blk00000001/sig00000215 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000486 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000023d ), + .Q(\blk00000001/sig00000216 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000485 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000023e ), + .Q(\blk00000001/sig00000217 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000484 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000023f ), + .Q(\blk00000001/sig00000218 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000483 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000240 ), + .Q(\blk00000001/sig00000219 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000482 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000241 ), + .Q(\blk00000001/sig0000021a ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000481 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000242 ), + .Q(\blk00000001/sig0000021b ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000480 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000243 ), + .Q(\blk00000001/sig0000021c ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000047f ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000244 ), + .Q(\blk00000001/sig0000021d ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000047e ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000245 ), + .Q(\blk00000001/sig0000021e ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000047d ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000246 ), + .Q(\blk00000001/sig0000021f ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000047c ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000247 ), + .Q(\blk00000001/sig00000220 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000047b ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000248 ), + .Q(\blk00000001/sig00000221 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000047a ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000249 ), + .Q(\blk00000001/sig00000222 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000479 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000024a ), + .Q(\blk00000001/sig00000223 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000478 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000024b ), + .Q(\blk00000001/sig00000224 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000477 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000024c ), + .Q(\blk00000001/sig00000225 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000476 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000024d ), + .Q(\blk00000001/sig00000226 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000475 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000024e ), + .Q(\blk00000001/sig00000227 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000474 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000024f ), + .Q(\blk00000001/sig00000228 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000473 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000250 ), + .Q(\blk00000001/sig00000229 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000472 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000251 ), + .Q(\blk00000001/sig0000022a ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000471 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000252 ), + .Q(\blk00000001/sig0000022b ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000470 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000253 ), + .Q(\blk00000001/sig0000022c ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000046f ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000254 ), + .Q(\blk00000001/sig0000022d ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000046e ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000255 ), + .Q(\blk00000001/sig0000022e ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000046d ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000256 ), + .Q(\blk00000001/sig0000022f ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000046c ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000257 ), + .Q(\blk00000001/sig00000230 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000046b ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000258 ), + .Q(\blk00000001/sig00000231 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000046a ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000259 ), + .Q(\blk00000001/sig00000232 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000469 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000002b0 ), + .Q(\blk00000001/sig00000236 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000468 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000028f ), + .Q(\blk00000001/sig00000237 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000467 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000028e ), + .Q(\blk00000001/sig00000238 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000466 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000028d ), + .Q(\blk00000001/sig00000239 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000465 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000290 ), + .Q(\blk00000001/sig0000023a ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000464 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000291 ), + .Q(\blk00000001/sig0000023b ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000463 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000292 ), + .Q(\blk00000001/sig0000023c ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000462 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000293 ), + .Q(\blk00000001/sig0000023d ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000461 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000294 ), + .Q(\blk00000001/sig0000023e ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000460 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000295 ), + .Q(\blk00000001/sig0000023f ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000045f ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000296 ), + .Q(\blk00000001/sig00000240 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000045e ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000297 ), + .Q(\blk00000001/sig00000241 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000045d ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000298 ), + .Q(\blk00000001/sig00000242 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000045c ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000299 ), + .Q(\blk00000001/sig00000243 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000045b ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000029a ), + .Q(\blk00000001/sig00000244 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000045a ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000029b ), + .Q(\blk00000001/sig00000245 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000459 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000029c ), + .Q(\blk00000001/sig00000246 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000458 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000029d ), + .Q(\blk00000001/sig00000247 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000457 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000029e ), + .Q(\blk00000001/sig00000248 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000456 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000029f ), + .Q(\blk00000001/sig00000249 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000455 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000002a0 ), + .Q(\blk00000001/sig0000024a ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000454 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000002a1 ), + .Q(\blk00000001/sig0000024b ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000453 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000002a2 ), + .Q(\blk00000001/sig0000024c ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000452 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000002a3 ), + .Q(\blk00000001/sig0000024d ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000451 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000002a4 ), + .Q(\blk00000001/sig0000024e ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000450 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000002a5 ), + .Q(\blk00000001/sig0000024f ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000044f ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000002a6 ), + .Q(\blk00000001/sig00000250 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000044e ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000002a7 ), + .Q(\blk00000001/sig00000251 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000044d ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000002a8 ), + .Q(\blk00000001/sig00000252 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000044c ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000002a9 ), + .Q(\blk00000001/sig00000253 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000044b ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000002aa ), + .Q(\blk00000001/sig00000254 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000044a ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000002ab ), + .Q(\blk00000001/sig00000255 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000449 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000002ac ), + .Q(\blk00000001/sig00000256 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000448 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000002ad ), + .Q(\blk00000001/sig00000257 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000447 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000002ae ), + .Q(\blk00000001/sig00000258 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000446 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000002af ), + .Q(\blk00000001/sig00000259 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000445 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000302 ), + .Q(\blk00000001/sig00000290 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000444 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000002e5 ), + .Q(\blk00000001/sig00000291 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000443 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000002e4 ), + .Q(\blk00000001/sig00000292 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000442 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000002e3 ), + .Q(\blk00000001/sig00000293 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000441 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000002e6 ), + .Q(\blk00000001/sig00000294 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000440 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000002e7 ), + .Q(\blk00000001/sig00000295 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000043f ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000002e8 ), + .Q(\blk00000001/sig00000296 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000043e ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000002e9 ), + .Q(\blk00000001/sig00000297 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000043d ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000002ea ), + .Q(\blk00000001/sig00000298 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000043c ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000002eb ), + .Q(\blk00000001/sig00000299 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000043b ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000002ec ), + .Q(\blk00000001/sig0000029a ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000043a ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000002ed ), + .Q(\blk00000001/sig0000029b ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000439 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000002ee ), + .Q(\blk00000001/sig0000029c ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000438 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000002ef ), + .Q(\blk00000001/sig0000029d ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000437 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000002f0 ), + .Q(\blk00000001/sig0000029e ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000436 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000002f1 ), + .Q(\blk00000001/sig0000029f ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000435 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000002f2 ), + .Q(\blk00000001/sig000002a0 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000434 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000002f3 ), + .Q(\blk00000001/sig000002a1 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000433 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000002f4 ), + .Q(\blk00000001/sig000002a2 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000432 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000002f5 ), + .Q(\blk00000001/sig000002a3 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000431 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000002f6 ), + .Q(\blk00000001/sig000002a4 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000430 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000002f7 ), + .Q(\blk00000001/sig000002a5 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000042f ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000002f8 ), + .Q(\blk00000001/sig000002a6 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000042e ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000002f9 ), + .Q(\blk00000001/sig000002a7 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000042d ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000002fa ), + .Q(\blk00000001/sig000002a8 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000042c ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000002fb ), + .Q(\blk00000001/sig000002a9 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000042b ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000002fc ), + .Q(\blk00000001/sig000002aa ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000042a ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000002fd ), + .Q(\blk00000001/sig000002ab ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000429 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000002fe ), + .Q(\blk00000001/sig000002ac ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000428 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000002ff ), + .Q(\blk00000001/sig000002ad ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000427 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000300 ), + .Q(\blk00000001/sig000002ae ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000426 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000301 ), + .Q(\blk00000001/sig000002af ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000425 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000350 ), + .Q(\blk00000001/sig000002e6 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000424 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000337 ), + .Q(\blk00000001/sig000002e7 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000423 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000336 ), + .Q(\blk00000001/sig000002e8 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000422 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000335 ), + .Q(\blk00000001/sig000002e9 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000421 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000338 ), + .Q(\blk00000001/sig000002ea ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000420 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000339 ), + .Q(\blk00000001/sig000002eb ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000041f ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000033a ), + .Q(\blk00000001/sig000002ec ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000041e ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000033b ), + .Q(\blk00000001/sig000002ed ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000041d ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000033c ), + .Q(\blk00000001/sig000002ee ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000041c ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000033d ), + .Q(\blk00000001/sig000002ef ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000041b ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000033e ), + .Q(\blk00000001/sig000002f0 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000041a ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000033f ), + .Q(\blk00000001/sig000002f1 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000419 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000340 ), + .Q(\blk00000001/sig000002f2 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000418 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000341 ), + .Q(\blk00000001/sig000002f3 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000417 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000342 ), + .Q(\blk00000001/sig000002f4 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000416 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000343 ), + .Q(\blk00000001/sig000002f5 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000415 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000344 ), + .Q(\blk00000001/sig000002f6 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000414 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000345 ), + .Q(\blk00000001/sig000002f7 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000413 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000346 ), + .Q(\blk00000001/sig000002f8 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000412 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000347 ), + .Q(\blk00000001/sig000002f9 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000411 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000348 ), + .Q(\blk00000001/sig000002fa ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000410 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000349 ), + .Q(\blk00000001/sig000002fb ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000040f ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000034a ), + .Q(\blk00000001/sig000002fc ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000040e ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000034b ), + .Q(\blk00000001/sig000002fd ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000040d ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000034c ), + .Q(\blk00000001/sig000002fe ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000040c ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000034d ), + .Q(\blk00000001/sig000002ff ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000040b ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000034e ), + .Q(\blk00000001/sig00000300 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000040a ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000034f ), + .Q(\blk00000001/sig00000301 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000409 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000039b ), + .Q(\blk00000001/sig00000338 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000408 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000386 ), + .Q(\blk00000001/sig00000339 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000407 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000385 ), + .Q(\blk00000001/sig0000033a ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000406 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000384 ), + .Q(\blk00000001/sig0000033b ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000405 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000387 ), + .Q(\blk00000001/sig0000033c ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000404 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000388 ), + .Q(\blk00000001/sig0000033d ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000403 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000389 ), + .Q(\blk00000001/sig0000033e ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000402 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000038a ), + .Q(\blk00000001/sig0000033f ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000401 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000038b ), + .Q(\blk00000001/sig00000340 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000400 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000038c ), + .Q(\blk00000001/sig00000341 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk000003ff ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000038d ), + .Q(\blk00000001/sig00000342 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk000003fe ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000038e ), + .Q(\blk00000001/sig00000343 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk000003fd ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000038f ), + .Q(\blk00000001/sig00000344 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk000003fc ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000390 ), + .Q(\blk00000001/sig00000345 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk000003fb ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000391 ), + .Q(\blk00000001/sig00000346 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk000003fa ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000392 ), + .Q(\blk00000001/sig00000347 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk000003f9 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000393 ), + .Q(\blk00000001/sig00000348 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk000003f8 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000394 ), + .Q(\blk00000001/sig00000349 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk000003f7 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000395 ), + .Q(\blk00000001/sig0000034a ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk000003f6 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000396 ), + .Q(\blk00000001/sig0000034b ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk000003f5 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000397 ), + .Q(\blk00000001/sig0000034c ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk000003f4 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000398 ), + .Q(\blk00000001/sig0000034d ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk000003f3 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000399 ), + .Q(\blk00000001/sig0000034e ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk000003f2 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000039a ), + .Q(\blk00000001/sig0000034f ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk000003f1 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000003e6 ), + .Q(\blk00000001/sig00000387 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk000003f0 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000003d5 ), + .Q(\blk00000001/sig00000388 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk000003ef ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000003d4 ), + .Q(\blk00000001/sig00000389 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk000003ee ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000003d3 ), + .Q(\blk00000001/sig0000038a ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk000003ed ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000003d6 ), + .Q(\blk00000001/sig0000038b ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk000003ec ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000003d7 ), + .Q(\blk00000001/sig0000038c ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk000003eb ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000003d8 ), + .Q(\blk00000001/sig0000038d ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk000003ea ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000003d9 ), + .Q(\blk00000001/sig0000038e ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk000003e9 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000003da ), + .Q(\blk00000001/sig0000038f ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk000003e8 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000003db ), + .Q(\blk00000001/sig00000390 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk000003e7 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000003dc ), + .Q(\blk00000001/sig00000391 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk000003e6 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000003dd ), + .Q(\blk00000001/sig00000392 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk000003e5 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000003de ), + .Q(\blk00000001/sig00000393 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk000003e4 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000003df ), + .Q(\blk00000001/sig00000394 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk000003e3 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000003e0 ), + .Q(\blk00000001/sig00000395 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk000003e2 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000003e1 ), + .Q(\blk00000001/sig00000396 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk000003e1 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000003e2 ), + .Q(\blk00000001/sig00000397 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk000003e0 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000003e3 ), + .Q(\blk00000001/sig00000398 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk000003df ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000003e4 ), + .Q(\blk00000001/sig00000399 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk000003de ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000003e5 ), + .Q(\blk00000001/sig0000039a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000003dd ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig0000041a ), + .Q(\blk00000001/sig000003cf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000003dc ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig0000041b ), + .Q(\blk00000001/sig000003d0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000003db ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig0000041c ), + .Q(\blk00000001/sig000003d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000003da ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig0000041d ), + .Q(\blk00000001/sig000003d2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000003d9 ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig00000465 ), + .Q(\blk00000001/sig0000041a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000003d8 ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig00000466 ), + .Q(\blk00000001/sig0000041b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000003d7 ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig00000467 ), + .Q(\blk00000001/sig0000041c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000003d6 ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig00000468 ), + .Q(\blk00000001/sig0000041d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000003d5 ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig00000469 ), + .Q(\blk00000001/sig0000041e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000003d4 ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig0000046a ), + .Q(\blk00000001/sig0000041f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000003d3 ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig0000046b ), + .Q(\blk00000001/sig00000420 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000003d2 ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig0000046c ), + .Q(\blk00000001/sig00000421 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk000003d1 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000047c ), + .Q(\blk00000001/sig00000425 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk000003d0 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000473 ), + .Q(\blk00000001/sig00000426 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk000003cf ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000472 ), + .Q(\blk00000001/sig00000427 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk000003ce ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000471 ), + .Q(\blk00000001/sig00000428 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk000003cd ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000474 ), + .Q(\blk00000001/sig00000429 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk000003cc ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000475 ), + .Q(\blk00000001/sig0000042a ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk000003cb ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000476 ), + .Q(\blk00000001/sig0000042b ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk000003ca ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000477 ), + .Q(\blk00000001/sig0000042c ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk000003c9 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000478 ), + .Q(\blk00000001/sig0000042d ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk000003c8 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000479 ), + .Q(\blk00000001/sig0000042e ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk000003c7 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000047a ), + .Q(\blk00000001/sig0000042f ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk000003c6 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000047b ), + .Q(\blk00000001/sig00000430 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000003c5 ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig000004b0 ), + .Q(\blk00000001/sig00000465 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000003c4 ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig000004b1 ), + .Q(\blk00000001/sig00000466 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000003c3 ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig000004b2 ), + .Q(\blk00000001/sig00000467 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000003c2 ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig000004b3 ), + .Q(\blk00000001/sig00000468 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000003c1 ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig000004b4 ), + .Q(\blk00000001/sig00000469 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000003c0 ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig000004b5 ), + .Q(\blk00000001/sig0000046a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000003bf ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig000004b6 ), + .Q(\blk00000001/sig0000046b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000003be ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig000004b7 ), + .Q(\blk00000001/sig0000046c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000003bd ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig000004b8 ), + .Q(\blk00000001/sig0000046d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000003bc ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig000004b9 ), + .Q(\blk00000001/sig0000046e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000003bb ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig000004ba ), + .Q(\blk00000001/sig0000046f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000003ba ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig000004bb ), + .Q(\blk00000001/sig00000470 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk000003b9 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000004c7 ), + .Q(\blk00000001/sig00000474 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk000003b8 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000004c2 ), + .Q(\blk00000001/sig00000475 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk000003b7 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000004c1 ), + .Q(\blk00000001/sig00000476 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk000003b6 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000004c0 ), + .Q(\blk00000001/sig00000477 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk000003b5 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000004c3 ), + .Q(\blk00000001/sig00000478 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk000003b4 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000004c4 ), + .Q(\blk00000001/sig00000479 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk000003b3 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000004c5 ), + .Q(\blk00000001/sig0000047a ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk000003b2 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000004c6 ), + .Q(\blk00000001/sig0000047b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000003b1 ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig000004fb ), + .Q(\blk00000001/sig000004b0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000003b0 ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig000004fc ), + .Q(\blk00000001/sig000004b1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000003af ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig000004fd ), + .Q(\blk00000001/sig000004b2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000003ae ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig000004fe ), + .Q(\blk00000001/sig000004b3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000003ad ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig000004ff ), + .Q(\blk00000001/sig000004b4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000003ac ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig00000500 ), + .Q(\blk00000001/sig000004b5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000003ab ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig00000501 ), + .Q(\blk00000001/sig000004b6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000003aa ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig00000502 ), + .Q(\blk00000001/sig000004b7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000003a9 ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig00000503 ), + .Q(\blk00000001/sig000004b8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000003a8 ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig00000504 ), + .Q(\blk00000001/sig000004b9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000003a7 ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig00000505 ), + .Q(\blk00000001/sig000004ba ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000003a6 ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig00000506 ), + .Q(\blk00000001/sig000004bb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000003a5 ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig00000507 ), + .Q(\blk00000001/sig000004bc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000003a4 ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig00000508 ), + .Q(\blk00000001/sig000004bd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000003a3 ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig00000509 ), + .Q(\blk00000001/sig000004be ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000003a2 ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig0000050a ), + .Q(\blk00000001/sig000004bf ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk000003a1 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000512 ), + .Q(\blk00000001/sig000004c3 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk000003a0 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000511 ), + .Q(\blk00000001/sig000004c4 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000039f ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000510 ), + .Q(\blk00000001/sig000004c5 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000039e ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000050f ), + .Q(\blk00000001/sig000004c6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk0000039d ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig00000546 ), + .Q(\blk00000001/sig000004fb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk0000039c ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig00000547 ), + .Q(\blk00000001/sig000004fc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk0000039b ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig00000548 ), + .Q(\blk00000001/sig000004fd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk0000039a ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig00000549 ), + .Q(\blk00000001/sig000004fe ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk00000399 ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig0000054a ), + .Q(\blk00000001/sig000004ff ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk00000398 ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig0000054b ), + .Q(\blk00000001/sig00000500 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk00000397 ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig0000054c ), + .Q(\blk00000001/sig00000501 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk00000396 ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig0000054d ), + .Q(\blk00000001/sig00000502 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk00000395 ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig0000054e ), + .Q(\blk00000001/sig00000503 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk00000394 ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig0000054f ), + .Q(\blk00000001/sig00000504 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk00000393 ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig00000550 ), + .Q(\blk00000001/sig00000505 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk00000392 ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig00000551 ), + .Q(\blk00000001/sig00000506 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk00000391 ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig00000552 ), + .Q(\blk00000001/sig00000507 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk00000390 ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig00000553 ), + .Q(\blk00000001/sig00000508 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk0000038f ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig00000554 ), + .Q(\blk00000001/sig00000509 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk0000038e ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig00000555 ), + .Q(\blk00000001/sig0000050a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk0000038d ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig00000556 ), + .Q(\blk00000001/sig0000050b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk0000038c ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig00000557 ), + .Q(\blk00000001/sig0000050c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk0000038b ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig00000558 ), + .Q(\blk00000001/sig0000050d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk0000038a ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig00000559 ), + .Q(\blk00000001/sig0000050e ) + ); + FD #( + .INIT ( 1'b1 )) + \blk00000001/blk00000389 ( + .C(aclk), + .D(\blk00000001/sig00000512 ), + .Q(\blk00000001/sig00000511 ) + ); + FD #( + .INIT ( 1'b1 )) + \blk00000001/blk00000388 ( + .C(aclk), + .D(\blk00000001/sig00000511 ), + .Q(\blk00000001/sig00000510 ) + ); + FD #( + .INIT ( 1'b1 )) + \blk00000001/blk00000387 ( + .C(aclk), + .D(\blk00000001/sig00000510 ), + .Q(\blk00000001/sig0000050f ) + ); + FD #( + .INIT ( 1'b1 )) + \blk00000001/blk00000386 ( + .C(aclk), + .D(\blk00000001/sig000004c7 ), + .Q(\blk00000001/sig000004c2 ) + ); + FD #( + .INIT ( 1'b1 )) + \blk00000001/blk00000385 ( + .C(aclk), + .D(\blk00000001/sig000004c2 ), + .Q(\blk00000001/sig000004c1 ) + ); + FD #( + .INIT ( 1'b1 )) + \blk00000001/blk00000384 ( + .C(aclk), + .D(\blk00000001/sig000004c1 ), + .Q(\blk00000001/sig000004c0 ) + ); + FD #( + .INIT ( 1'b1 )) + \blk00000001/blk00000383 ( + .C(aclk), + .D(\blk00000001/sig0000047c ), + .Q(\blk00000001/sig00000473 ) + ); + FD #( + .INIT ( 1'b1 )) + \blk00000001/blk00000382 ( + .C(aclk), + .D(\blk00000001/sig00000473 ), + .Q(\blk00000001/sig00000472 ) + ); + FD #( + .INIT ( 1'b1 )) + \blk00000001/blk00000381 ( + .C(aclk), + .D(\blk00000001/sig00000472 ), + .Q(\blk00000001/sig00000471 ) + ); + FD #( + .INIT ( 1'b1 )) + \blk00000001/blk00000380 ( + .C(aclk), + .D(\blk00000001/sig00000431 ), + .Q(\blk00000001/sig00000424 ) + ); + FD #( + .INIT ( 1'b1 )) + \blk00000001/blk0000037f ( + .C(aclk), + .D(\blk00000001/sig00000424 ), + .Q(\blk00000001/sig00000423 ) + ); + FD #( + .INIT ( 1'b1 )) + \blk00000001/blk0000037e ( + .C(aclk), + .D(\blk00000001/sig00000423 ), + .Q(\blk00000001/sig00000422 ) + ); + FD #( + .INIT ( 1'b1 )) + \blk00000001/blk0000037d ( + .C(aclk), + .D(\blk00000001/sig000003e6 ), + .Q(\blk00000001/sig000003d5 ) + ); + FD #( + .INIT ( 1'b1 )) + \blk00000001/blk0000037c ( + .C(aclk), + .D(\blk00000001/sig000003d5 ), + .Q(\blk00000001/sig000003d4 ) + ); + FD #( + .INIT ( 1'b1 )) + \blk00000001/blk0000037b ( + .C(aclk), + .D(\blk00000001/sig000003d4 ), + .Q(\blk00000001/sig000003d3 ) + ); + FD #( + .INIT ( 1'b1 )) + \blk00000001/blk0000037a ( + .C(aclk), + .D(\blk00000001/sig0000039b ), + .Q(\blk00000001/sig00000386 ) + ); + FD #( + .INIT ( 1'b1 )) + \blk00000001/blk00000379 ( + .C(aclk), + .D(\blk00000001/sig00000386 ), + .Q(\blk00000001/sig00000385 ) + ); + FD #( + .INIT ( 1'b1 )) + \blk00000001/blk00000378 ( + .C(aclk), + .D(\blk00000001/sig00000385 ), + .Q(\blk00000001/sig00000384 ) + ); + FD #( + .INIT ( 1'b1 )) + \blk00000001/blk00000377 ( + .C(aclk), + .D(\blk00000001/sig00000350 ), + .Q(\blk00000001/sig00000337 ) + ); + FD #( + .INIT ( 1'b1 )) + \blk00000001/blk00000376 ( + .C(aclk), + .D(\blk00000001/sig00000337 ), + .Q(\blk00000001/sig00000336 ) + ); + FD #( + .INIT ( 1'b1 )) + \blk00000001/blk00000375 ( + .C(aclk), + .D(\blk00000001/sig00000336 ), + .Q(\blk00000001/sig00000335 ) + ); + FD #( + .INIT ( 1'b1 )) + \blk00000001/blk00000374 ( + .C(aclk), + .D(\blk00000001/sig00000302 ), + .Q(\blk00000001/sig000002e5 ) + ); + FD #( + .INIT ( 1'b1 )) + \blk00000001/blk00000373 ( + .C(aclk), + .D(\blk00000001/sig000002e5 ), + .Q(\blk00000001/sig000002e4 ) + ); + FD #( + .INIT ( 1'b1 )) + \blk00000001/blk00000372 ( + .C(aclk), + .D(\blk00000001/sig000002e4 ), + .Q(\blk00000001/sig000002e3 ) + ); + FD #( + .INIT ( 1'b1 )) + \blk00000001/blk00000371 ( + .C(aclk), + .D(\blk00000001/sig000002b0 ), + .Q(\blk00000001/sig0000028f ) + ); + FD #( + .INIT ( 1'b1 )) + \blk00000001/blk00000370 ( + .C(aclk), + .D(\blk00000001/sig0000028f ), + .Q(\blk00000001/sig0000028e ) + ); + FD #( + .INIT ( 1'b1 )) + \blk00000001/blk0000036f ( + .C(aclk), + .D(\blk00000001/sig0000028e ), + .Q(\blk00000001/sig0000028d ) + ); + FD #( + .INIT ( 1'b1 )) + \blk00000001/blk0000036e ( + .C(aclk), + .D(\blk00000001/sig0000025a ), + .Q(\blk00000001/sig00000235 ) + ); + FD #( + .INIT ( 1'b1 )) + \blk00000001/blk0000036d ( + .C(aclk), + .D(\blk00000001/sig00000235 ), + .Q(\blk00000001/sig00000234 ) + ); + FD #( + .INIT ( 1'b1 )) + \blk00000001/blk0000036c ( + .C(aclk), + .D(\blk00000001/sig00000234 ), + .Q(\blk00000001/sig00000233 ) + ); + MUXCY \blk00000001/blk0000036b ( + .CI(\blk00000001/sig0000026b ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig000006aa ), + .O(\blk00000001/sig000006ba ) + ); + XORCY \blk00000001/blk0000036a ( + .CI(\blk00000001/sig0000026b ), + .LI(\blk00000001/sig000006aa ), + .O(\blk00000001/sig0000025b ) + ); + MUXCY \blk00000001/blk00000369 ( + .CI(\blk00000001/sig000006ab ), + .DI(\blk00000001/sig0000027c ), + .S(\blk00000001/sig000006a9 ), + .O(\NLW_blk00000001/blk00000369_O_UNCONNECTED ) + ); + MUXCY \blk00000001/blk00000368 ( + .CI(\blk00000001/sig000006ba ), + .DI(\blk00000001/sig0000026d ), + .S(\blk00000001/sig000006a8 ), + .O(\blk00000001/sig000006b9 ) + ); + MUXCY \blk00000001/blk00000367 ( + .CI(\blk00000001/sig000006b9 ), + .DI(\blk00000001/sig0000026e ), + .S(\blk00000001/sig000006a7 ), + .O(\blk00000001/sig000006b8 ) + ); + MUXCY \blk00000001/blk00000366 ( + .CI(\blk00000001/sig000006b8 ), + .DI(\blk00000001/sig0000026f ), + .S(\blk00000001/sig000006a6 ), + .O(\blk00000001/sig000006b7 ) + ); + MUXCY \blk00000001/blk00000365 ( + .CI(\blk00000001/sig000006b7 ), + .DI(\blk00000001/sig00000270 ), + .S(\blk00000001/sig000006a5 ), + .O(\blk00000001/sig000006b6 ) + ); + MUXCY \blk00000001/blk00000364 ( + .CI(\blk00000001/sig000006b6 ), + .DI(\blk00000001/sig00000271 ), + .S(\blk00000001/sig000006a4 ), + .O(\blk00000001/sig000006b5 ) + ); + MUXCY \blk00000001/blk00000363 ( + .CI(\blk00000001/sig000006b5 ), + .DI(\blk00000001/sig00000272 ), + .S(\blk00000001/sig000006a3 ), + .O(\blk00000001/sig000006b4 ) + ); + MUXCY \blk00000001/blk00000362 ( + .CI(\blk00000001/sig000006b4 ), + .DI(\blk00000001/sig00000273 ), + .S(\blk00000001/sig000006a2 ), + .O(\blk00000001/sig000006b3 ) + ); + MUXCY \blk00000001/blk00000361 ( + .CI(\blk00000001/sig000006b3 ), + .DI(\blk00000001/sig00000274 ), + .S(\blk00000001/sig000006a1 ), + .O(\blk00000001/sig000006b2 ) + ); + MUXCY \blk00000001/blk00000360 ( + .CI(\blk00000001/sig000006b2 ), + .DI(\blk00000001/sig00000275 ), + .S(\blk00000001/sig000006a0 ), + .O(\blk00000001/sig000006b1 ) + ); + MUXCY \blk00000001/blk0000035f ( + .CI(\blk00000001/sig000006b1 ), + .DI(\blk00000001/sig00000276 ), + .S(\blk00000001/sig0000069f ), + .O(\blk00000001/sig000006b0 ) + ); + MUXCY \blk00000001/blk0000035e ( + .CI(\blk00000001/sig000006b0 ), + .DI(\blk00000001/sig00000277 ), + .S(\blk00000001/sig0000069e ), + .O(\blk00000001/sig000006af ) + ); + MUXCY \blk00000001/blk0000035d ( + .CI(\blk00000001/sig000006af ), + .DI(\blk00000001/sig00000278 ), + .S(\blk00000001/sig0000069d ), + .O(\blk00000001/sig000006ae ) + ); + MUXCY \blk00000001/blk0000035c ( + .CI(\blk00000001/sig000006ae ), + .DI(\blk00000001/sig00000279 ), + .S(\blk00000001/sig0000069c ), + .O(\blk00000001/sig000006ad ) + ); + MUXCY \blk00000001/blk0000035b ( + .CI(\blk00000001/sig000006ad ), + .DI(\blk00000001/sig0000027a ), + .S(\blk00000001/sig0000069b ), + .O(\blk00000001/sig000006ac ) + ); + MUXCY \blk00000001/blk0000035a ( + .CI(\blk00000001/sig000006ac ), + .DI(\blk00000001/sig0000027b ), + .S(\blk00000001/sig0000069a ), + .O(\blk00000001/sig000006ab ) + ); + XORCY \blk00000001/blk00000359 ( + .CI(\blk00000001/sig000006ba ), + .LI(\blk00000001/sig000006a8 ), + .O(\blk00000001/sig0000025c ) + ); + XORCY \blk00000001/blk00000358 ( + .CI(\blk00000001/sig000006b9 ), + .LI(\blk00000001/sig000006a7 ), + .O(\blk00000001/sig0000025d ) + ); + XORCY \blk00000001/blk00000357 ( + .CI(\blk00000001/sig000006b8 ), + .LI(\blk00000001/sig000006a6 ), + .O(\blk00000001/sig0000025e ) + ); + XORCY \blk00000001/blk00000356 ( + .CI(\blk00000001/sig000006b7 ), + .LI(\blk00000001/sig000006a5 ), + .O(\blk00000001/sig0000025f ) + ); + XORCY \blk00000001/blk00000355 ( + .CI(\blk00000001/sig000006b6 ), + .LI(\blk00000001/sig000006a4 ), + .O(\blk00000001/sig00000260 ) + ); + XORCY \blk00000001/blk00000354 ( + .CI(\blk00000001/sig000006b5 ), + .LI(\blk00000001/sig000006a3 ), + .O(\blk00000001/sig00000261 ) + ); + XORCY \blk00000001/blk00000353 ( + .CI(\blk00000001/sig000006b4 ), + .LI(\blk00000001/sig000006a2 ), + .O(\blk00000001/sig00000262 ) + ); + XORCY \blk00000001/blk00000352 ( + .CI(\blk00000001/sig000006b3 ), + .LI(\blk00000001/sig000006a1 ), + .O(\blk00000001/sig00000263 ) + ); + XORCY \blk00000001/blk00000351 ( + .CI(\blk00000001/sig000006b2 ), + .LI(\blk00000001/sig000006a0 ), + .O(\blk00000001/sig00000264 ) + ); + XORCY \blk00000001/blk00000350 ( + .CI(\blk00000001/sig000006b1 ), + .LI(\blk00000001/sig0000069f ), + .O(\blk00000001/sig00000265 ) + ); + XORCY \blk00000001/blk0000034f ( + .CI(\blk00000001/sig000006b0 ), + .LI(\blk00000001/sig0000069e ), + .O(\blk00000001/sig00000266 ) + ); + XORCY \blk00000001/blk0000034e ( + .CI(\blk00000001/sig000006af ), + .LI(\blk00000001/sig0000069d ), + .O(\blk00000001/sig00000267 ) + ); + XORCY \blk00000001/blk0000034d ( + .CI(\blk00000001/sig000006ae ), + .LI(\blk00000001/sig0000069c ), + .O(\blk00000001/sig00000268 ) + ); + XORCY \blk00000001/blk0000034c ( + .CI(\blk00000001/sig000006ad ), + .LI(\blk00000001/sig0000069b ), + .O(\blk00000001/sig00000269 ) + ); + XORCY \blk00000001/blk0000034b ( + .CI(\blk00000001/sig000006ac ), + .LI(\blk00000001/sig0000069a ), + .O(\blk00000001/sig0000026a ) + ); + XORCY \blk00000001/blk0000034a ( + .CI(\blk00000001/sig000006ab ), + .LI(\blk00000001/sig000006a9 ), + .O(\blk00000001/sig0000025a ) + ); + MUXCY \blk00000001/blk00000349 ( + .CI(\blk00000001/sig000002c1 ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig00000689 ), + .O(\blk00000001/sig00000699 ) + ); + XORCY \blk00000001/blk00000348 ( + .CI(\blk00000001/sig000002c1 ), + .LI(\blk00000001/sig00000689 ), + .O(\blk00000001/sig000002b1 ) + ); + MUXCY \blk00000001/blk00000347 ( + .CI(\blk00000001/sig0000068a ), + .DI(\blk00000001/sig000002d2 ), + .S(\blk00000001/sig00000688 ), + .O(\NLW_blk00000001/blk00000347_O_UNCONNECTED ) + ); + MUXCY \blk00000001/blk00000346 ( + .CI(\blk00000001/sig00000699 ), + .DI(\blk00000001/sig000002c3 ), + .S(\blk00000001/sig00000687 ), + .O(\blk00000001/sig00000698 ) + ); + MUXCY \blk00000001/blk00000345 ( + .CI(\blk00000001/sig00000698 ), + .DI(\blk00000001/sig000002c4 ), + .S(\blk00000001/sig00000686 ), + .O(\blk00000001/sig00000697 ) + ); + MUXCY \blk00000001/blk00000344 ( + .CI(\blk00000001/sig00000697 ), + .DI(\blk00000001/sig000002c5 ), + .S(\blk00000001/sig00000685 ), + .O(\blk00000001/sig00000696 ) + ); + MUXCY \blk00000001/blk00000343 ( + .CI(\blk00000001/sig00000696 ), + .DI(\blk00000001/sig000002c6 ), + .S(\blk00000001/sig00000684 ), + .O(\blk00000001/sig00000695 ) + ); + MUXCY \blk00000001/blk00000342 ( + .CI(\blk00000001/sig00000695 ), + .DI(\blk00000001/sig000002c7 ), + .S(\blk00000001/sig00000683 ), + .O(\blk00000001/sig00000694 ) + ); + MUXCY \blk00000001/blk00000341 ( + .CI(\blk00000001/sig00000694 ), + .DI(\blk00000001/sig000002c8 ), + .S(\blk00000001/sig00000682 ), + .O(\blk00000001/sig00000693 ) + ); + MUXCY \blk00000001/blk00000340 ( + .CI(\blk00000001/sig00000693 ), + .DI(\blk00000001/sig000002c9 ), + .S(\blk00000001/sig00000681 ), + .O(\blk00000001/sig00000692 ) + ); + MUXCY \blk00000001/blk0000033f ( + .CI(\blk00000001/sig00000692 ), + .DI(\blk00000001/sig000002ca ), + .S(\blk00000001/sig00000680 ), + .O(\blk00000001/sig00000691 ) + ); + MUXCY \blk00000001/blk0000033e ( + .CI(\blk00000001/sig00000691 ), + .DI(\blk00000001/sig000002cb ), + .S(\blk00000001/sig0000067f ), + .O(\blk00000001/sig00000690 ) + ); + MUXCY \blk00000001/blk0000033d ( + .CI(\blk00000001/sig00000690 ), + .DI(\blk00000001/sig000002cc ), + .S(\blk00000001/sig0000067e ), + .O(\blk00000001/sig0000068f ) + ); + MUXCY \blk00000001/blk0000033c ( + .CI(\blk00000001/sig0000068f ), + .DI(\blk00000001/sig000002cd ), + .S(\blk00000001/sig0000067d ), + .O(\blk00000001/sig0000068e ) + ); + MUXCY \blk00000001/blk0000033b ( + .CI(\blk00000001/sig0000068e ), + .DI(\blk00000001/sig000002ce ), + .S(\blk00000001/sig0000067c ), + .O(\blk00000001/sig0000068d ) + ); + MUXCY \blk00000001/blk0000033a ( + .CI(\blk00000001/sig0000068d ), + .DI(\blk00000001/sig000002cf ), + .S(\blk00000001/sig0000067b ), + .O(\blk00000001/sig0000068c ) + ); + MUXCY \blk00000001/blk00000339 ( + .CI(\blk00000001/sig0000068c ), + .DI(\blk00000001/sig000002d0 ), + .S(\blk00000001/sig0000067a ), + .O(\blk00000001/sig0000068b ) + ); + MUXCY \blk00000001/blk00000338 ( + .CI(\blk00000001/sig0000068b ), + .DI(\blk00000001/sig000002d1 ), + .S(\blk00000001/sig00000679 ), + .O(\blk00000001/sig0000068a ) + ); + XORCY \blk00000001/blk00000337 ( + .CI(\blk00000001/sig00000699 ), + .LI(\blk00000001/sig00000687 ), + .O(\blk00000001/sig000002b2 ) + ); + XORCY \blk00000001/blk00000336 ( + .CI(\blk00000001/sig00000698 ), + .LI(\blk00000001/sig00000686 ), + .O(\blk00000001/sig000002b3 ) + ); + XORCY \blk00000001/blk00000335 ( + .CI(\blk00000001/sig00000697 ), + .LI(\blk00000001/sig00000685 ), + .O(\blk00000001/sig000002b4 ) + ); + XORCY \blk00000001/blk00000334 ( + .CI(\blk00000001/sig00000696 ), + .LI(\blk00000001/sig00000684 ), + .O(\blk00000001/sig000002b5 ) + ); + XORCY \blk00000001/blk00000333 ( + .CI(\blk00000001/sig00000695 ), + .LI(\blk00000001/sig00000683 ), + .O(\blk00000001/sig000002b6 ) + ); + XORCY \blk00000001/blk00000332 ( + .CI(\blk00000001/sig00000694 ), + .LI(\blk00000001/sig00000682 ), + .O(\blk00000001/sig000002b7 ) + ); + XORCY \blk00000001/blk00000331 ( + .CI(\blk00000001/sig00000693 ), + .LI(\blk00000001/sig00000681 ), + .O(\blk00000001/sig000002b8 ) + ); + XORCY \blk00000001/blk00000330 ( + .CI(\blk00000001/sig00000692 ), + .LI(\blk00000001/sig00000680 ), + .O(\blk00000001/sig000002b9 ) + ); + XORCY \blk00000001/blk0000032f ( + .CI(\blk00000001/sig00000691 ), + .LI(\blk00000001/sig0000067f ), + .O(\blk00000001/sig000002ba ) + ); + XORCY \blk00000001/blk0000032e ( + .CI(\blk00000001/sig00000690 ), + .LI(\blk00000001/sig0000067e ), + .O(\blk00000001/sig000002bb ) + ); + XORCY \blk00000001/blk0000032d ( + .CI(\blk00000001/sig0000068f ), + .LI(\blk00000001/sig0000067d ), + .O(\blk00000001/sig000002bc ) + ); + XORCY \blk00000001/blk0000032c ( + .CI(\blk00000001/sig0000068e ), + .LI(\blk00000001/sig0000067c ), + .O(\blk00000001/sig000002bd ) + ); + XORCY \blk00000001/blk0000032b ( + .CI(\blk00000001/sig0000068d ), + .LI(\blk00000001/sig0000067b ), + .O(\blk00000001/sig000002be ) + ); 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+ FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk00000131 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000004f7 ), + .Q(\blk00000001/sig000004ac ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk00000130 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000004f8 ), + .Q(\blk00000001/sig000004ad ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk0000012f ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000004f9 ), + .Q(\blk00000001/sig000004ae ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk0000012e ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000004fa ), + .Q(\blk00000001/sig000004af ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000012d ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000004a0 ), + .Q(\blk00000001/sig00000455 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk0000012c ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000004a1 ), + .Q(\blk00000001/sig00000456 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk0000012b ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000004a2 ), + .Q(\blk00000001/sig00000457 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk0000012a ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000004a3 ), + .Q(\blk00000001/sig00000458 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk00000129 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000004a4 ), + .Q(\blk00000001/sig00000459 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk00000128 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000004a5 ), + .Q(\blk00000001/sig0000045a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk00000127 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000004a6 ), + .Q(\blk00000001/sig0000045b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk00000126 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000004a7 ), + .Q(\blk00000001/sig0000045c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk00000125 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000004a8 ), + .Q(\blk00000001/sig0000045d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk00000124 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000004a9 ), + .Q(\blk00000001/sig0000045e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk00000123 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000004aa ), + .Q(\blk00000001/sig0000045f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk00000122 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000004ab ), + .Q(\blk00000001/sig00000460 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk00000121 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000004ac ), + .Q(\blk00000001/sig00000461 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk00000120 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000004ad ), + .Q(\blk00000001/sig00000462 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk0000011f ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000004ae ), + .Q(\blk00000001/sig00000463 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk0000011e ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000004af ), + .Q(\blk00000001/sig00000464 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000011d ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000455 ), + .Q(\blk00000001/sig0000040a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk0000011c ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000456 ), + .Q(\blk00000001/sig0000040b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk0000011b ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000457 ), + .Q(\blk00000001/sig0000040c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk0000011a ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000458 ), + .Q(\blk00000001/sig0000040d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk00000119 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000459 ), + .Q(\blk00000001/sig0000040e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk00000118 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000045a ), + .Q(\blk00000001/sig0000040f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk00000117 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000045b ), + .Q(\blk00000001/sig00000410 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk00000116 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000045c ), + .Q(\blk00000001/sig00000411 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk00000115 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000045d ), + .Q(\blk00000001/sig00000412 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk00000114 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000045e ), + .Q(\blk00000001/sig00000413 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk00000113 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000045f ), + .Q(\blk00000001/sig00000414 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk00000112 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000460 ), + .Q(\blk00000001/sig00000415 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk00000111 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000461 ), + .Q(\blk00000001/sig00000416 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk00000110 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000462 ), + .Q(\blk00000001/sig00000417 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk0000010f ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000463 ), + .Q(\blk00000001/sig00000418 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk0000010e ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000464 ), + .Q(\blk00000001/sig00000419 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000010d ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000040a ), + .Q(\blk00000001/sig000003bf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk0000010c ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000040b ), + .Q(\blk00000001/sig000003c0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk0000010b ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000040c ), + .Q(\blk00000001/sig000003c1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk0000010a ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000040d ), + .Q(\blk00000001/sig000003c2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk00000109 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000040e ), + .Q(\blk00000001/sig000003c3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk00000108 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000040f ), + .Q(\blk00000001/sig000003c4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk00000107 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000410 ), + .Q(\blk00000001/sig000003c5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk00000106 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000411 ), + .Q(\blk00000001/sig000003c6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk00000105 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000412 ), + .Q(\blk00000001/sig000003c7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk00000104 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000413 ), + .Q(\blk00000001/sig000003c8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk00000103 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000414 ), + .Q(\blk00000001/sig000003c9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk00000102 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000415 ), + .Q(\blk00000001/sig000003ca ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk00000101 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000416 ), + .Q(\blk00000001/sig000003cb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk00000100 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000417 ), + .Q(\blk00000001/sig000003cc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000ff ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000418 ), + .Q(\blk00000001/sig000003cd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000fe ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000419 ), + .Q(\blk00000001/sig000003ce ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk000000fd ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000003bf ), + .Q(\blk00000001/sig00000374 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000fc ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000003c0 ), + .Q(\blk00000001/sig00000375 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000fb ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000003c1 ), + .Q(\blk00000001/sig00000376 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000fa ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000003c2 ), + .Q(\blk00000001/sig00000377 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000f9 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000003c3 ), + .Q(\blk00000001/sig00000378 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000f8 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000003c4 ), + .Q(\blk00000001/sig00000379 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000f7 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000003c5 ), + .Q(\blk00000001/sig0000037a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000f6 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000003c6 ), + .Q(\blk00000001/sig0000037b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000f5 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000003c7 ), + .Q(\blk00000001/sig0000037c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000f4 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000003c8 ), + .Q(\blk00000001/sig0000037d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000f3 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000003c9 ), + .Q(\blk00000001/sig0000037e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000f2 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000003ca ), + .Q(\blk00000001/sig0000037f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000f1 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000003cb ), + .Q(\blk00000001/sig00000380 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000f0 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000003cc ), + .Q(\blk00000001/sig00000381 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000ef ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000003cd ), + .Q(\blk00000001/sig00000382 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000ee ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000003ce ), + .Q(\blk00000001/sig00000383 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk000000ed ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000374 ), + .Q(\blk00000001/sig00000325 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000ec ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000375 ), + .Q(\blk00000001/sig00000326 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000eb ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000376 ), + .Q(\blk00000001/sig00000327 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000ea ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000377 ), + .Q(\blk00000001/sig00000328 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000e9 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000378 ), + .Q(\blk00000001/sig00000329 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000e8 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000379 ), + .Q(\blk00000001/sig0000032a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000e7 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000037a ), + .Q(\blk00000001/sig0000032b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000e6 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000037b ), + .Q(\blk00000001/sig0000032c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000e5 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000037c ), + .Q(\blk00000001/sig0000032d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000e4 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000037d ), + .Q(\blk00000001/sig0000032e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000e3 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000037e ), + .Q(\blk00000001/sig0000032f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000e2 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000037f ), + .Q(\blk00000001/sig00000330 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000e1 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000380 ), + .Q(\blk00000001/sig00000331 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000e0 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000381 ), + .Q(\blk00000001/sig00000332 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000df ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000382 ), + .Q(\blk00000001/sig00000333 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000de ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000383 ), + .Q(\blk00000001/sig00000334 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk000000dd ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000325 ), + .Q(\blk00000001/sig000002d3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000dc ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000326 ), + .Q(\blk00000001/sig000002d4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000db ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000327 ), + .Q(\blk00000001/sig000002d5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000da ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000328 ), + .Q(\blk00000001/sig000002d6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000d9 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000329 ), + .Q(\blk00000001/sig000002d7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000d8 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000032a ), + .Q(\blk00000001/sig000002d8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000d7 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000032b ), + .Q(\blk00000001/sig000002d9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000d6 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000032c ), + .Q(\blk00000001/sig000002da ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000d5 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000032d ), + .Q(\blk00000001/sig000002db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000d4 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000032e ), + .Q(\blk00000001/sig000002dc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000d3 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000032f ), + .Q(\blk00000001/sig000002dd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000d2 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000330 ), + .Q(\blk00000001/sig000002de ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000d1 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000331 ), + .Q(\blk00000001/sig000002df ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000d0 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000332 ), + .Q(\blk00000001/sig000002e0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000cf ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000333 ), + .Q(\blk00000001/sig000002e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000ce ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000334 ), + .Q(\blk00000001/sig000002e2 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk000000cd ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000002d3 ), + .Q(\blk00000001/sig0000027d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000cc ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000002d4 ), + .Q(\blk00000001/sig0000027e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000cb ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000002d5 ), + .Q(\blk00000001/sig0000027f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000ca ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000002d6 ), + .Q(\blk00000001/sig00000280 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000c9 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000002d7 ), + .Q(\blk00000001/sig00000281 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000c8 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000002d8 ), + .Q(\blk00000001/sig00000282 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000c7 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000002d9 ), + .Q(\blk00000001/sig00000283 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000c6 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000002da ), + .Q(\blk00000001/sig00000284 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000c5 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000002db ), + .Q(\blk00000001/sig00000285 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000c4 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000002dc ), + .Q(\blk00000001/sig00000286 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000c3 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000002dd ), + .Q(\blk00000001/sig00000287 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000c2 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000002de ), + .Q(\blk00000001/sig00000288 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000c1 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000002df ), + .Q(\blk00000001/sig00000289 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000c0 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000002e0 ), + .Q(\blk00000001/sig0000028a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000bf ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000002e1 ), + .Q(\blk00000001/sig0000028b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000be ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig000002e2 ), + .Q(\blk00000001/sig0000028c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000bd ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig00000096 ), + .Q(\blk00000001/sig00000546 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000bc ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig00000097 ), + .Q(\blk00000001/sig00000547 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000bb ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig00000098 ), + .Q(\blk00000001/sig00000548 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000ba ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig00000099 ), + .Q(\blk00000001/sig00000549 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000b9 ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig0000009a ), + .Q(\blk00000001/sig0000054a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000b8 ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig0000009b ), + .Q(\blk00000001/sig0000054b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000b7 ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig0000009c ), + .Q(\blk00000001/sig0000054c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000b6 ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig0000009d ), + .Q(\blk00000001/sig0000054d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000b5 ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig0000009e ), + .Q(\blk00000001/sig0000054e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000b4 ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig0000009f ), + .Q(\blk00000001/sig0000054f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000b3 ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig000000a0 ), + .Q(\blk00000001/sig00000550 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000b2 ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig000000a1 ), + .Q(\blk00000001/sig00000551 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000b1 ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig000000a2 ), + .Q(\blk00000001/sig00000552 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000b0 ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig000000a3 ), + .Q(\blk00000001/sig00000553 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000af ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig000000a4 ), + .Q(\blk00000001/sig00000554 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000ae ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig000000a5 ), + .Q(\blk00000001/sig00000555 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000ad ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig000000a6 ), + .Q(\blk00000001/sig00000556 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000ac ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig000000a7 ), + .Q(\blk00000001/sig00000557 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000ab ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig000000a8 ), + .Q(\blk00000001/sig00000558 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000aa ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig000000a9 ), + .Q(\blk00000001/sig00000559 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000a9 ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig000000aa ), + .Q(\blk00000001/sig0000055a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000a8 ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig000000ab ), + .Q(\blk00000001/sig0000055b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000a7 ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig000000ac ), + .Q(\blk00000001/sig0000055c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk000000a6 ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig000000ad ), + .Q(\blk00000001/sig0000055d ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk000000a5 ( + .C(aclk), + .D(\blk00000001/sig00000123 ), + .Q(\blk00000001/sig0000055e ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk000000a4 ( + .C(aclk), + .D(\blk00000001/sig00000122 ), + .Q(\blk00000001/sig0000055f ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk000000a3 ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig00000086 ), + .Q(\blk00000001/sig00000561 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk000000a2 ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig00000087 ), + .Q(\blk00000001/sig00000562 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk000000a1 ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig00000088 ), + .Q(\blk00000001/sig00000563 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk000000a0 ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig00000089 ), + .Q(\blk00000001/sig00000564 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000009f ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig0000008a ), + .Q(\blk00000001/sig00000565 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000009e ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig0000008b ), + .Q(\blk00000001/sig00000566 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000009d ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig0000008c ), + .Q(\blk00000001/sig00000567 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000009c ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig0000008d ), + .Q(\blk00000001/sig00000568 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000009b ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig0000008e ), + .Q(\blk00000001/sig00000569 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000009a ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig0000008f ), + .Q(\blk00000001/sig0000056a ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000099 ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig00000090 ), + .Q(\blk00000001/sig0000056b ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000098 ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig00000091 ), + .Q(\blk00000001/sig0000056c ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000097 ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig00000092 ), + .Q(\blk00000001/sig0000056d ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000096 ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig00000093 ), + .Q(\blk00000001/sig0000056e ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000095 ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig00000094 ), + .Q(\blk00000001/sig0000056f ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000094 ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig00000095 ), + .Q(\blk00000001/sig00000570 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000093 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000431 ), + .Q(\blk00000001/sig000003d6 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000092 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000424 ), + .Q(\blk00000001/sig000003d7 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000091 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000423 ), + .Q(\blk00000001/sig000003d8 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000090 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000422 ), + .Q(\blk00000001/sig000003d9 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000008f ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000425 ), + .Q(\blk00000001/sig000003da ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000008e ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000426 ), + .Q(\blk00000001/sig000003db ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000008d ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000427 ), + .Q(\blk00000001/sig000003dc ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000008c ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000428 ), + .Q(\blk00000001/sig000003dd ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000008b ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000429 ), + .Q(\blk00000001/sig000003de ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk0000008a ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000042a ), + .Q(\blk00000001/sig000003df ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000089 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000042b ), + .Q(\blk00000001/sig000003e0 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000088 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000042c ), + .Q(\blk00000001/sig000003e1 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000087 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000042d ), + .Q(\blk00000001/sig000003e2 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000086 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000042e ), + .Q(\blk00000001/sig000003e3 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000085 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig0000042f ), + .Q(\blk00000001/sig000003e4 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000001/blk00000084 ( + .C(aclk), + .CE(\blk00000001/sig00000560 ), + .D(\blk00000001/sig00000430 ), + .Q(\blk00000001/sig000003e5 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000083 ( + .C(aclk), + .D(\blk00000001/sig00000125 ), + .Q(\blk00000001/sig00000123 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000082 ( + .C(aclk), + .D(\blk00000001/sig00000124 ), + .Q(\blk00000001/sig00000122 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000081 ( + .C(aclk), + .D(\blk00000001/sig00000058 ), + .Q(\blk00000001/sig00000560 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000080 ( + .C(aclk), + .D(\blk00000001/sig00000126 ), + .Q(\blk00000001/sig00000058 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk0000007f ( + .C(aclk), + .D(\blk00000001/sig00000127 ), + .Q(NlwRenamedSig_OI_s_axis_dividend_tready) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk0000007e ( + .C(aclk), + .D(\blk00000001/sig00000082 ), + .Q(\blk00000001/sig00000120 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk0000007d ( + .C(aclk), + .D(\blk00000001/sig00000083 ), + .Q(\blk00000001/sig00000121 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk0000007c ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig00000085 ), + .Q(\blk00000001/sig00000083 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000001/blk0000007b ( + .C(aclk), + .CE(\blk00000001/sig00000058 ), + .D(\blk00000001/sig00000084 ), + .Q(\blk00000001/sig00000082 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk0000007a ( + .C(aclk), + .D(s_axis_dividend_tdata[23]), + .Q(\blk00000001/sig00000085 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000079 ( + .C(aclk), + .D(s_axis_divisor_tdata[15]), + .Q(\blk00000001/sig00000084 ) + ); + FD #( + .INIT ( 1'b1 )) + \blk00000001/blk00000078 ( + .C(aclk), + .D(\blk00000001/sig00000102 ), + .Q(\blk00000001/sig00000086 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000077 ( + .C(aclk), + .D(\blk00000001/sig00000103 ), + .Q(\blk00000001/sig00000087 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000076 ( + .C(aclk), + .D(\blk00000001/sig00000104 ), + .Q(\blk00000001/sig00000088 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000075 ( + .C(aclk), + .D(\blk00000001/sig00000105 ), + .Q(\blk00000001/sig00000089 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000074 ( + .C(aclk), + .D(\blk00000001/sig00000106 ), + .Q(\blk00000001/sig0000008a ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000073 ( + .C(aclk), + .D(\blk00000001/sig00000107 ), + .Q(\blk00000001/sig0000008b ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000072 ( + .C(aclk), + .D(\blk00000001/sig00000108 ), + .Q(\blk00000001/sig0000008c ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000071 ( + .C(aclk), + .D(\blk00000001/sig00000109 ), + .Q(\blk00000001/sig0000008d ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000070 ( + .C(aclk), + .D(\blk00000001/sig0000010a ), + .Q(\blk00000001/sig0000008e ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk0000006f ( + .C(aclk), + .D(\blk00000001/sig0000010b ), + .Q(\blk00000001/sig0000008f ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk0000006e ( + .C(aclk), + .D(\blk00000001/sig0000010c ), + .Q(\blk00000001/sig00000090 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk0000006d ( + .C(aclk), + .D(\blk00000001/sig0000010d ), + .Q(\blk00000001/sig00000091 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk0000006c ( + .C(aclk), + .D(\blk00000001/sig0000010e ), + .Q(\blk00000001/sig00000092 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk0000006b ( + .C(aclk), + .D(\blk00000001/sig0000010f ), + .Q(\blk00000001/sig00000093 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk0000006a ( + .C(aclk), + .D(\blk00000001/sig00000110 ), + .Q(\blk00000001/sig00000094 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000069 ( + .C(aclk), + .D(\blk00000001/sig00000111 ), + .Q(\blk00000001/sig00000095 ) + ); + MUXCY \blk00000001/blk00000068 ( + .CI(\blk00000001/sig00000363 ), + .DI(s_axis_divisor_tdata[15]), + .S(\blk00000001/sig00000731 ), + .O(\blk00000001/sig00000101 ) + ); + XORCY \blk00000001/blk00000067 ( + .CI(\blk00000001/sig00000363 ), + .LI(\blk00000001/sig00000731 ), + .O(\blk00000001/sig00000102 ) + ); + MUXCY \blk00000001/blk00000066 ( + .CI(\blk00000001/sig00000101 ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig00000112 ), + .O(\blk00000001/sig00000100 ) + ); + XORCY \blk00000001/blk00000065 ( + .CI(\blk00000001/sig00000101 ), + .LI(\blk00000001/sig00000112 ), + .O(\blk00000001/sig00000103 ) + ); + MUXCY \blk00000001/blk00000064 ( + .CI(\blk00000001/sig00000100 ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig00000113 ), + .O(\blk00000001/sig000000ff ) + ); + XORCY \blk00000001/blk00000063 ( + .CI(\blk00000001/sig00000100 ), + .LI(\blk00000001/sig00000113 ), + .O(\blk00000001/sig00000104 ) + ); + MUXCY \blk00000001/blk00000062 ( + .CI(\blk00000001/sig000000ff ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig00000114 ), + .O(\blk00000001/sig000000fe ) + ); + XORCY \blk00000001/blk00000061 ( + .CI(\blk00000001/sig000000ff ), + .LI(\blk00000001/sig00000114 ), + .O(\blk00000001/sig00000105 ) + ); + MUXCY \blk00000001/blk00000060 ( + .CI(\blk00000001/sig000000fe ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig00000115 ), + .O(\blk00000001/sig000000fd ) + ); + XORCY \blk00000001/blk0000005f ( + .CI(\blk00000001/sig000000fe ), + .LI(\blk00000001/sig00000115 ), + .O(\blk00000001/sig00000106 ) + ); + MUXCY \blk00000001/blk0000005e ( + .CI(\blk00000001/sig000000fd ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig00000116 ), + .O(\blk00000001/sig000000fc ) + ); + XORCY \blk00000001/blk0000005d ( + .CI(\blk00000001/sig000000fd ), + .LI(\blk00000001/sig00000116 ), + .O(\blk00000001/sig00000107 ) + ); + MUXCY \blk00000001/blk0000005c ( + .CI(\blk00000001/sig000000fc ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig00000117 ), + .O(\blk00000001/sig000000fb ) + ); + XORCY \blk00000001/blk0000005b ( + .CI(\blk00000001/sig000000fc ), + .LI(\blk00000001/sig00000117 ), + .O(\blk00000001/sig00000108 ) + ); + MUXCY \blk00000001/blk0000005a ( + .CI(\blk00000001/sig000000fb ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig00000118 ), + .O(\blk00000001/sig000000fa ) + ); + XORCY \blk00000001/blk00000059 ( + .CI(\blk00000001/sig000000fb ), + .LI(\blk00000001/sig00000118 ), + .O(\blk00000001/sig00000109 ) + ); + MUXCY \blk00000001/blk00000058 ( + .CI(\blk00000001/sig000000fa ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig00000119 ), + .O(\blk00000001/sig000000f9 ) + ); + XORCY \blk00000001/blk00000057 ( + .CI(\blk00000001/sig000000fa ), + .LI(\blk00000001/sig00000119 ), + .O(\blk00000001/sig0000010a ) + ); + MUXCY \blk00000001/blk00000056 ( + .CI(\blk00000001/sig000000f9 ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig0000011a ), + .O(\blk00000001/sig000000f8 ) + ); + XORCY \blk00000001/blk00000055 ( + .CI(\blk00000001/sig000000f9 ), + .LI(\blk00000001/sig0000011a ), + .O(\blk00000001/sig0000010b ) + ); + MUXCY \blk00000001/blk00000054 ( + .CI(\blk00000001/sig000000f8 ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig0000011b ), + .O(\blk00000001/sig000000f7 ) + ); + XORCY \blk00000001/blk00000053 ( + .CI(\blk00000001/sig000000f8 ), + .LI(\blk00000001/sig0000011b ), + .O(\blk00000001/sig0000010c ) + ); + MUXCY \blk00000001/blk00000052 ( + .CI(\blk00000001/sig000000f7 ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig0000011c ), + .O(\blk00000001/sig000000f6 ) + ); + XORCY \blk00000001/blk00000051 ( + .CI(\blk00000001/sig000000f7 ), + .LI(\blk00000001/sig0000011c ), + .O(\blk00000001/sig0000010d ) + ); + MUXCY \blk00000001/blk00000050 ( + .CI(\blk00000001/sig000000f6 ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig0000011d ), + .O(\blk00000001/sig000000f5 ) + ); + XORCY \blk00000001/blk0000004f ( + .CI(\blk00000001/sig000000f6 ), + .LI(\blk00000001/sig0000011d ), + .O(\blk00000001/sig0000010e ) + ); + MUXCY \blk00000001/blk0000004e ( + .CI(\blk00000001/sig000000f5 ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig0000011e ), + .O(\blk00000001/sig000000f4 ) + ); + XORCY \blk00000001/blk0000004d ( + .CI(\blk00000001/sig000000f5 ), + .LI(\blk00000001/sig0000011e ), + .O(\blk00000001/sig0000010f ) + ); + MUXCY \blk00000001/blk0000004c ( + .CI(\blk00000001/sig000000f4 ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig0000011f ), + .O(\blk00000001/sig000000f3 ) + ); + XORCY \blk00000001/blk0000004b ( + .CI(\blk00000001/sig000000f4 ), + .LI(\blk00000001/sig0000011f ), + .O(\blk00000001/sig00000110 ) + ); + XORCY \blk00000001/blk0000004a ( + .CI(\blk00000001/sig000000f3 ), + .LI(\blk00000001/sig00000363 ), + .O(\blk00000001/sig00000111 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000049 ( + .C(aclk), + .D(\blk00000001/sig000000c5 ), + .Q(\blk00000001/sig00000096 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000048 ( + .C(aclk), + .D(\blk00000001/sig000000c6 ), + .Q(\blk00000001/sig00000097 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000047 ( + .C(aclk), + .D(\blk00000001/sig000000c7 ), + .Q(\blk00000001/sig00000098 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000046 ( + .C(aclk), + .D(\blk00000001/sig000000c8 ), + .Q(\blk00000001/sig00000099 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000045 ( + .C(aclk), + .D(\blk00000001/sig000000c9 ), + .Q(\blk00000001/sig0000009a ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000044 ( + .C(aclk), + .D(\blk00000001/sig000000ca ), + .Q(\blk00000001/sig0000009b ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000043 ( + .C(aclk), + .D(\blk00000001/sig000000cb ), + .Q(\blk00000001/sig0000009c ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000042 ( + .C(aclk), + .D(\blk00000001/sig000000cc ), + .Q(\blk00000001/sig0000009d ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000041 ( + .C(aclk), + .D(\blk00000001/sig000000cd ), + .Q(\blk00000001/sig0000009e ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000040 ( + .C(aclk), + .D(\blk00000001/sig000000ce ), + .Q(\blk00000001/sig0000009f ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk0000003f ( + .C(aclk), + .D(\blk00000001/sig000000cf ), + .Q(\blk00000001/sig000000a0 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk0000003e ( + .C(aclk), + .D(\blk00000001/sig000000d0 ), + .Q(\blk00000001/sig000000a1 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk0000003d ( + .C(aclk), + .D(\blk00000001/sig000000d1 ), + .Q(\blk00000001/sig000000a2 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk0000003c ( + .C(aclk), + .D(\blk00000001/sig000000d2 ), + .Q(\blk00000001/sig000000a3 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk0000003b ( + .C(aclk), + .D(\blk00000001/sig000000d3 ), + .Q(\blk00000001/sig000000a4 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk0000003a ( + .C(aclk), + .D(\blk00000001/sig000000d4 ), + .Q(\blk00000001/sig000000a5 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000039 ( + .C(aclk), + .D(\blk00000001/sig000000d5 ), + .Q(\blk00000001/sig000000a6 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000038 ( + .C(aclk), + .D(\blk00000001/sig000000d6 ), + .Q(\blk00000001/sig000000a7 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000037 ( + .C(aclk), + .D(\blk00000001/sig000000d7 ), + .Q(\blk00000001/sig000000a8 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000036 ( + .C(aclk), + .D(\blk00000001/sig000000d8 ), + .Q(\blk00000001/sig000000a9 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000035 ( + .C(aclk), + .D(\blk00000001/sig000000d9 ), + .Q(\blk00000001/sig000000aa ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000034 ( + .C(aclk), + .D(\blk00000001/sig000000da ), + .Q(\blk00000001/sig000000ab ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000033 ( + .C(aclk), + .D(\blk00000001/sig000000db ), + .Q(\blk00000001/sig000000ac ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000001/blk00000032 ( + .C(aclk), + .D(\blk00000001/sig000000dc ), + .Q(\blk00000001/sig000000ad ) + ); + MUXCY \blk00000001/blk00000031 ( + .CI(\blk00000001/sig00000363 ), + .DI(s_axis_dividend_tdata[23]), + .S(\blk00000001/sig00000730 ), + .O(\blk00000001/sig000000c4 ) + ); + XORCY \blk00000001/blk00000030 ( + .CI(\blk00000001/sig00000363 ), + .LI(\blk00000001/sig00000730 ), + .O(\blk00000001/sig000000c5 ) + ); + MUXCY \blk00000001/blk0000002f ( + .CI(\blk00000001/sig000000c4 ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig000000dd ), + .O(\blk00000001/sig000000c3 ) + ); + XORCY \blk00000001/blk0000002e ( + .CI(\blk00000001/sig000000c4 ), + .LI(\blk00000001/sig000000dd ), + .O(\blk00000001/sig000000c6 ) + ); + MUXCY \blk00000001/blk0000002d ( + .CI(\blk00000001/sig000000c3 ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig000000de ), + .O(\blk00000001/sig000000c2 ) + ); + XORCY \blk00000001/blk0000002c ( + .CI(\blk00000001/sig000000c3 ), + .LI(\blk00000001/sig000000de ), + .O(\blk00000001/sig000000c7 ) + ); + MUXCY \blk00000001/blk0000002b ( + .CI(\blk00000001/sig000000c2 ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig000000df ), + .O(\blk00000001/sig000000c1 ) + ); + XORCY \blk00000001/blk0000002a ( + .CI(\blk00000001/sig000000c2 ), + .LI(\blk00000001/sig000000df ), + .O(\blk00000001/sig000000c8 ) + ); + MUXCY \blk00000001/blk00000029 ( + .CI(\blk00000001/sig000000c1 ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig000000e0 ), + .O(\blk00000001/sig000000c0 ) + ); + XORCY \blk00000001/blk00000028 ( + .CI(\blk00000001/sig000000c1 ), + .LI(\blk00000001/sig000000e0 ), + .O(\blk00000001/sig000000c9 ) + ); + MUXCY \blk00000001/blk00000027 ( + .CI(\blk00000001/sig000000c0 ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig000000e1 ), + .O(\blk00000001/sig000000bf ) + ); + XORCY \blk00000001/blk00000026 ( + .CI(\blk00000001/sig000000c0 ), + .LI(\blk00000001/sig000000e1 ), + .O(\blk00000001/sig000000ca ) + ); + MUXCY \blk00000001/blk00000025 ( + .CI(\blk00000001/sig000000bf ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig000000e2 ), + .O(\blk00000001/sig000000be ) + ); + XORCY \blk00000001/blk00000024 ( + .CI(\blk00000001/sig000000bf ), + .LI(\blk00000001/sig000000e2 ), + .O(\blk00000001/sig000000cb ) + ); + MUXCY \blk00000001/blk00000023 ( + .CI(\blk00000001/sig000000be ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig000000e3 ), + .O(\blk00000001/sig000000bd ) + ); + XORCY \blk00000001/blk00000022 ( + .CI(\blk00000001/sig000000be ), + .LI(\blk00000001/sig000000e3 ), + .O(\blk00000001/sig000000cc ) + ); + MUXCY \blk00000001/blk00000021 ( + .CI(\blk00000001/sig000000bd ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig000000e4 ), + .O(\blk00000001/sig000000bc ) + ); + XORCY \blk00000001/blk00000020 ( + .CI(\blk00000001/sig000000bd ), + .LI(\blk00000001/sig000000e4 ), + .O(\blk00000001/sig000000cd ) + ); + MUXCY \blk00000001/blk0000001f ( + .CI(\blk00000001/sig000000bc ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig000000e5 ), + .O(\blk00000001/sig000000bb ) + ); + XORCY \blk00000001/blk0000001e ( + .CI(\blk00000001/sig000000bc ), + .LI(\blk00000001/sig000000e5 ), + .O(\blk00000001/sig000000ce ) + ); + MUXCY \blk00000001/blk0000001d ( + .CI(\blk00000001/sig000000bb ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig000000e6 ), + .O(\blk00000001/sig000000ba ) + ); + XORCY \blk00000001/blk0000001c ( + .CI(\blk00000001/sig000000bb ), + .LI(\blk00000001/sig000000e6 ), + .O(\blk00000001/sig000000cf ) + ); + MUXCY \blk00000001/blk0000001b ( + .CI(\blk00000001/sig000000ba ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig000000e7 ), + .O(\blk00000001/sig000000b9 ) + ); + XORCY \blk00000001/blk0000001a ( + .CI(\blk00000001/sig000000ba ), + .LI(\blk00000001/sig000000e7 ), + .O(\blk00000001/sig000000d0 ) + ); + MUXCY \blk00000001/blk00000019 ( + .CI(\blk00000001/sig000000b9 ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig000000e8 ), + .O(\blk00000001/sig000000b8 ) + ); + XORCY \blk00000001/blk00000018 ( + .CI(\blk00000001/sig000000b9 ), + .LI(\blk00000001/sig000000e8 ), + .O(\blk00000001/sig000000d1 ) + ); + MUXCY \blk00000001/blk00000017 ( + .CI(\blk00000001/sig000000b8 ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig000000e9 ), + .O(\blk00000001/sig000000b7 ) + ); + XORCY \blk00000001/blk00000016 ( + .CI(\blk00000001/sig000000b8 ), + .LI(\blk00000001/sig000000e9 ), + .O(\blk00000001/sig000000d2 ) + ); + MUXCY \blk00000001/blk00000015 ( + .CI(\blk00000001/sig000000b7 ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig000000ea ), + .O(\blk00000001/sig000000b6 ) + ); + XORCY \blk00000001/blk00000014 ( + .CI(\blk00000001/sig000000b7 ), + .LI(\blk00000001/sig000000ea ), + .O(\blk00000001/sig000000d3 ) + ); + MUXCY \blk00000001/blk00000013 ( + .CI(\blk00000001/sig000000b6 ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig000000eb ), + .O(\blk00000001/sig000000b5 ) + ); + XORCY \blk00000001/blk00000012 ( + .CI(\blk00000001/sig000000b6 ), + .LI(\blk00000001/sig000000eb ), + .O(\blk00000001/sig000000d4 ) + ); + MUXCY \blk00000001/blk00000011 ( + .CI(\blk00000001/sig000000b5 ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig000000ec ), + .O(\blk00000001/sig000000b4 ) + ); + XORCY \blk00000001/blk00000010 ( + .CI(\blk00000001/sig000000b5 ), + .LI(\blk00000001/sig000000ec ), + .O(\blk00000001/sig000000d5 ) + ); + MUXCY \blk00000001/blk0000000f ( + .CI(\blk00000001/sig000000b4 ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig000000ed ), + .O(\blk00000001/sig000000b3 ) + ); + XORCY \blk00000001/blk0000000e ( + .CI(\blk00000001/sig000000b4 ), + .LI(\blk00000001/sig000000ed ), + .O(\blk00000001/sig000000d6 ) + ); + MUXCY \blk00000001/blk0000000d ( + .CI(\blk00000001/sig000000b3 ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig000000ee ), + .O(\blk00000001/sig000000b2 ) + ); + XORCY \blk00000001/blk0000000c ( + .CI(\blk00000001/sig000000b3 ), + .LI(\blk00000001/sig000000ee ), + .O(\blk00000001/sig000000d7 ) + ); + MUXCY \blk00000001/blk0000000b ( + .CI(\blk00000001/sig000000b2 ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig000000ef ), + .O(\blk00000001/sig000000b1 ) + ); + XORCY \blk00000001/blk0000000a ( + .CI(\blk00000001/sig000000b2 ), + .LI(\blk00000001/sig000000ef ), + .O(\blk00000001/sig000000d8 ) + ); + MUXCY \blk00000001/blk00000009 ( + .CI(\blk00000001/sig000000b1 ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig000000f0 ), + .O(\blk00000001/sig000000b0 ) + ); + XORCY \blk00000001/blk00000008 ( + .CI(\blk00000001/sig000000b1 ), + .LI(\blk00000001/sig000000f0 ), + .O(\blk00000001/sig000000d9 ) + ); + MUXCY \blk00000001/blk00000007 ( + .CI(\blk00000001/sig000000b0 ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig000000f1 ), + .O(\blk00000001/sig000000af ) + ); + XORCY \blk00000001/blk00000006 ( + .CI(\blk00000001/sig000000b0 ), + .LI(\blk00000001/sig000000f1 ), + .O(\blk00000001/sig000000da ) + ); + MUXCY \blk00000001/blk00000005 ( + .CI(\blk00000001/sig000000af ), + .DI(\blk00000001/sig00000363 ), + .S(\blk00000001/sig000000f2 ), + .O(\blk00000001/sig000000ae ) + ); + XORCY \blk00000001/blk00000004 ( + .CI(\blk00000001/sig000000af ), + .LI(\blk00000001/sig000000f2 ), + .O(\blk00000001/sig000000db ) + ); + XORCY \blk00000001/blk00000003 ( + .CI(\blk00000001/sig000000ae ), + .LI(\blk00000001/sig00000363 ), + .O(\blk00000001/sig000000dc ) + ); + GND \blk00000001/blk00000002 ( + .G(\blk00000001/sig00000363 ) + ); + +// synthesis translate_on + +endmodule + +// synthesis translate_off + +`ifndef GLBL +`define GLBL + +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (weak1, weak0) GSR = GSR_int; + assign (weak1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule + +`endif + +// synthesis translate_on diff --git a/ipcore_dir/div_8_dot_8_nodsp.veo b/ipcore_dir/div_8_dot_8_nodsp.veo new file mode 100644 index 0000000..cc722aa --- /dev/null +++ b/ipcore_dir/div_8_dot_8_nodsp.veo @@ -0,0 +1,69 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used solely * +* for design, simulation, implementation and creation of design files * +* limited to Xilinx devices or technologies. Use with non-Xilinx * +* devices or technologies is expressly prohibited and immediately * +* terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY * +* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY * +* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE * +* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS * +* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY * +* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY * +* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY * +* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * +* PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support appliances, * +* devices, or systems. Use in such applications are expressly * +* prohibited. * +* * +* (c) Copyright 1995-2018 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ + +/******************************************************************************* +* Generated from core with identifier: xilinx.com:ip:div_gen:4.0 * +* * +* This core provides division using one of two algorithms. The Radix-2 * +* algorithm provides a fabric solution suitable for smaller operand * +* division, and High Radix algorithm provides a solution based upon * +* XtremeDSP slices and so is well suited to larger operands (that is * +* above about 16 bits wide). * +*******************************************************************************/ + +// Interfaces: +// M_AXIS_DOUT +// aclk_intf +// aresetn_intf +// aclken_intf +// S_AXIS_DIVISOR +// S_AXIS_DIVIDEND + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +div_8_dot_8_nodsp your_instance_name ( + .aclk(aclk), // input aclk + .s_axis_divisor_tvalid(s_axis_divisor_tvalid), // input s_axis_divisor_tvalid + .s_axis_divisor_tready(s_axis_divisor_tready), // output s_axis_divisor_tready + .s_axis_divisor_tdata(s_axis_divisor_tdata), // input [15 : 0] s_axis_divisor_tdata + .s_axis_dividend_tvalid(s_axis_dividend_tvalid), // input s_axis_dividend_tvalid + .s_axis_dividend_tready(s_axis_dividend_tready), // output s_axis_dividend_tready + .s_axis_dividend_tdata(s_axis_dividend_tdata), // input [23 : 0] s_axis_dividend_tdata + .m_axis_dout_tvalid(m_axis_dout_tvalid), // output m_axis_dout_tvalid + .m_axis_dout_tdata(m_axis_dout_tdata) // output [39 : 0] m_axis_dout_tdata +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file div_8_dot_8_nodsp.v when simulating +// the core, div_8_dot_8_nodsp. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + diff --git a/ipcore_dir/div_8_dot_8_nodsp.xco b/ipcore_dir/div_8_dot_8_nodsp.xco new file mode 100644 index 0000000..b8eb314 --- /dev/null +++ b/ipcore_dir/div_8_dot_8_nodsp.xco @@ -0,0 +1,70 @@ +############################################################## +# +# Xilinx Core Generator version 14.7 +# Date: Fri Nov 30 06:46:53 2018 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:div_gen:4.0 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc6slx9 +SET devicefamily = spartan6 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = tqg144 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -2 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT Divider_Generator xilinx.com:ip:div_gen:4.0 +# END Select +# BEGIN Parameters +CSET aclken=false +CSET algorithm_type=Radix2 +CSET aresetn=false +CSET clocks_per_division=4 +CSET component_name=div_8_dot_8_nodsp +CSET divide_by_zero_detect=false +CSET dividend_and_quotient_width=24 +CSET dividend_has_tlast=false +CSET dividend_has_tuser=false +CSET dividend_tuser_width=1 +CSET divisor_has_tlast=false +CSET divisor_has_tuser=false +CSET divisor_tuser_width=1 +CSET divisor_width=16 +CSET flowcontrol=NonBlocking +CSET fractional_width=16 +CSET latency=45 +CSET latency_configuration=Automatic +CSET operand_sign=Signed +CSET optimizegoal=Performance +CSET outtlastbehv=Null +CSET outtready=false +CSET remainder_type=Fractional +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2013-07-22T10:43:42Z +# END Extra information +GENERATE +# CRC: bbab219b diff --git a/ipcore_dir/div_8_dot_8_nodsp.xise b/ipcore_dir/div_8_dot_8_nodsp.xise new file mode 100644 index 0000000..7368985 --- /dev/null +++ b/ipcore_dir/div_8_dot_8_nodsp.xise @@ -0,0 +1,73 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ipcore_dir/div_8_dot_8_nodsp/doc/div_gen_v4_0_readme.txt b/ipcore_dir/div_8_dot_8_nodsp/doc/div_gen_v4_0_readme.txt new file mode 100644 index 0000000..2f809f4 --- /dev/null +++ b/ipcore_dir/div_8_dot_8_nodsp/doc/div_gen_v4_0_readme.txt @@ -0,0 +1,164 @@ +CHANGE LOG for Xilinx LogiCORE Divider Generator 4.0 + +Release Date: October 2, 2013 +-------------------------------------------------------------------------------- + +Table of Contents + +1. INTRODUCTION +2. DEVICE SUPPORT +3. NEW FEATURE HISTORY +4. RESOLVED ISSUES +5. KNOWN ISSUES & LIMITATIONS +6. TECHNICAL SUPPORT & FEEDBACK +7. CORE RELEASE HISTORY +8. LEGAL DISCLAIMER + +-------------------------------------------------------------------------------- + + +1. INTRODUCTION + + This file contains the change log for all released versions of the Xilinx + LogiCORE IP Divider Generator. + + For the latest core updates, see the product page at: + + http://www.xilinx.com/products/ipcenter/Divider.htm + + For installation instructions for this release, please go to: + + http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm + + For system requirements: + + http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm + + +2. DEVICE SUPPORT + + 2.1. ISE + + The following device families are supported by the core for this release: + + All Series 7 devices + All Virtex-6 devices + All Spartan-6 devices + + +3. NEW FEATURE HISTORY + + 3.1 ISE + + v4.0 + - Ongoing new device support. + - AXI-4 Stream Interfaces replace old pinout + - Maximum operand and output widths increased to 64 bits. + + +4. RESOLVED ISSUES + + 4.1 ISE + + - N/A + + +5. KNOWN ISSUES & LIMITATIONS + + The following are known issues for this core at time of release: + + 5.1 ISE + - None + + - For a comprehensive listing of Known Issues for this core, please see the IP + Release Notes Guide, + + www.xilinx.com/support/documentation/user_guides/xtp025.pdf + + +6. TECHNICAL SUPPORT & FEEDBACK + + To obtain technical support, create a WebCase at www.xilinx.com/support. + Questions are routed to a team with expertise using this product. + Please feel free to leave feedback on this IP under the "Leave Feedback" + menu item in Vivado/PlanAhead. + + Xilinx provides technical support for use of this product when used + according to the guidelines described in the core documentation, and + cannot guarantee timing, functionality, or support of this product for + designs that do not follow specified guidelines. + + +7. CORE RELEASE HISTORY + +Date By Version Description +================================================================================ +10/02/2013 Xilinx, Inc. 4.0 ISE 14.7 support and Production support for Series 7 +06/19/2012 Xilinx, Inc. 4.0 ISE 14.6 support +03/20/2012 Xilinx, Inc. 4.0 ISE 14.5 support. +12/18/2012 Xilinx, Inc. 4.0 ISE 14.4 and Vivado 2012.4 support +10/16/2012 Xilinx, Inc. 4.0 ISE 14.3 and Vivado 2012.3 support +07/25/2012 Xilinx, Inc. 4.0 ISE 14.2 and Vivado 2012.2 support +04/24/2012 Xilinx, Inc. 4.0 ISE 14.1 and Vivado 2012.1 support +01/11/2012 Xilinx, Inc. 4.0 ISE 13.4 support +10/19/2011 Xilinx, Inc. 4.0 ISE 13.3 support, Artix-7 support +06/22/2011 Xilinx, Inc 4.0 13.2 support, Virtex7, Kintex7, Virtex7 + Low Power and Kintex7 Low Power Support + AXI4-Stream interfaces, 64 bit width support. +12/02/2009 Xilinx, Inc. 3.0 11.4 support, Spartan-6L support + and Automotive Spartan6 support +09/16/2009 Xilinx, Inc. 3.0 11.3 support, Virtex-6L support +06/24/2009 Xilinx, Inc. 3.0 11.2 support +04/25/2008 Xilinx, Inc. 2.0 10.1i support +01/18/2006 Xilinx, Inc. 1.0 Introduction +================================================================================ + + +8. LEGAL DISCLAIMER + + (c) Copyright 2002 - 2013 Xilinx, Inc. All rights reserved. + + This file contains confidential and proprietary information + of Xilinx, Inc. and is protected under U.S. and + international copyright and other intellectual property + laws. + + DISCLAIMER + This disclaimer is not a license and does not grant any + rights to the materials distributed herewith. Except as + otherwise provided in a valid license issued to you by + Xilinx, and to the maximum extent permitted by applicable + law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND + WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES + AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING + BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- + INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and + (2) Xilinx shall not be liable (whether in contract or tort, + including negligence, or under any other theory of + liability) for any loss or damage of any kind or nature + related to, arising under or in connection with these + materials, including for any direct, or any indirect, + special, incidental, or consequential loss or damage + (including loss of data, profits, goodwill, or any type of + loss or damage suffered as a result of any action brought + by a third party) even if such damage or loss was + reasonably foreseeable or Xilinx had been advised of the + possibility of the same. + + CRITICAL APPLICATIONS + Xilinx products are not designed or intended to be fail- + safe, or for use in any application requiring fail-safe + performance, such as life-support or safety devices or + systems, Class III medical devices, nuclear facilities, + applications related to the deployment of airbags, or any + other applications that could lead to death, personal + injury, or severe property or environmental damage + (individually and collectively, "Critical + Applications"). Customer assumes the sole risk and + liability of any use of Xilinx products in Critical + Applications, subject only to applicable laws and + regulations governing limitations on product liability. + + THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS + PART OF THIS FILE AT ALL TIMES. + diff --git a/ipcore_dir/div_8_dot_8_nodsp/doc/div_gen_v4_0_vinfo.html b/ipcore_dir/div_8_dot_8_nodsp/doc/div_gen_v4_0_vinfo.html new file mode 100644 index 0000000..094c527 --- /dev/null +++ b/ipcore_dir/div_8_dot_8_nodsp/doc/div_gen_v4_0_vinfo.html @@ -0,0 +1,175 @@ + + +div_gen_v4_0_vinfo + + + +

+CHANGE LOG for Xilinx LogiCORE Divider Generator 4.0
+
+Release Date:  October 2, 2013 
+--------------------------------------------------------------------------------
+
+Table of Contents
+
+1.   INTRODUCTION 
+2.   DEVICE SUPPORT    
+3.   NEW FEATURE HISTORY   
+4.   RESOLVED ISSUES 
+5.   KNOWN ISSUES & LIMITATIONS 
+6.   TECHNICAL SUPPORT & FEEDBACK 
+7.   CORE RELEASE HISTORY 
+8.   LEGAL DISCLAIMER 
+
+--------------------------------------------------------------------------------
+
+
+1. INTRODUCTION
+
+  This file contains the change log for all released versions of the Xilinx 
+  LogiCORE IP Divider Generator. 
+
+  For the latest core updates, see the product page at:
+
+    www.xilinx.com/products/ipcenter/Divider.htm
+
+  For installation instructions for this release, please go to:
+
+    www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
+
+  For system requirements:
+
+    www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
+
+
+2. DEVICE SUPPORT 
+
+  2.1. ISE
+
+    The following device families are supported by the core for this release:
+
+    All Series 7 devices
+    All Virtex-6 devices
+    All Spartan-6 devices
+
+
+3. NEW FEATURE HISTORY
+
+  3.1 ISE
+ 
+  v4.0
+    - Ongoing new device support.
+    - AXI-4 Stream Interfaces replace old pinout
+    - Maximum operand and output widths increased to 64 bits. 
+
+
+4. RESOLVED ISSUES 
+
+  4.1 ISE
+
+    - N/A
+
+
+5. KNOWN ISSUES & LIMITATIONS 
+
+  The following are known issues for this core at time of release:
+
+  5.1 ISE
+    - None
+
+  - For a comprehensive listing of Known Issues for this core, please see the IP 
+    Release Notes Guide,  
+    
+    www.xilinx.com/support/documentation/user_guides/xtp025.pdf
+
+
+6. TECHNICAL SUPPORT & FEEDBACK
+
+  To obtain technical support, create a WebCase at www.xilinx.com/support.
+  Questions are routed to a team with expertise using this product.
+  Please feel free to leave feedback on this IP under the "Leave Feedback"
+  menu item in Vivado/PlanAhead.
+
+  Xilinx provides technical support for use of this product when used
+  according to the guidelines described in the core documentation, and
+  cannot guarantee timing, functionality, or support of this product for
+  designs that do not follow specified guidelines.
+
+
+7. CORE RELEASE HISTORY
+
+Date        By            Version      Description
+================================================================================
+10/02/2013  Xilinx, Inc.  4.0          ISE 14.7 support and Production support for Series 7
+06/19/2012  Xilinx, Inc.  4.0          ISE 14.6 support
+03/20/2012  Xilinx, Inc.  4.0          ISE 14.5 support. 
+12/18/2012  Xilinx, Inc.  4.0          ISE 14.4 and Vivado 2012.4 support
+10/16/2012  Xilinx, Inc.  4.0          ISE 14.3 and Vivado 2012.3 support
+07/25/2012  Xilinx, Inc.  4.0          ISE 14.2 and Vivado 2012.2 support
+04/24/2012  Xilinx, Inc.  4.0          ISE 14.1 and Vivado 2012.1 support
+01/11/2012  Xilinx, Inc.  4.0          ISE 13.4 support
+10/19/2011  Xilinx, Inc.  4.0          ISE 13.3 support, Artix-7 support
+06/22/2011  Xilinx, Inc   4.0          13.2 support, Virtex7, Kintex7, Virtex7 
+                                       Low Power and Kintex7 Low Power Support
+                                       AXI4-Stream interfaces, 64 bit width support.
+12/02/2009  Xilinx, Inc.  3.0          11.4 support, Spartan-6L support
+                                       and Automotive Spartan6 support
+09/16/2009  Xilinx, Inc.  3.0          11.3 support, Virtex-6L support
+06/24/2009  Xilinx, Inc.  3.0          11.2 support
+04/25/2008  Xilinx, Inc.  2.0          10.1i support
+01/18/2006  Xilinx, Inc.  1.0          Introduction
+================================================================================
+
+
+8. LEGAL DISCLAIMER
+
+  (c) Copyright 2002 - 2013 Xilinx, Inc. All rights reserved.
+  
+  This file contains confidential and proprietary information
+  of Xilinx, Inc. and is protected under U.S. and
+  international copyright and other intellectual property
+  laws.
+  
+  DISCLAIMER
+  This disclaimer is not a license and does not grant any
+  rights to the materials distributed herewith. Except as
+  otherwise provided in a valid license issued to you by
+  Xilinx, and to the maximum extent permitted by applicable
+  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+  (2) Xilinx shall not be liable (whether in contract or tort,
+  including negligence, or under any other theory of
+  liability) for any loss or damage of any kind or nature
+  related to, arising under or in connection with these
+  materials, including for any direct, or any indirect,
+  special, incidental, or consequential loss or damage
+  (including loss of data, profits, goodwill, or any type of
+  loss or damage suffered as a result of any action brought
+  by a third party) even if such damage or loss was
+  reasonably foreseeable or Xilinx had been advised of the
+  possibility of the same.
+  
+  CRITICAL APPLICATIONS
+  Xilinx products are not designed or intended to be fail-
+  safe, or for use in any application requiring fail-safe
+  performance, such as life-support or safety devices or
+  systems, Class III medical devices, nuclear facilities,
+  applications related to the deployment of airbags, or any
+  other applications that could lead to death, personal
+  injury, or severe property or environmental damage
+  (individually and collectively, "Critical
+  Applications"). Customer assumes the sole risk and
+  liability of any use of Xilinx products in Critical
+  Applications, subject only to applicable laws and
+  regulations governing limitations on product liability.
+  
+  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+  PART OF THIS FILE AT ALL TIMES.
+  
+
+
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zHbHF4=NlVZ@`Wf4un?I+=xM>T1b@WlnL<>?gDEYv;2EQXB&twyC=Hjr(q*&Zg|4Qi K#dOPVs{aE6FuVi+ literal 0 HcmV?d00001 diff --git a/ipcore_dir/div_8_dot_8_nodsp_flist.txt b/ipcore_dir/div_8_dot_8_nodsp_flist.txt new file mode 100644 index 0000000..01ab1e8 --- /dev/null +++ b/ipcore_dir/div_8_dot_8_nodsp_flist.txt @@ -0,0 +1,15 @@ +# Output products list for +_xmsgs/pn_parser.xmsgs +demo_tb/tb_div_8_dot_8_nodsp.vhd +div_8_dot_8_nodsp/doc/div_gen_v4_0_readme.txt +div_8_dot_8_nodsp/doc/div_gen_v4_0_vinfo.html +div_8_dot_8_nodsp/doc/ds819_div_gen.pdf +div_8_dot_8_nodsp.asy +div_8_dot_8_nodsp.gise +div_8_dot_8_nodsp.ngc +div_8_dot_8_nodsp.v +div_8_dot_8_nodsp.veo +div_8_dot_8_nodsp.xco +div_8_dot_8_nodsp.xise +div_8_dot_8_nodsp_flist.txt +div_8_dot_8_nodsp_xmdf.tcl diff --git a/ipcore_dir/div_8_dot_8_nodsp_xmdf.tcl b/ipcore_dir/div_8_dot_8_nodsp_xmdf.tcl new file mode 100644 index 0000000..506e60e --- /dev/null +++ b/ipcore_dir/div_8_dot_8_nodsp_xmdf.tcl @@ -0,0 +1,83 @@ +# The package naming convention is _xmdf +package provide div_8_dot_8_nodsp_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::div_8_dot_8_nodsp_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::div_8_dot_8_nodsp_xmdf::xmdfInit { instance } { +# Variable containing name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name div_8_dot_8_nodsp +} +# ::div_8_dot_8_nodsp_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::div_8_dot_8_nodsp_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path demo_tb/tb_div_8_dot_8_nodsp.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path div_8_dot_8_nodsp/doc/div_gen_v4_0_readme.txt +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path div_8_dot_8_nodsp/doc/div_gen_v4_0_vinfo.html +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path div_8_dot_8_nodsp/doc/ds819_div_gen.pdf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path div_8_dot_8_nodsp.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path div_8_dot_8_nodsp.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path div_8_dot_8_nodsp.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path div_8_dot_8_nodsp.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path div_8_dot_8_nodsp.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path div_8_dot_8_nodsp_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module div_8_dot_8_nodsp +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/ipcore_dir/lcd_spi_clk.asy b/ipcore_dir/lcd_spi_clk.asy new file mode 100644 index 0000000..2c24774 --- /dev/null +++ b/ipcore_dir/lcd_spi_clk.asy @@ -0,0 +1,17 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 lcd_spi_clk +RECTANGLE Normal 32 32 576 1088 +LINE Normal 0 80 32 80 +PIN 0 80 LEFT 36 +PINATTR PinName clk_in1 +PINATTR Polarity IN +LINE Normal 608 80 576 80 +PIN 608 80 RIGHT 36 +PINATTR PinName clk_out1 +PINATTR Polarity OUT +LINE Normal 608 176 576 176 +PIN 608 176 RIGHT 36 +PINATTR PinName clk_out2 +PINATTR Polarity OUT + diff --git a/ipcore_dir/lcd_spi_clk.gise b/ipcore_dir/lcd_spi_clk.gise new file mode 100644 index 0000000..ee50cca --- /dev/null +++ b/ipcore_dir/lcd_spi_clk.gise @@ -0,0 +1,52 @@ + + + + + + + + + + + + + + + + + + + + 11.1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ipcore_dir/lcd_spi_clk.ncf b/ipcore_dir/lcd_spi_clk.ncf new file mode 100644 index 0000000..fc946d7 --- /dev/null +++ b/ipcore_dir/lcd_spi_clk.ncf @@ -0,0 +1,59 @@ +# file: lcd_spi_clk.ucf +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# Input clock periods. These duplicate the values entered for the +# input clocks. You can use these to time your system +#---------------------------------------------------------------- +NET "CLK_IN1" TNM_NET = "CLK_IN1"; +TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 20.0 ns HIGH 50% INPUT_JITTER 200.0ps; + + +# FALSE PATH constraints + + diff --git a/ipcore_dir/lcd_spi_clk.sym b/ipcore_dir/lcd_spi_clk.sym new file mode 100644 index 0000000..a4ff736 --- /dev/null +++ b/ipcore_dir/lcd_spi_clk.sym @@ -0,0 +1,18 @@ + + + BLOCK + 2018-12-10T8:32:51 + + + + + lcd_spi_clk + + + + + + + + + diff --git a/ipcore_dir/lcd_spi_clk.ucf b/ipcore_dir/lcd_spi_clk.ucf new file mode 100755 index 0000000..5320c00 --- /dev/null +++ b/ipcore_dir/lcd_spi_clk.ucf @@ -0,0 +1,58 @@ +# file: lcd_spi_clk.ucf +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# Input clock periods. These duplicate the values entered for the +# input clocks. You can use these to time your system +#---------------------------------------------------------------- +NET "CLK_IN1" TNM_NET = "CLK_IN1"; +TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 20.0 ns HIGH 50% INPUT_JITTER 200.0ps; + + +# FALSE PATH constraints + diff --git a/ipcore_dir/lcd_spi_clk.v b/ipcore_dir/lcd_spi_clk.v new file mode 100755 index 0000000..0924f75 --- /dev/null +++ b/ipcore_dir/lcd_spi_clk.v @@ -0,0 +1,150 @@ +// file: lcd_spi_clk.v +// +// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//---------------------------------------------------------------------------- +// User entered comments +//---------------------------------------------------------------------------- +// None +// +//---------------------------------------------------------------------------- +// "Output Output Phase Duty Pk-to-Pk Phase" +// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)" +//---------------------------------------------------------------------------- +// CLK_OUT1___250.000______0.000______50.0______280.000____150.000 +// CLK_OUT2____50.000______0.000______50.0______200.000____150.000 +// +//---------------------------------------------------------------------------- +// "Input Clock Freq (MHz) Input Jitter (UI)" +//---------------------------------------------------------------------------- +// __primary__________50.000____________0.010 + +`timescale 1ps/1ps + +(* CORE_GENERATION_INFO = "lcd_spi_clk,clk_wiz_v3_6,{component_name=lcd_spi_clk,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=2,clkin1_period=20.0,clkin2_period=20.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *) +module lcd_spi_clk + (// Clock in ports + input clk_in, + // Clock out ports + output clk_fout, + output clk_nout + ); + + // Input buffering + //------------------------------------ + IBUFG clkin1_buf + (.O (clkin1), + .I (clk_in)); + + + // Clocking primitive + //------------------------------------ + + // Instantiation of the DCM primitive + // * Unused inputs are tied off + // * Unused outputs are labeled unused + wire psdone_unused; + wire locked_int; + wire [7:0] status_int; + wire clkfb; + wire clk0; + wire clkfx; + + DCM_SP + #(.CLKDV_DIVIDE (2.000), + .CLKFX_DIVIDE (1), + .CLKFX_MULTIPLY (5), + .CLKIN_DIVIDE_BY_2 ("FALSE"), + .CLKIN_PERIOD (20.0), + .CLKOUT_PHASE_SHIFT ("NONE"), + .CLK_FEEDBACK ("1X"), + .DESKEW_ADJUST ("SYSTEM_SYNCHRONOUS"), + .PHASE_SHIFT (0), + .STARTUP_WAIT ("FALSE")) + dcm_sp_inst + // Input clock + (.CLKIN (clkin1), + .CLKFB (clkfb), + // Output clocks + .CLK0 (clk0), + .CLK90 (), + .CLK180 (), + .CLK270 (), + .CLK2X (), + .CLK2X180 (), + .CLKFX (clkfx), + .CLKFX180 (), + .CLKDV (), + // Ports for dynamic phase shift + .PSCLK (1'b0), + .PSEN (1'b0), + .PSINCDEC (1'b0), + .PSDONE (), + // Other control and status signals + .LOCKED (locked_int), + .STATUS (status_int), + .RST (1'b0), + // Unused pin- tie low + .DSSEN (1'b0)); + + + // Output buffering + //----------------------------------- + assign clkfb = clk_nout; + + BUFG clkout1_buf + (.O (clk_fout), + .I (clkfx)); + + + BUFG clkout2_buf + (.O (clk_nout), + .I (clk0)); + + + +endmodule diff --git a/ipcore_dir/lcd_spi_clk.veo b/ipcore_dir/lcd_spi_clk.veo new file mode 100755 index 0000000..3f78df7 --- /dev/null +++ b/ipcore_dir/lcd_spi_clk.veo @@ -0,0 +1,77 @@ +// +// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//---------------------------------------------------------------------------- +// User entered comments +//---------------------------------------------------------------------------- +// None +// +//---------------------------------------------------------------------------- +// "Output Output Phase Duty Pk-to-Pk Phase" +// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)" +//---------------------------------------------------------------------------- +// CLK_OUT1___250.000______0.000______50.0______280.000____150.000 +// CLK_OUT2____50.000______0.000______50.0______200.000____150.000 +// +//---------------------------------------------------------------------------- +// "Input Clock Freq (MHz) Input Jitter (UI)" +//---------------------------------------------------------------------------- +// __primary__________50.000____________0.010 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG + + lcd_spi_clk instance_name + (// Clock in ports + .clk_in(clk_in), // IN + // Clock out ports + .clk_fout(clk_fout), // OUT + .clk_nout(clk_nout)); // OUT +// INST_TAG_END ------ End INSTANTIATION Template --------- diff --git a/ipcore_dir/lcd_spi_clk.xco b/ipcore_dir/lcd_spi_clk.xco new file mode 100644 index 0000000..af9736d --- /dev/null +++ b/ipcore_dir/lcd_spi_clk.xco @@ -0,0 +1,269 @@ +############################################################## +# +# Xilinx Core Generator version 14.7 +# Date: Wed Dec 12 08:29:52 2018 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:clk_wiz:3.6 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc6slx9 +SET devicefamily = spartan6 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = tqg144 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -2 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT Clocking_Wizard xilinx.com:ip:clk_wiz:3.6 +# END Select +# BEGIN Parameters +CSET calc_done=DONE +CSET clk_in_sel_port=CLK_IN_SEL +CSET clk_out1_port=clk_fout +CSET clk_out1_use_fine_ps_gui=false +CSET clk_out2_port=clk_nout +CSET clk_out2_use_fine_ps_gui=false +CSET clk_out3_port=CLK_OUT3 +CSET clk_out3_use_fine_ps_gui=false +CSET clk_out4_port=CLK_OUT4 +CSET clk_out4_use_fine_ps_gui=false +CSET clk_out5_port=CLK_OUT5 +CSET clk_out5_use_fine_ps_gui=false +CSET clk_out6_port=CLK_OUT6 +CSET clk_out6_use_fine_ps_gui=false +CSET clk_out7_port=CLK_OUT7 +CSET clk_out7_use_fine_ps_gui=false +CSET clk_valid_port=CLK_VALID +CSET clkfb_in_n_port=CLKFB_IN_N +CSET clkfb_in_p_port=CLKFB_IN_P +CSET clkfb_in_port=CLKFB_IN +CSET clkfb_in_signaling=SINGLE +CSET clkfb_out_n_port=CLKFB_OUT_N +CSET clkfb_out_p_port=CLKFB_OUT_P +CSET clkfb_out_port=CLKFB_OUT +CSET clkfb_stopped_port=CLKFB_STOPPED +CSET clkin1_jitter_ps=200.0 +CSET clkin1_ui_jitter=0.010 +CSET clkin2_jitter_ps=100.0 +CSET clkin2_ui_jitter=0.010 +CSET clkout1_drives=BUFG +CSET clkout1_requested_duty_cycle=50.000 +CSET clkout1_requested_out_freq=250.000 +CSET clkout1_requested_phase=0.000 +CSET clkout2_drives=BUFG +CSET clkout2_requested_duty_cycle=50.000 +CSET clkout2_requested_out_freq=50.000 +CSET clkout2_requested_phase=0.000 +CSET clkout2_used=true +CSET clkout3_drives=BUFG +CSET clkout3_requested_duty_cycle=50.000 +CSET clkout3_requested_out_freq=100.000 +CSET clkout3_requested_phase=0.000 +CSET clkout3_used=false +CSET clkout4_drives=BUFG +CSET clkout4_requested_duty_cycle=50.000 +CSET clkout4_requested_out_freq=100.000 +CSET clkout4_requested_phase=0.000 +CSET clkout4_used=false +CSET clkout5_drives=BUFG +CSET clkout5_requested_duty_cycle=50.000 +CSET clkout5_requested_out_freq=100.000 +CSET clkout5_requested_phase=0.000 +CSET clkout5_used=false +CSET clkout6_drives=BUFG +CSET clkout6_requested_duty_cycle=50.000 +CSET clkout6_requested_out_freq=100.000 +CSET clkout6_requested_phase=0.000 +CSET clkout6_used=false +CSET clkout7_drives=BUFG +CSET clkout7_requested_duty_cycle=50.000 +CSET clkout7_requested_out_freq=100.000 +CSET clkout7_requested_phase=0.000 +CSET clkout7_used=false +CSET clock_mgr_type=AUTO +CSET component_name=lcd_spi_clk +CSET daddr_port=DADDR +CSET dclk_port=DCLK +CSET dcm_clk_feedback=1X +CSET dcm_clk_out1_port=CLKFX +CSET dcm_clk_out2_port=CLK0 +CSET dcm_clk_out3_port=CLK0 +CSET dcm_clk_out4_port=CLK0 +CSET dcm_clk_out5_port=CLK0 +CSET dcm_clk_out6_port=CLK0 +CSET dcm_clkdv_divide=2.0 +CSET dcm_clkfx_divide=1 +CSET dcm_clkfx_multiply=5 +CSET dcm_clkgen_clk_out1_port=CLKFX +CSET dcm_clkgen_clk_out2_port=CLKFX +CSET dcm_clkgen_clk_out3_port=CLKFX +CSET dcm_clkgen_clkfx_divide=1 +CSET dcm_clkgen_clkfx_md_max=0.000 +CSET dcm_clkgen_clkfx_multiply=4 +CSET dcm_clkgen_clkfxdv_divide=2 +CSET dcm_clkgen_clkin_period=10.000 +CSET dcm_clkgen_notes=None +CSET dcm_clkgen_spread_spectrum=NONE +CSET dcm_clkgen_startup_wait=false +CSET dcm_clkin_divide_by_2=false +CSET dcm_clkin_period=20.000 +CSET dcm_clkout_phase_shift=NONE +CSET dcm_deskew_adjust=SYSTEM_SYNCHRONOUS +CSET dcm_notes=None +CSET dcm_phase_shift=0 +CSET dcm_pll_cascade=NONE +CSET dcm_startup_wait=false +CSET den_port=DEN +CSET din_port=DIN +CSET dout_port=DOUT +CSET drdy_port=DRDY +CSET dwe_port=DWE +CSET feedback_source=FDBK_AUTO +CSET in_freq_units=Units_MHz +CSET in_jitter_units=Units_UI +CSET input_clk_stopped_port=INPUT_CLK_STOPPED +CSET jitter_options=UI +CSET jitter_sel=No_Jitter +CSET locked_port=LOCKED +CSET mmcm_bandwidth=OPTIMIZED +CSET mmcm_clkfbout_mult_f=4.000 +CSET mmcm_clkfbout_phase=0.000 +CSET mmcm_clkfbout_use_fine_ps=false +CSET mmcm_clkin1_period=10.000 +CSET mmcm_clkin2_period=10.000 +CSET mmcm_clkout0_divide_f=4.000 +CSET mmcm_clkout0_duty_cycle=0.500 +CSET mmcm_clkout0_phase=0.000 +CSET mmcm_clkout0_use_fine_ps=false +CSET mmcm_clkout1_divide=1 +CSET mmcm_clkout1_duty_cycle=0.500 +CSET mmcm_clkout1_phase=0.000 +CSET mmcm_clkout1_use_fine_ps=false +CSET mmcm_clkout2_divide=1 +CSET mmcm_clkout2_duty_cycle=0.500 +CSET mmcm_clkout2_phase=0.000 +CSET mmcm_clkout2_use_fine_ps=false +CSET mmcm_clkout3_divide=1 +CSET mmcm_clkout3_duty_cycle=0.500 +CSET mmcm_clkout3_phase=0.000 +CSET mmcm_clkout3_use_fine_ps=false +CSET mmcm_clkout4_cascade=false +CSET mmcm_clkout4_divide=1 +CSET mmcm_clkout4_duty_cycle=0.500 +CSET mmcm_clkout4_phase=0.000 +CSET mmcm_clkout4_use_fine_ps=false +CSET mmcm_clkout5_divide=1 +CSET mmcm_clkout5_duty_cycle=0.500 +CSET mmcm_clkout5_phase=0.000 +CSET mmcm_clkout5_use_fine_ps=false +CSET mmcm_clkout6_divide=1 +CSET mmcm_clkout6_duty_cycle=0.500 +CSET mmcm_clkout6_phase=0.000 +CSET mmcm_clkout6_use_fine_ps=false +CSET mmcm_clock_hold=false +CSET mmcm_compensation=ZHOLD +CSET mmcm_divclk_divide=1 +CSET mmcm_notes=None +CSET mmcm_ref_jitter1=0.010 +CSET mmcm_ref_jitter2=0.010 +CSET mmcm_startup_wait=false +CSET num_out_clks=2 +CSET override_dcm=false +CSET override_dcm_clkgen=false +CSET override_mmcm=false +CSET override_pll=false +CSET platform=lin64 +CSET pll_bandwidth=OPTIMIZED +CSET pll_clk_feedback=CLKFBOUT +CSET pll_clkfbout_mult=8 +CSET pll_clkfbout_phase=0.000 +CSET pll_clkin_period=20.0 +CSET pll_clkout0_divide=128 +CSET pll_clkout0_duty_cycle=0.500 +CSET pll_clkout0_phase=0.000 +CSET pll_clkout1_divide=8 +CSET pll_clkout1_duty_cycle=0.500 +CSET pll_clkout1_phase=0.000 +CSET pll_clkout2_divide=1 +CSET pll_clkout2_duty_cycle=0.500 +CSET pll_clkout2_phase=0.000 +CSET pll_clkout3_divide=1 +CSET pll_clkout3_duty_cycle=0.500 +CSET pll_clkout3_phase=0.000 +CSET pll_clkout4_divide=1 +CSET pll_clkout4_duty_cycle=0.500 +CSET pll_clkout4_phase=0.000 +CSET pll_clkout5_divide=1 +CSET pll_clkout5_duty_cycle=0.500 +CSET pll_clkout5_phase=0.000 +CSET pll_compensation=SYSTEM_SYNCHRONOUS +CSET pll_divclk_divide=1 +CSET pll_notes=None +CSET pll_ref_jitter=0.010 +CSET power_down_port=POWER_DOWN +CSET prim_in_freq=50.000 +CSET prim_in_jitter=0.010 +CSET prim_source=Single_ended_clock_capable_pin +CSET primary_port=clk_in +CSET primitive=MMCM +CSET primtype_sel=PLL_BASE +CSET psclk_port=PSCLK +CSET psdone_port=PSDONE +CSET psen_port=PSEN +CSET psincdec_port=PSINCDEC +CSET relative_inclk=REL_PRIMARY +CSET reset_port=RESET +CSET secondary_in_freq=100.000 +CSET secondary_in_jitter=0.010 +CSET secondary_port=CLK_IN2 +CSET secondary_source=Single_ended_clock_capable_pin +CSET ss_mod_freq=250 +CSET ss_mode=CENTER_HIGH +CSET status_port=STATUS +CSET summary_strings=empty +CSET use_clk_valid=false +CSET use_clkfb_stopped=false +CSET use_dyn_phase_shift=false +CSET use_dyn_reconfig=false +CSET use_freeze=false +CSET use_freq_synth=true +CSET use_inclk_stopped=false +CSET use_inclk_switchover=false +CSET use_locked=false +CSET use_max_i_jitter=false +CSET use_min_o_jitter=false +CSET use_min_power=false +CSET use_phase_alignment=true +CSET use_power_down=false +CSET use_reset=false +CSET use_spread_spectrum=false +CSET use_spread_spectrum_1=false +CSET use_status=false +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2012-05-10T12:44:55Z +# END Extra information +GENERATE +# CRC: cd91ca7d diff --git a/ipcore_dir/lcd_spi_clk.xdc b/ipcore_dir/lcd_spi_clk.xdc new file mode 100755 index 0000000..1ee05e8 --- /dev/null +++ b/ipcore_dir/lcd_spi_clk.xdc @@ -0,0 +1,66 @@ +# file: lcd_spi_clk.xdc +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# Input clock periods. These duplicate the values entered for the +# input clocks. You can use these to time your system +#---------------------------------------------------------------- +create_clock -name CLK_IN1 -period 20.0 [get_ports CLK_IN1] +set_propagated_clock CLK_IN1 +set_input_jitter CLK_IN1 0.2 + + +# Derived clock periods. These are commented out because they are +# automatically propogated by the tools +# However, if you'd like to use them for module level testing, you +# can copy them into your module level timing checks +#----------------------------------------------------------------- + +#----------------------------------------------------------------- + +#----------------------------------------------------------------- diff --git a/ipcore_dir/lcd_spi_clk.xise b/ipcore_dir/lcd_spi_clk.xise new file mode 100644 index 0000000..4c15e86 --- /dev/null +++ b/ipcore_dir/lcd_spi_clk.xise @@ -0,0 +1,69 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ipcore_dir/lcd_spi_clk/clk_wiz_v3_6_readme.txt b/ipcore_dir/lcd_spi_clk/clk_wiz_v3_6_readme.txt new file mode 100644 index 0000000..91dcdd0 --- /dev/null +++ b/ipcore_dir/lcd_spi_clk/clk_wiz_v3_6_readme.txt @@ -0,0 +1,184 @@ +CHANGE LOG for LogiCORE Clocking Wizard V3.6 + + Release Date: June 19, 2013 +-------------------------------------------------------------------------------- + +Table of Contents + +1. INTRODUCTION +2. DEVICE SUPPORT +3. NEW FEATURE HISTORY +4. RESOLVED ISSUES +5. KNOWN ISSUES & LIMITATIONS +6. TECHNICAL SUPPORT & FEEDBACK +7. CORE RELEASE HISTORY +8. LEGAL DISCLAIMER + +-------------------------------------------------------------------------------- + + +1. INTRODUCTION + +For installation instructions for this release, please go to: + + http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm + +For system requirements: + + http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm + +This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.6 +solution. For the latest core updates, see the product page at: + + http://www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/ + +................................................................................ + +2. DEVICE SUPPORT + + + 2.1 ISE + + + The following device families are supported by the core for this release. + + All 7 Series devices + + + Zynq-7000 devices + Zynq-7000 + Defense Grade Zynq-7000Q (XQ) + + + All Virtex-6 devices + + + All Spartan-6 devices + + +................................................................................ + +3. NEW FEATURE HISTORY + + + 3.1 ISE + + - Spread Spectrum support for 7 series MMCME2 + + - ISE 14.2 software support + +................................................................................ + +4. RESOLVED ISSUES + + + 4.1 ISE + + Resolved issue with example design becoming core top in planAhead + + Resolved issue with Virtex6 MMCM instantiation for VHDL project + Please refer to AR 50719 - http://www.xilinx.com/support/answers/50719.htm + +................................................................................ + +5. KNOWN ISSUES & LIMITATIONS + + + 5.1 ISE + + + The most recent information, including known issues, workarounds, and + resolutions for this version is provided in the IP Release Notes Guide + located at + + www.xilinx.com/support/documentation/user_guides/xtp025.pdf + + +................................................................................ + +6. TECHNICAL SUPPORT & FEEDBACK + + +To obtain technical support, create a WebCase at www.xilinx.com/support. +Questions are routed to a team with expertise using this product. + +Xilinx provides technical support for use of this product when used +according to the guidelines described in the core documentation, and +cannot guarantee timing, functionality, or support of this product for +designs that do not follow specified guidelines. + + +................................................................................ + +7. CORE RELEASE HISTORY + + +Date By Version Description +================================================================================ +06/19/2013 Xilinx, Inc. 3.6(Rev3) ISE 14.6 support +10/16/2012 Xilinx, Inc. 3.6(Rev2) ISE 14.3 support +07/25/2012 Xilinx, Inc. 3.6 ISE 14.2 support +04/24/2012 Xilinx, Inc. 3.5 ISE 14.1 support +01/18/2012 Xilinx, Inc. 3.3 ISE 13.4 support +06/22/2011 Xilinx, Inc. 3.2 ISE 13.2 support +03/01/2011 Xilinx, Inc. 3.1 ISE 13.1 support +12/14/2010 Xilinx, Inc. 1.8 ISE 12.4 support +09/21/2010 Xilinx, Inc. 1.7 ISE 12.3 support +07/23/2010 Xilinx, Inc. 1.6 ISE 12.2 support +04/19/2010 Xilinx, Inc. 1.5 ISE 12.1 support +12/02/2009 Xilinx, Inc. 1.4 ISE 11.4 support +09/16/2009 Xilinx, Inc. 1.3 ISE 11.3 support +06/24/2009 Xilinx, Inc. 1.2 ISE 11.2 support +04/24/2009 Xilinx, Inc. 1.1 Initial release; 11.1 support +================================================================================ + +................................................................................ + +8. LEGAL DISCLAIMER + +(c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. + +This file contains confidential and proprietary information +of Xilinx, Inc. and is protected under U.S. and +international copyright and other intellectual property +laws. + +DISCLAIMER +This disclaimer is not a license and does not grant any +rights to the materials distributed herewith. Except as +otherwise provided in a valid license issued to you by +Xilinx, and to the maximum extent permitted by applicable +law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +(2) Xilinx shall not be liable (whether in contract or tort, +including negligence, or under any other theory of +liability) for any loss or damage of any kind or nature +related to, arising under or in connection with these +materials, including for any direct, or any indirect, +special, incidental, or consequential loss or damage +(including loss of data, profits, goodwill, or any type of +loss or damage suffered as a result of any action brought +by a third party) even if such damage or loss was +reasonably foreseeable or Xilinx had been advised of the +possibility of the same. + +CRITICAL APPLICATIONS +Xilinx products are not designed or intended to be fail- +safe, or for use in any application requiring fail-safe +performance, such as life-support or safety devices or +systems, Class III medical devices, nuclear facilities, +applications related to the deployment of airbags, or any +other applications that could lead to death, personal +injury, or severe property or environmental damage +(individually and collectively, "Critical +Applications"). Customer assumes the sole risk and +liability of any use of Xilinx products in Critical +Applications, subject only to applicable laws and +regulations governing limitations on product liability. + +THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +PART OF THIS FILE AT ALL TIMES. + diff --git a/ipcore_dir/lcd_spi_clk/doc/clk_wiz_v3_6_readme.txt b/ipcore_dir/lcd_spi_clk/doc/clk_wiz_v3_6_readme.txt new file mode 100644 index 0000000..91dcdd0 --- /dev/null +++ b/ipcore_dir/lcd_spi_clk/doc/clk_wiz_v3_6_readme.txt @@ -0,0 +1,184 @@ +CHANGE LOG for LogiCORE Clocking Wizard V3.6 + + Release Date: June 19, 2013 +-------------------------------------------------------------------------------- + +Table of Contents + +1. INTRODUCTION +2. DEVICE SUPPORT +3. NEW FEATURE HISTORY +4. RESOLVED ISSUES +5. KNOWN ISSUES & LIMITATIONS +6. TECHNICAL SUPPORT & FEEDBACK +7. CORE RELEASE HISTORY +8. LEGAL DISCLAIMER + +-------------------------------------------------------------------------------- + + +1. INTRODUCTION + +For installation instructions for this release, please go to: + + http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm + +For system requirements: + + http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm + +This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.6 +solution. For the latest core updates, see the product page at: + + http://www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/ + +................................................................................ + +2. DEVICE SUPPORT + + + 2.1 ISE + + + The following device families are supported by the core for this release. + + All 7 Series devices + + + Zynq-7000 devices + Zynq-7000 + Defense Grade Zynq-7000Q (XQ) + + + All Virtex-6 devices + + + All Spartan-6 devices + + +................................................................................ + +3. NEW FEATURE HISTORY + + + 3.1 ISE + + - Spread Spectrum support for 7 series MMCME2 + + - ISE 14.2 software support + +................................................................................ + +4. RESOLVED ISSUES + + + 4.1 ISE + + Resolved issue with example design becoming core top in planAhead + + Resolved issue with Virtex6 MMCM instantiation for VHDL project + Please refer to AR 50719 - http://www.xilinx.com/support/answers/50719.htm + +................................................................................ + +5. KNOWN ISSUES & LIMITATIONS + + + 5.1 ISE + + + The most recent information, including known issues, workarounds, and + resolutions for this version is provided in the IP Release Notes Guide + located at + + www.xilinx.com/support/documentation/user_guides/xtp025.pdf + + +................................................................................ + +6. TECHNICAL SUPPORT & FEEDBACK + + +To obtain technical support, create a WebCase at www.xilinx.com/support. +Questions are routed to a team with expertise using this product. + +Xilinx provides technical support for use of this product when used +according to the guidelines described in the core documentation, and +cannot guarantee timing, functionality, or support of this product for +designs that do not follow specified guidelines. + + +................................................................................ + +7. CORE RELEASE HISTORY + + +Date By Version Description +================================================================================ +06/19/2013 Xilinx, Inc. 3.6(Rev3) ISE 14.6 support +10/16/2012 Xilinx, Inc. 3.6(Rev2) ISE 14.3 support +07/25/2012 Xilinx, Inc. 3.6 ISE 14.2 support +04/24/2012 Xilinx, Inc. 3.5 ISE 14.1 support +01/18/2012 Xilinx, Inc. 3.3 ISE 13.4 support +06/22/2011 Xilinx, Inc. 3.2 ISE 13.2 support +03/01/2011 Xilinx, Inc. 3.1 ISE 13.1 support +12/14/2010 Xilinx, Inc. 1.8 ISE 12.4 support +09/21/2010 Xilinx, Inc. 1.7 ISE 12.3 support +07/23/2010 Xilinx, Inc. 1.6 ISE 12.2 support +04/19/2010 Xilinx, Inc. 1.5 ISE 12.1 support +12/02/2009 Xilinx, Inc. 1.4 ISE 11.4 support +09/16/2009 Xilinx, Inc. 1.3 ISE 11.3 support +06/24/2009 Xilinx, Inc. 1.2 ISE 11.2 support +04/24/2009 Xilinx, Inc. 1.1 Initial release; 11.1 support +================================================================================ + +................................................................................ + +8. LEGAL DISCLAIMER + +(c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. + +This file contains confidential and proprietary information +of Xilinx, Inc. and is protected under U.S. and +international copyright and other intellectual property +laws. + +DISCLAIMER +This disclaimer is not a license and does not grant any +rights to the materials distributed herewith. Except as +otherwise provided in a valid license issued to you by +Xilinx, and to the maximum extent permitted by applicable +law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +(2) Xilinx shall not be liable (whether in contract or tort, +including negligence, or under any other theory of +liability) for any loss or damage of any kind or nature +related to, arising under or in connection with these +materials, including for any direct, or any indirect, +special, incidental, or consequential loss or damage +(including loss of data, profits, goodwill, or any type of +loss or damage suffered as a result of any action brought +by a third party) even if such damage or loss was +reasonably foreseeable or Xilinx had been advised of the +possibility of the same. + +CRITICAL APPLICATIONS +Xilinx products are not designed or intended to be fail- +safe, or for use in any application requiring fail-safe +performance, such as life-support or safety devices or +systems, Class III medical devices, nuclear facilities, +applications related to the deployment of airbags, or any +other applications that could lead to death, personal +injury, or severe property or environmental damage +(individually and collectively, "Critical +Applications"). Customer assumes the sole risk and +liability of any use of Xilinx products in Critical +Applications, subject only to applicable laws and +regulations governing limitations on product liability. + +THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +PART OF THIS FILE AT ALL TIMES. + diff --git a/ipcore_dir/lcd_spi_clk/doc/clk_wiz_v3_6_vinfo.html b/ipcore_dir/lcd_spi_clk/doc/clk_wiz_v3_6_vinfo.html new file mode 100644 index 0000000..d6deba0 --- /dev/null +++ b/ipcore_dir/lcd_spi_clk/doc/clk_wiz_v3_6_vinfo.html @@ -0,0 +1,195 @@ + + +clk_wiz_v3_6_vinfo + + + + + + diff --git a/ipcore_dir/lcd_spi_clk/doc/pg065_clk_wiz.pdf b/ipcore_dir/lcd_spi_clk/doc/pg065_clk_wiz.pdf new file mode 100644 index 0000000000000000000000000000000000000000..a7daa6089fb11fc95652ecbb7534db7fa9e8b245 GIT binary patch literal 42657 zcma&N1$5oYmMvtl}c-_IajSJ4Ux$TiO@3Au^^D`>`u-iz%nrrG7wtnnIUj-(My_I8tU4bx*8e~ zGSW*DGP45NnCN8)nE>>{gv?9;1}1vx&jQ8I0%le=dND$ELI4{xAtNh5lZOYv(9+M)h1i9dMTA)a%xuCy7Iq;veqnY70VW|~K^`t< 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index 0000000..f979bce --- /dev/null +++ b/ipcore_dir/lcd_spi_clk/example_design/lcd_spi_clk_exdes.ucf @@ -0,0 +1,59 @@ +# file: lcd_spi_clk_exdes.ucf +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# Input clock periods. These duplicate the values entered for the +# input clocks. You can use these to time your system +#---------------------------------------------------------------- +NET "CLK_IN1" TNM_NET = "CLK_IN1"; +TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 20.0 ns HIGH 50% INPUT_JITTER 200.0ps; + + +# FALSE PATH constraints +PIN "COUNTER_RESET" TIG; + diff --git a/ipcore_dir/lcd_spi_clk/example_design/lcd_spi_clk_exdes.v b/ipcore_dir/lcd_spi_clk/example_design/lcd_spi_clk_exdes.v new file mode 100755 index 0000000..e034060 --- /dev/null +++ b/ipcore_dir/lcd_spi_clk/example_design/lcd_spi_clk_exdes.v @@ -0,0 +1,169 @@ +// file: lcd_spi_clk_exdes.v +// +// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// + +//---------------------------------------------------------------------------- +// Clocking wizard example design +//---------------------------------------------------------------------------- +// This example design instantiates the created clocking network, where each +// output clock drives a counter. The high bit of each counter is ported. +//---------------------------------------------------------------------------- + +`timescale 1ps/1ps + +module lcd_spi_clk_exdes + #( + parameter TCQ = 100 + ) + (// Clock in ports + input CLK_IN1, + // Reset that only drives logic in example design + input COUNTER_RESET, + output [2:1] CLK_OUT, + // High bits of counters driven by clocks + output [2:1] COUNT + ); + + // Parameters for the counters + //------------------------------- + // Counter width + localparam C_W = 16; + localparam NUM_C = 2; + genvar count_gen; + // Create reset for the counters + wire reset_int = COUNTER_RESET; + + reg [NUM_C:1] rst_sync; + reg [NUM_C:1] rst_sync_int; + reg [NUM_C:1] rst_sync_int1; + reg [NUM_C:1] rst_sync_int2; + + + // Declare the clocks and counters + wire [NUM_C:1] clk_int; + wire [NUM_C:1] clk_n; + wire [NUM_C:1] clk; + reg [C_W-1:0] counter [NUM_C:1]; + + // Instantiation of the clocking network + //-------------------------------------- + lcd_spi_clk clknetwork + (// Clock in ports + .clk_in (CLK_IN1), + // Clock out ports + .clk_fout (clk_int[1]), + .clk_nout (clk_int[2])); + +genvar clk_out_pins; + +generate + for (clk_out_pins = 1; clk_out_pins <= NUM_C; clk_out_pins = clk_out_pins + 1) + begin: gen_outclk_oddr + assign clk_n[clk_out_pins] = ~clk[clk_out_pins]; + + ODDR2 clkout_oddr + (.Q (CLK_OUT[clk_out_pins]), + .C0 (clk[clk_out_pins]), + .C1 (clk_n[clk_out_pins]), + .CE (1'b1), + .D0 (1'b1), + .D1 (1'b0), + .R (1'b0), + .S (1'b0)); + end +endgenerate + + // Connect the output clocks to the design + //----------------------------------------- + assign clk[1] = clk_int[1]; + assign clk[2] = clk_int[2]; + + + // Reset synchronizer + //----------------------------------- + generate for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin: counters_1 + always @(posedge reset_int or posedge clk[count_gen]) begin + if (reset_int) begin + rst_sync[count_gen] <= 1'b1; + rst_sync_int[count_gen]<= 1'b1; + rst_sync_int1[count_gen]<= 1'b1; + rst_sync_int2[count_gen]<= 1'b1; + end + else begin + rst_sync[count_gen] <= 1'b0; + rst_sync_int[count_gen] <= rst_sync[count_gen]; + rst_sync_int1[count_gen] <= rst_sync_int[count_gen]; + rst_sync_int2[count_gen] <= rst_sync_int1[count_gen]; + end + end + end + endgenerate + + + // Output clock sampling + //----------------------------------- + generate for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin: counters + + always @(posedge clk[count_gen] or posedge rst_sync_int2[count_gen]) begin + if (rst_sync_int2[count_gen]) begin + counter[count_gen] <= #TCQ { C_W { 1'b 0 } }; + end else begin + counter[count_gen] <= #TCQ counter[count_gen] + 1'b 1; + end + end + // alias the high bit of each counter to the corresponding + // bit in the output bus + assign COUNT[count_gen] = counter[count_gen][C_W-1]; + end + endgenerate + + + + + +endmodule diff --git a/ipcore_dir/lcd_spi_clk/example_design/lcd_spi_clk_exdes.xdc b/ipcore_dir/lcd_spi_clk/example_design/lcd_spi_clk_exdes.xdc new file mode 100755 index 0000000..85d7e7c --- /dev/null +++ b/ipcore_dir/lcd_spi_clk/example_design/lcd_spi_clk_exdes.xdc @@ -0,0 +1,68 @@ +# file: lcd_spi_clk_exdes.xdc +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# Input clock periods. These duplicate the values entered for the +# input clocks. You can use these to time your system +#---------------------------------------------------------------- +create_clock -name CLK_IN1 -period 20.0 [get_ports CLK_IN1] +set_propagated_clock CLK_IN1 +set_input_jitter CLK_IN1 0.2 + +# FALSE PATH constraint added on COUNTER_RESET +set_false_path -from [get_ports "COUNTER_RESET"] + +# Derived clock periods. These are commented out because they are +# automatically propogated by the tools +# However, if you'd like to use them for module level testing, you +# can copy them into your module level timing checks +#----------------------------------------------------------------- + +#----------------------------------------------------------------- + +#----------------------------------------------------------------- diff --git a/ipcore_dir/lcd_spi_clk/implement/implement.bat b/ipcore_dir/lcd_spi_clk/implement/implement.bat new file mode 100755 index 0000000..b6bb1e8 --- /dev/null +++ b/ipcore_dir/lcd_spi_clk/implement/implement.bat @@ -0,0 +1,90 @@ +REM file: implement.bat +REM +REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +REM +REM This file contains confidential and proprietary information +REM of Xilinx, Inc. and is protected under U.S. and +REM international copyright and other intellectual property +REM laws. +REM +REM DISCLAIMER +REM This disclaimer is not a license and does not grant any +REM rights to the materials distributed herewith. Except as +REM otherwise provided in a valid license issued to you by +REM Xilinx, and to the maximum extent permitted by applicable +REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +REM (2) Xilinx shall not be liable (whether in contract or tort, +REM including negligence, or under any other theory of +REM liability) for any loss or damage of any kind or nature +REM related to, arising under or in connection with these +REM materials, including for any direct, or any indirect, +REM special, incidental, or consequential loss or damage +REM (including loss of data, profits, goodwill, or any type of +REM loss or damage suffered as a result of any action brought +REM by a third party) even if such damage or loss was +REM reasonably foreseeable or Xilinx had been advised of the +REM possibility of the same. +REM +REM CRITICAL APPLICATIONS +REM Xilinx products are not designed or intended to be fail- +REM safe, or for use in any application requiring fail-safe +REM performance, such as life-support or safety devices or +REM systems, Class III medical devices, nuclear facilities, +REM applications related to the deployment of airbags, or any +REM other applications that could lead to death, personal +REM injury, or severe property or environmental damage +REM (individually and collectively, "Critical +REM Applications"). Customer assumes the sole risk and +REM liability of any use of Xilinx products in Critical +REM Applications, subject only to applicable laws and +REM regulations governing limitations on product liability. +REM +REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +REM PART OF THIS FILE AT ALL TIMES. +REM + +REM ----------------------------------------------------------------------------- +REM Script to synthesize and implement the RTL provided for the clocking wizard +REM ----------------------------------------------------------------------------- + +REM Clean up the results directory +rmdir /S /Q results +mkdir results + +REM Copy unisim_comp.v file to results directory +copy %XILINX%\verilog\src\iSE\unisim_comp.v .\results\ + +REM Synthesize the Verilog Wrapper Files +echo 'Synthesizing Clocking Wizard design with XST' +xst -ifn xst.scr +move lcd_spi_clk_exdes.ngc results\ + +REM Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +copy ..\example_design\lcd_spi_clk_exdes.ucf results\ + +cd results + +echo 'Running ngdbuild' +ngdbuild -uc lcd_spi_clk_exdes.ucf lcd_spi_clk_exdes + +echo 'Running map' +map -timing -pr b lcd_spi_clk_exdes -o mapped.ncd + +echo 'Running par' +par -w mapped.ncd routed mapped.pcf + +echo 'Running trce' +trce -e 10 routed -o routed mapped.pcf + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level model for the clocking wizard example design' +netgen -ofmt verilog -sim -sdf_anno false -tm lcd_spi_clk_exdes -w routed.ncd routed.v +cd .. + diff --git a/ipcore_dir/lcd_spi_clk/implement/implement.sh b/ipcore_dir/lcd_spi_clk/implement/implement.sh new file mode 100755 index 0000000..a90b83c --- /dev/null +++ b/ipcore_dir/lcd_spi_clk/implement/implement.sh @@ -0,0 +1,91 @@ +#!/bin/sh +# file: implement.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +#----------------------------------------------------------------------------- +# Script to synthesize and implement the RTL provided for the clocking wizard +#----------------------------------------------------------------------------- + +# Clean up the results directory +rm -rf results +mkdir results + +# Copy unisim_comp.v file to results directory +cp $XILINX/verilog/src/iSE/unisim_comp.v ./results/ + +# Synthesize the Verilog Wrapper Files +echo 'Synthesizing Clocking Wizard design with XST' +xst -ifn xst.scr +mv lcd_spi_clk_exdes.ngc results/ + +# Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +cp ../example_design/lcd_spi_clk_exdes.ucf results/ + +cd results + +echo 'Running ngdbuild' +ngdbuild -uc lcd_spi_clk_exdes.ucf lcd_spi_clk_exdes + +echo 'Running map' +map -timing lcd_spi_clk_exdes -o mapped.ncd + +echo 'Running par' +par -w mapped.ncd routed mapped.pcf + +echo 'Running trce' +trce -e 10 routed -o routed mapped.pcf + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level model for the clocking wizard example design' +netgen -ofmt verilog -sim -sdf_anno false -tm lcd_spi_clk_exdes -w routed.ncd routed.v + +cd .. diff --git a/ipcore_dir/lcd_spi_clk/implement/planAhead_ise.bat b/ipcore_dir/lcd_spi_clk/implement/planAhead_ise.bat new file mode 100755 index 0000000..8ac7718 --- /dev/null +++ b/ipcore_dir/lcd_spi_clk/implement/planAhead_ise.bat @@ -0,0 +1,58 @@ +REM file: planAhead_ise.bat +REM +REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +REM +REM This file contains confidential and proprietary information +REM of Xilinx, Inc. and is protected under U.S. and +REM international copyright and other intellectual property +REM laws. +REM +REM DISCLAIMER +REM This disclaimer is not a license and does not grant any +REM rights to the materials distributed herewith. Except as +REM otherwise provided in a valid license issued to you by +REM Xilinx, and to the maximum extent permitted by applicable +REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +REM (2) Xilinx shall not be liable (whether in contract or tort, +REM including negligence, or under any other theory of +REM liability) for any loss or damage of any kind or nature +REM related to, arising under or in connection with these +REM materials, including for any direct, or any indirect, +REM special, incidental, or consequential loss or damage +REM (including loss of data, profits, goodwill, or any type of +REM loss or damage suffered as a result of any action brought +REM by a third party) even if such damage or loss was +REM reasonably foreseeable or Xilinx had been advised of the +REM possibility of the same. +REM +REM CRITICAL APPLICATIONS +REM Xilinx products are not designed or intended to be fail- +REM safe, or for use in any application requiring fail-safe +REM performance, such as life-support or safety devices or +REM systems, Class III medical devices, nuclear facilities, +REM applications related to the deployment of airbags, or any +REM other applications that could lead to death, personal +REM injury, or severe property or environmental damage +REM (individually and collectively, "Critical +REM Applications"). Customer assumes the sole risk and +REM liability of any use of Xilinx products in Critical +REM Applications, subject only to applicable laws and +REM regulations governing limitations on product liability. +REM +REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +REM PART OF THIS FILE AT ALL TIMES. +REM + +REM----------------------------------------------------------------------------- +REM Script to synthesize and implement the RTL provided for the clocking wizard +REM----------------------------------------------------------------------------- + +del \f results +mkdir results +cd results + +planAhead -mode batch -source ..\planAhead_ise.tcl diff --git a/ipcore_dir/lcd_spi_clk/implement/planAhead_ise.sh b/ipcore_dir/lcd_spi_clk/implement/planAhead_ise.sh new file mode 100755 index 0000000..6c8c837 --- /dev/null +++ b/ipcore_dir/lcd_spi_clk/implement/planAhead_ise.sh @@ -0,0 +1,59 @@ +#!/bin/sh +# file: planAhead_ise.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +#----------------------------------------------------------------------------- +# Script to synthesize and implement the RTL provided for the clocking wizard +#----------------------------------------------------------------------------- + +rm -rf results +mkdir results +cd results + +planAhead -mode batch -source ../planAhead_ise.tcl diff --git a/ipcore_dir/lcd_spi_clk/implement/planAhead_ise.tcl b/ipcore_dir/lcd_spi_clk/implement/planAhead_ise.tcl new file mode 100755 index 0000000..69f66c4 --- /dev/null +++ b/ipcore_dir/lcd_spi_clk/implement/planAhead_ise.tcl @@ -0,0 +1,78 @@ +# file: planAhead_ise.tcl +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +set projDir [file dirname [info script]] +set projName lcd_spi_clk +set topName lcd_spi_clk_exdes +set device xc6slx9tqg144-2 + +create_project $projName $projDir/results/$projName -part $device + +set_property design_mode RTL [get_filesets sources_1] + +## Source files +#set verilogSources [glob $srcDir/*.v] +import_files -fileset [get_filesets sources_1] -force -norecurse ../../example_design/lcd_spi_clk_exdes.v +import_files -fileset [get_filesets sources_1] -force -norecurse ../../../lcd_spi_clk.v + + +#UCF file +import_files -fileset [get_filesets constrs_1] -force -norecurse ../../example_design/lcd_spi_clk_exdes.ucf + +set_property top $topName [get_property srcset [current_run]] + +launch_runs -runs synth_1 +wait_on_run synth_1 + +set_property add_step Bitgen [get_runs impl_1] +launch_runs -runs impl_1 +wait_on_run impl_1 + + + diff --git a/ipcore_dir/lcd_spi_clk/implement/planAhead_rdn.bat b/ipcore_dir/lcd_spi_clk/implement/planAhead_rdn.bat new file mode 100755 index 0000000..42273f5 --- /dev/null +++ b/ipcore_dir/lcd_spi_clk/implement/planAhead_rdn.bat @@ -0,0 +1,58 @@ +REM file: planAhead_rdn.sh +REM +REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +REM +REM This file contains confidential and proprietary information +REM of Xilinx, Inc. and is protected under U.S. and +REM international copyright and other intellectual property +REM laws. +REM +REM DISCLAIMER +REM This disclaimer is not a license and does not grant any +REM rights to the materials distributed herewith. Except as +REM otherwise provided in a valid license issued to you by +REM Xilinx, and to the maximum extent permitted by applicable +REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +REM (2) Xilinx shall not be liable (whether in contract or tort, +REM including negligence, or under any other theory of +REM liability) for any loss or damage of any kind or nature +REM related to, arising under or in connection with these +REM materials, including for any direct, or any indirect, +REM special, incidental, or consequential loss or damage +REM (including loss of data, profits, goodwill, or any type of +REM loss or damage suffered as a result of any action brought +REM by a third party) even if such damage or loss was +REM reasonably foreseeable or Xilinx had been advised of the +REM possibility of the same. +REM +REM CRITICAL APPLICATIONS +REM Xilinx products are not designed or intended to be fail- +REM safe, or for use in any application requiring fail-safe +REM performance, such as life-support or safety devices or +REM systems, Class III medical devices, nuclear facilities, +REM applications related to the deployment of airbags, or any +REM other applications that could lead to death, personal +REM injury, or severe property or environmental damage +REM (individually and collectively, "Critical +REM Applications"). Customer assumes the sole risk and +REM liability of any use of Xilinx products in Critical +REM Applications, subject only to applicable laws and +REM regulations governing limitations on product liability. +REM +REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +REM PART OF THIS FILE AT ALL TIMES. +REM + +REM----------------------------------------------------------------------------- +REM Script to synthesize and implement the RTL provided for the XADC wizard +REM----------------------------------------------------------------------------- + +del \f results +mkdir results +cd results + +planAhead -mode batch -source ..\planAhead_rdn.tcl diff --git a/ipcore_dir/lcd_spi_clk/implement/planAhead_rdn.sh b/ipcore_dir/lcd_spi_clk/implement/planAhead_rdn.sh new file mode 100755 index 0000000..f4c1472 --- /dev/null +++ b/ipcore_dir/lcd_spi_clk/implement/planAhead_rdn.sh @@ -0,0 +1,57 @@ +#!/bin/sh +# file: planAhead_rdn.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +#----------------------------------------------------------------------------- +# Script to synthesize and implement the RTL provided for the XADC wizard +#----------------------------------------------------------------------------- +rm -rf results +mkdir results +cd results +planAhead -mode batch -source ../planAhead_rdn.tcl diff --git a/ipcore_dir/lcd_spi_clk/implement/planAhead_rdn.tcl b/ipcore_dir/lcd_spi_clk/implement/planAhead_rdn.tcl new file mode 100755 index 0000000..5e0bbc9 --- /dev/null +++ b/ipcore_dir/lcd_spi_clk/implement/planAhead_rdn.tcl @@ -0,0 +1,69 @@ +# file : planAhead_rdn.tcl +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +set device xc6slx9tqg144-2 +set projName lcd_spi_clk +set design lcd_spi_clk +set projDir [file dirname [info script]] +create_project $projName $projDir/results/$projName -part $device -force +set_property design_mode RTL [current_fileset -srcset] +set top_module lcd_spi_clk_exdes +set_property top lcd_spi_clk_exdes [get_property srcset [current_run]] +add_files -norecurse {../../../lcd_spi_clk.v} +add_files -norecurse {../../example_design/lcd_spi_clk_exdes.v} +import_files -fileset [get_filesets constrs_1 ] -force -norecurse {../../example_design/lcd_spi_clk_exdes.xdc} +synth_design +opt_design +place_design +route_design +write_sdf -rename_top_module lcd_spi_clk_exdes -file routed.sdf +write_verilog -nolib -mode timesim -sdf_anno false -rename_top_module lcd_spi_clk_exdes -file routed.v +report_timing -nworst 30 -path_type full -file routed.twr +report_drc -file report.drc +write_bitstream -bitgen_options {-g UnconstrainedPins:Allow} -file routed.bit diff --git a/ipcore_dir/lcd_spi_clk/implement/xst.prj b/ipcore_dir/lcd_spi_clk/implement/xst.prj new file mode 100755 index 0000000..c567a63 --- /dev/null +++ b/ipcore_dir/lcd_spi_clk/implement/xst.prj @@ -0,0 +1,2 @@ +verilog work ../../lcd_spi_clk.v +verilog work ../example_design/lcd_spi_clk_exdes.v diff --git a/ipcore_dir/lcd_spi_clk/implement/xst.scr b/ipcore_dir/lcd_spi_clk/implement/xst.scr new file mode 100755 index 0000000..38abb82 --- /dev/null +++ b/ipcore_dir/lcd_spi_clk/implement/xst.scr @@ -0,0 +1,9 @@ +run +-ifmt MIXED +-top lcd_spi_clk_exdes +-p xc6slx9-tqg144-2 +-ifn xst.prj +-ofn lcd_spi_clk_exdes +-keep_hierarchy soft +-equivalent_register_removal no +-max_fanout 65535 diff --git a/ipcore_dir/lcd_spi_clk/simulation/functional/simcmds.tcl b/ipcore_dir/lcd_spi_clk/simulation/functional/simcmds.tcl new file mode 100755 index 0000000..9dc9880 --- /dev/null +++ b/ipcore_dir/lcd_spi_clk/simulation/functional/simcmds.tcl @@ -0,0 +1,8 @@ +# file: simcmds.tcl + +# create the simulation script +vcd dumpfile isim.vcd +vcd dumpvars -m /lcd_spi_clk_tb -l 0 +wave add / +run 50000ns +quit diff --git a/ipcore_dir/lcd_spi_clk/simulation/functional/simulate_isim.bat b/ipcore_dir/lcd_spi_clk/simulation/functional/simulate_isim.bat new file mode 100755 index 0000000..18b9b59 --- /dev/null +++ b/ipcore_dir/lcd_spi_clk/simulation/functional/simulate_isim.bat @@ -0,0 +1,59 @@ +REM file: simulate_isim.bat +REM +REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +REM +REM This file contains confidential and proprietary information +REM of Xilinx, Inc. and is protected under U.S. and +REM international copyright and other intellectual property +REM laws. +REM +REM DISCLAIMER +REM This disclaimer is not a license and does not grant any +REM rights to the materials distributed herewith. Except as +REM otherwise provided in a valid license issued to you by +REM Xilinx, and to the maximum extent permitted by applicable +REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +REM (2) Xilinx shall not be liable (whether in contract or tort, +REM including negligence, or under any other theory of +REM liability) for any loss or damage of any kind or nature +REM related to, arising under or in connection with these +REM materials, including for any direct, or any indirect, +REM special, incidental, or consequential loss or damage +REM (including loss of data, profits, goodwill, or any type of +REM loss or damage suffered as a result of any action brought +REM by a third party) even if such damage or loss was +REM reasonably foreseeable or Xilinx had been advised of the +REM possibility of the same. +REM +REM CRITICAL APPLICATIONS +REM Xilinx products are not designed or intended to be fail- +REM safe, or for use in any application requiring fail-safe +REM performance, such as life-support or safety devices or +REM systems, Class III medical devices, nuclear facilities, +REM applications related to the deployment of airbags, or any +REM other applications that could lead to death, personal +REM injury, or severe property or environmental damage +REM (individually and collectively, "Critical +REM Applications"). Customer assumes the sole risk and +REM liability of any use of Xilinx products in Critical +REM Applications, subject only to applicable laws and +REM regulations governing limitations on product liability. +REM +REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +REM PART OF THIS FILE AT ALL TIMES. +REM + +vlogcomp -work work %XILINX%\verilog\src\glbl.v +vlogcomp -work work ..\..\..\lcd_spi_clk.v +vlogcomp -work work ..\..\example_design\lcd_spi_clk_exdes.v +vlogcomp -work work ..\lcd_spi_clk_tb.v + +REM compile the project +fuse work.lcd_spi_clk_tb work.glbl -L unisims_ver -o lcd_spi_clk_isim.exe + +REM run the simulation script +.\lcd_spi_clk_isim.exe -gui -tclbatch simcmds.tcl diff --git a/ipcore_dir/lcd_spi_clk/simulation/functional/simulate_isim.sh b/ipcore_dir/lcd_spi_clk/simulation/functional/simulate_isim.sh new file mode 100755 index 0000000..b814df2 --- /dev/null +++ b/ipcore_dir/lcd_spi_clk/simulation/functional/simulate_isim.sh @@ -0,0 +1,61 @@ +# file: simulate_isim.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# lin64 +# create the project +vlogcomp -work work ${XILINX}/verilog/src/glbl.v +vlogcomp -work work ../../../lcd_spi_clk.v +vlogcomp -work work ../../example_design/lcd_spi_clk_exdes.v +vlogcomp -work work ../lcd_spi_clk_tb.v + +# compile the project +fuse work.lcd_spi_clk_tb work.glbl -L unisims_ver -o lcd_spi_clk_isim.exe + +# run the simulation script +./lcd_spi_clk_isim.exe -gui -tclbatch simcmds.tcl diff --git a/ipcore_dir/lcd_spi_clk/simulation/functional/simulate_mti.bat b/ipcore_dir/lcd_spi_clk/simulation/functional/simulate_mti.bat new file mode 100755 index 0000000..7ff51f8 --- /dev/null +++ b/ipcore_dir/lcd_spi_clk/simulation/functional/simulate_mti.bat @@ -0,0 +1,61 @@ +REM file: simulate_mti.bat +REM +REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +REM +REM This file contains confidential and proprietary information +REM of Xilinx, Inc. and is protected under U.S. and +REM international copyright and other intellectual property +REM laws. +REM +REM DISCLAIMER +REM This disclaimer is not a license and does not grant any +REM rights to the materials distributed herewith. Except as +REM otherwise provided in a valid license issued to you by +REM Xilinx, and to the maximum extent permitted by applicable +REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +REM (2) Xilinx shall not be liable (whether in contract or tort, +REM including negligence, or under any other theory of +REM liability) for any loss or damage of any kind or nature +REM related to, arising under or in connection with these +REM materials, including for any direct, or any indirect, +REM special, incidental, or consequential loss or damage +REM (including loss of data, profits, goodwill, or any type of +REM loss or damage suffered as a result of any action brought +REM by a third party) even if such damage or loss was +REM reasonably foreseeable or Xilinx had been advised of the +REM possibility of the same. +REM +REM CRITICAL APPLICATIONS +REM Xilinx products are not designed or intended to be fail- +REM safe, or for use in any application requiring fail-safe +REM performance, such as life-support or safety devices or +REM systems, Class III medical devices, nuclear facilities, +REM applications related to the deployment of airbags, or any +REM other applications that could lead to death, personal +REM injury, or severe property or environmental damage +REM (individually and collectively, "Critical +REM Applications"). Customer assumes the sole risk and +REM liability of any use of Xilinx products in Critical +REM Applications, subject only to applicable laws and +REM regulations governing limitations on product liability. +REM +REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +REM PART OF THIS FILE AT ALL TIMES. +REM + +REM set up the working directory +vlib work + +REM compile all of the files +vlog -work work %XILINX%\verilog\src\glbl.v +vlog -work work ..\..\..\lcd_spi_clk.v +vlog -work work ..\..\example_design\lcd_spi_clk_exdes.v +vlog -work work ..\lcd_spi_clk_tb.v + +REM run the simulation +vsim -c -t ps -voptargs="+acc" -L secureip -L unisims_ver work.lcd_spi_clk_tb work.glbl + diff --git a/ipcore_dir/lcd_spi_clk/simulation/functional/simulate_mti.do b/ipcore_dir/lcd_spi_clk/simulation/functional/simulate_mti.do new file mode 100755 index 0000000..b84dc1d --- /dev/null +++ b/ipcore_dir/lcd_spi_clk/simulation/functional/simulate_mti.do @@ -0,0 +1,65 @@ +# file: simulate_mti.do +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# set up the working directory +set work work +vlib work + +# compile all of the files +vlog -work work $env(XILINX)/verilog/src/glbl.v +vlog -work work ../../../lcd_spi_clk.v +vlog -work work ../../example_design/lcd_spi_clk_exdes.v +vlog -work work ../lcd_spi_clk_tb.v + +# run the simulation +vsim -t ps -voptargs="+acc" -L unisims_ver work.lcd_spi_clk_tb work.glbl +do wave.do +log lcd_spi_clk_tb/dut/counter +log -r /* +run 50000ns diff --git a/ipcore_dir/lcd_spi_clk/simulation/functional/simulate_mti.sh b/ipcore_dir/lcd_spi_clk/simulation/functional/simulate_mti.sh new file mode 100755 index 0000000..731e6ec --- /dev/null +++ b/ipcore_dir/lcd_spi_clk/simulation/functional/simulate_mti.sh @@ -0,0 +1,61 @@ +#/bin/sh +# file: simulate_mti.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# +# set up the working directory +set work work +vlib work + +# compile all of the files +vlog -work work $XILINX/verilog/src/glbl.v +vlog -work work ../../../lcd_spi_clk.v +vlog -work work ../../example_design/lcd_spi_clk_exdes.v +vlog -work work ../lcd_spi_clk_tb.v + +# run the simulation +vsim -c -t ps -voptargs="+acc" -L secureip -L unisims_ver work.lcd_spi_clk_tb work.glbl diff --git a/ipcore_dir/lcd_spi_clk/simulation/functional/simulate_ncsim.sh b/ipcore_dir/lcd_spi_clk/simulation/functional/simulate_ncsim.sh new file mode 100755 index 0000000..68acaf5 --- /dev/null +++ b/ipcore_dir/lcd_spi_clk/simulation/functional/simulate_ncsim.sh @@ -0,0 +1,62 @@ +#/bin/sh +# file: simulate_ncsim.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# set up the working directory +mkdir work + +# compile all of the files +ncvlog -work work ${XILINX}/verilog/src/glbl.v +ncvlog -work work ../../../lcd_spi_clk.v +ncvlog -work work ../../example_design/lcd_spi_clk_exdes.v +ncvlog -work work ../lcd_spi_clk_tb.v + +# elaborate and run the simulation +ncelab -work work -access +wc work.lcd_spi_clk_tb work.glbl +ncsim -input "@database -open -shm nc; probe -create -database nc -all -depth all; probe dut.counter; run 50000ns; exit" work.lcd_spi_clk_tb diff --git a/ipcore_dir/lcd_spi_clk/simulation/functional/simulate_vcs.sh b/ipcore_dir/lcd_spi_clk/simulation/functional/simulate_vcs.sh new file mode 100755 index 0000000..e5d3a1b --- /dev/null +++ b/ipcore_dir/lcd_spi_clk/simulation/functional/simulate_vcs.sh @@ -0,0 +1,72 @@ +#!/bin/sh +# file: simulate_vcs.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# remove old files +rm -rf simv* csrc DVEfiles AN.DB + +# compile all of the files +# Note that -sverilog is not strictly required- You can +# remove the -sverilog if you change the type of the +# localparam for the periods in the testbench file to +# [63:0] from time +vlogan -sverilog \ + ${XILINX}/verilog/src/glbl.v \ + ../../../lcd_spi_clk.v \ + ../../example_design/lcd_spi_clk_exdes.v \ + ../lcd_spi_clk_tb.v + +# prepare the simulation +vcs +vcs+lic+wait -debug lcd_spi_clk_tb glbl + +# run the simulation +./simv -ucli -i ucli_commands.key + +# launch the viewer +dve -vpd vcdplus.vpd -session vcs_session.tcl diff --git a/ipcore_dir/lcd_spi_clk/simulation/functional/ucli_commands.key b/ipcore_dir/lcd_spi_clk/simulation/functional/ucli_commands.key new file mode 100755 index 0000000..8152888 --- /dev/null +++ b/ipcore_dir/lcd_spi_clk/simulation/functional/ucli_commands.key @@ -0,0 +1,5 @@ +call {$vcdpluson} +call {$vcdplusmemon(lcd_spi_clk_tb.dut.counter)} +run +call {$vcdplusclose} +quit diff --git a/ipcore_dir/lcd_spi_clk/simulation/functional/vcs_session.tcl b/ipcore_dir/lcd_spi_clk/simulation/functional/vcs_session.tcl new file mode 100755 index 0000000..83de97a --- /dev/null +++ b/ipcore_dir/lcd_spi_clk/simulation/functional/vcs_session.tcl @@ -0,0 +1,15 @@ +gui_open_window Wave +gui_sg_create lcd_spi_clk_group +gui_list_add_group -id Wave.1 {lcd_spi_clk_group} +gui_sg_addsignal -group lcd_spi_clk_group {lcd_spi_clk_tb.test_phase} +gui_set_radix -radix {ascii} -signals {lcd_spi_clk_tb.test_phase} +gui_sg_addsignal -group lcd_spi_clk_group {{Input_clocks}} -divider +gui_sg_addsignal -group lcd_spi_clk_group {lcd_spi_clk_tb.CLK_IN1} +gui_sg_addsignal -group lcd_spi_clk_group {{Output_clocks}} -divider +gui_sg_addsignal -group lcd_spi_clk_group {lcd_spi_clk_tb.dut.clk} +gui_list_expand -id Wave.1 lcd_spi_clk_tb.dut.clk +gui_sg_addsignal -group lcd_spi_clk_group {{Counters}} -divider +gui_sg_addsignal -group lcd_spi_clk_group {lcd_spi_clk_tb.COUNT} +gui_sg_addsignal -group lcd_spi_clk_group {lcd_spi_clk_tb.dut.counter} +gui_list_expand -id Wave.1 lcd_spi_clk_tb.dut.counter +gui_zoom -window Wave.1 -full diff --git a/ipcore_dir/lcd_spi_clk/simulation/functional/wave.do b/ipcore_dir/lcd_spi_clk/simulation/functional/wave.do new file mode 100755 index 0000000..bb731af --- /dev/null +++ b/ipcore_dir/lcd_spi_clk/simulation/functional/wave.do @@ -0,0 +1,57 @@ +# file: wave.do +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +add wave -noupdate -format Literal -radix ascii /lcd_spi_clk_tb/test_phase +add wave -noupdate -divider {Input clocks} +add wave -noupdate -format Logic /lcd_spi_clk_tb/CLK_IN1 +add wave -noupdate -divider {Output clocks} +add wave -noupdate -format Literal -expand /lcd_spi_clk_tb/dut/clk +add wave -noupdate -divider Counters +add wave -noupdate -format Literal -radix hexadecimal /lcd_spi_clk_tb/COUNT +add wave -noupdate -format Literal -radix hexadecimal -expand /lcd_spi_clk_tb/dut/counter diff --git a/ipcore_dir/lcd_spi_clk/simulation/functional/wave.sv b/ipcore_dir/lcd_spi_clk/simulation/functional/wave.sv new file mode 100755 index 0000000..f4a6296 --- /dev/null +++ b/ipcore_dir/lcd_spi_clk/simulation/functional/wave.sv @@ -0,0 +1,111 @@ +# file: wave.sv +# +# (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# +# Get the windows set up +# +if {[catch {window new WatchList -name "Design Browser 1" -geometry 1054x819+536+322}] != ""} { + window geometry "Design Browser 1" 1054x819+536+322 +} +window target "Design Browser 1" on +browser using {Design Browser 1} +browser set \ + -scope nc::lcd_spi_clk_tb +browser yview see nc::lcd_spi_clk_tb +browser timecontrol set -lock 0 + +if {[catch {window new WaveWindow -name "Waveform 1" -geometry 1010x600+0+541}] != ""} { + window geometry "Waveform 1" 1010x600+0+541 +} +window target "Waveform 1" on +waveform using {Waveform 1} +waveform sidebar visibility partial +waveform set \ + -primarycursor TimeA \ + -signalnames name \ + -signalwidth 175 \ + -units ns \ + -valuewidth 75 +cursor set -using TimeA -time 0 +waveform baseline set -time 0 +waveform xview limits 0 20000n + +# +# Define signal groups +# +catch {group new -name {Output clocks} -overlay 0} +catch {group new -name {Status/control} -overlay 0} +catch {group new -name {Counters} -overlay 0} + +set id [waveform add -signals [list {nc::lcd_spi_clk_tb.CLK_IN1}]] + +group using {Output clocks} +group set -overlay 0 +group set -comment {} +group clear 0 end + +group insert \ + {lcd_spi_clk_tb.dut.clk[1]} \ + {lcd_spi_clk_tb.dut.clk[2]} +group using {Counters} +group set -overlay 0 +group set -comment {} +group clear 0 end + +group insert \ + {lcd_spi_clk_tb.dut.counter[1]} \ + {lcd_spi_clk_tb.dut.counter[2]} + +set id [waveform add -signals [list {nc::lcd_spi_clk_tb.COUNT} ]] + +set id [waveform add -signals [list {nc::lcd_spi_clk_tb.test_phase} ]] +waveform format $id -radix %a + +set groupId [waveform add -groups {{Input clocks}}] +set groupId [waveform add -groups {{Output clocks}}] +set groupId [waveform add -groups {{Status/control}}] +set groupId [waveform add -groups {{Counters}}] diff --git a/ipcore_dir/lcd_spi_clk/simulation/lcd_spi_clk_tb.v b/ipcore_dir/lcd_spi_clk/simulation/lcd_spi_clk_tb.v new file mode 100755 index 0000000..3005c07 --- /dev/null +++ b/ipcore_dir/lcd_spi_clk/simulation/lcd_spi_clk_tb.v @@ -0,0 +1,133 @@ +// file: lcd_spi_clk_tb.v +// +// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// + +//---------------------------------------------------------------------------- +// Clocking wizard demonstration testbench +//---------------------------------------------------------------------------- +// This demonstration testbench instantiates the example design for the +// clocking wizard. Input clocks are toggled, which cause the clocking +// network to lock and the counters to increment. +//---------------------------------------------------------------------------- + +`timescale 1ps/1ps + +`define wait_lock @(posedge dut.clknetwork.dcm_sp_inst.LOCKED) + +module lcd_spi_clk_tb (); + + // Clock to Q delay of 100ps + localparam TCQ = 100; + + + // timescale is 1ps/1ps + localparam ONE_NS = 1000; + localparam PHASE_ERR_MARGIN = 100; // 100ps + // how many cycles to run + localparam COUNT_PHASE = 1024; + // we'll be using the period in many locations + localparam time PER1 = 20.0*ONE_NS; + localparam time PER1_1 = PER1/2; + localparam time PER1_2 = PER1 - PER1/2; + + // Declare the input clock signals + reg CLK_IN1 = 1; + + // The high bits of the sampling counters + wire [2:1] COUNT; + reg COUNTER_RESET = 0; +wire [2:1] CLK_OUT; +//Freq Check using the M & D values setting and actual Frequency generated + + + // Input clock generation + //------------------------------------ + always begin + CLK_IN1 = #PER1_1 ~CLK_IN1; + CLK_IN1 = #PER1_2 ~CLK_IN1; + end + + // Test sequence + reg [15*8-1:0] test_phase = ""; + initial begin + // Set up any display statements using time to be readable + $timeformat(-12, 2, "ps", 10); + COUNTER_RESET = 0; + test_phase = "wait lock"; + `wait_lock; + #(PER1*6); + COUNTER_RESET = 1; + #(PER1*20) + COUNTER_RESET = 0; + + test_phase = "counting"; + #(PER1*COUNT_PHASE); + + $display("SIMULATION PASSED"); + $display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1); + $finish; + end + + // Instantiation of the example design containing the clock + // network and sampling counters + //--------------------------------------------------------- + lcd_spi_clk_exdes + #( + .TCQ (TCQ) + ) dut + (// Clock in ports + .CLK_IN1 (CLK_IN1), + // Reset for logic in example design + .COUNTER_RESET (COUNTER_RESET), + .CLK_OUT (CLK_OUT), + // High bits of the counters + .COUNT (COUNT)); + +// Freq Check + +endmodule diff --git a/ipcore_dir/lcd_spi_clk/simulation/timing/lcd_spi_clk_tb.v b/ipcore_dir/lcd_spi_clk/simulation/timing/lcd_spi_clk_tb.v new file mode 100755 index 0000000..e7bcef7 --- /dev/null +++ b/ipcore_dir/lcd_spi_clk/simulation/timing/lcd_spi_clk_tb.v @@ -0,0 +1,136 @@ +// file: lcd_spi_clk_tb.v +// +// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// + +//---------------------------------------------------------------------------- +// Clocking wizard demonstration testbench +//---------------------------------------------------------------------------- +// This demonstration testbench instantiates the example design for the +// clocking wizard. Input clocks are toggled, which cause the clocking +// network to lock and the counters to increment. +//---------------------------------------------------------------------------- + +`timescale 1ps/1ps + + +module lcd_spi_clk_tb (); + + // Clock to Q delay of 100ps + localparam TCQ = 100; + + + // timescale is 1ps/1ps + localparam ONE_NS = 1000; + localparam PHASE_ERR_MARGIN = 100; // 100ps + // how many cycles to run + localparam COUNT_PHASE = 1024; + // we'll be using the period in many locations + localparam time PER1 = 20.0*ONE_NS; + localparam time PER1_1 = PER1/2; + localparam time PER1_2 = PER1 - PER1/2; + + // Declare the input clock signals + reg CLK_IN1 = 1; + + // The high bits of the sampling counters + wire [2:1] COUNT; + reg COUNTER_RESET = 0; +wire [2:1] CLK_OUT; +//Freq Check using the M & D values setting and actual Frequency generated + + reg [13:0] timeout_counter = 14'b00000000000000; + + // Input clock generation + //------------------------------------ + always begin + CLK_IN1 = #PER1_1 ~CLK_IN1; + CLK_IN1 = #PER1_2 ~CLK_IN1; + end + + // Test sequence + reg [15*8-1:0] test_phase = ""; + initial begin + // Set up any display statements using time to be readable + $timeformat(-12, 2, "ps", 10); + $display ("Timing checks are not valid"); + COUNTER_RESET = 0; + test_phase = "wait lock"; + #(PER1*50); + #(PER1*6); + COUNTER_RESET = 1; + #(PER1*19.5) + COUNTER_RESET = 0; + #(PER1*1) + $display ("Timing checks are valid"); + test_phase = "counting"; + #(PER1*COUNT_PHASE); + + $display("SIMULATION PASSED"); + $display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1); + $finish; + end + + + + // Instantiation of the example design containing the clock + // network and sampling counters + //--------------------------------------------------------- + lcd_spi_clk_exdes + dut + (// Clock in ports + .CLK_IN1 (CLK_IN1), + // Reset for logic in example design + .COUNTER_RESET (COUNTER_RESET), + .CLK_OUT (CLK_OUT), + // High bits of the counters + .COUNT (COUNT)); + + +// Freq Check + +endmodule diff --git a/ipcore_dir/lcd_spi_clk/simulation/timing/sdf_cmd_file b/ipcore_dir/lcd_spi_clk/simulation/timing/sdf_cmd_file new file mode 100755 index 0000000..4456690 --- /dev/null +++ b/ipcore_dir/lcd_spi_clk/simulation/timing/sdf_cmd_file @@ -0,0 +1,2 @@ +COMPILED_SDF_FILE = "../../implement/results/routed.sdf.X", +SCOPE = lcd_spi_clk_tb.dut; diff --git a/ipcore_dir/lcd_spi_clk/simulation/timing/simcmds.tcl b/ipcore_dir/lcd_spi_clk/simulation/timing/simcmds.tcl new file mode 100755 index 0000000..acb2601 --- /dev/null +++ b/ipcore_dir/lcd_spi_clk/simulation/timing/simcmds.tcl @@ -0,0 +1,9 @@ +# file: simcmds.tcl + +# create the simulation script +vcd dumpfile isim.vcd +vcd dumpvars -m /lcd_spi_clk_tb -l 0 +wave add / +run 50000ns +quit + diff --git a/ipcore_dir/lcd_spi_clk/simulation/timing/simulate_isim.sh b/ipcore_dir/lcd_spi_clk/simulation/timing/simulate_isim.sh new file mode 100755 index 0000000..e65ad16 --- /dev/null +++ b/ipcore_dir/lcd_spi_clk/simulation/timing/simulate_isim.sh @@ -0,0 +1,62 @@ +# file: simulate_isim.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# create the project +vlogcomp -work work ${XILINX}/verilog/src/glbl.v +vlogcomp -work work ../../implement/results/routed.v +vlogcomp -work work lcd_spi_clk_tb.v + +# compile the project +fuse work.lcd_spi_clk_tb work.glbl -L secureip -L simprims_ver -o lcd_spi_clk_isim.exe + +# run the simulation script +./lcd_spi_clk_isim.exe -tclbatch simcmds.tcl -sdfmax /lcd_spi_clk_tb/dut=../../implement/results/routed.sdf + +# run the simulation script +#./lcd_spi_clk_isim.exe -gui -tclbatch simcmds.tcl diff --git a/ipcore_dir/lcd_spi_clk/simulation/timing/simulate_mti.bat b/ipcore_dir/lcd_spi_clk/simulation/timing/simulate_mti.bat new file mode 100755 index 0000000..6ef5f23 --- /dev/null +++ b/ipcore_dir/lcd_spi_clk/simulation/timing/simulate_mti.bat @@ -0,0 +1,59 @@ +REM file: simulate_mti.bat +REM +REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +REM +REM This file contains confidential and proprietary information +REM of Xilinx, Inc. and is protected under U.S. and +REM international copyright and other intellectual property +REM laws. +REM +REM DISCLAIMER +REM This disclaimer is not a license and does not grant any +REM rights to the materials distributed herewith. Except as +REM otherwise provided in a valid license issued to you by +REM Xilinx, and to the maximum extent permitted by applicable +REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +REM (2) Xilinx shall not be liable (whether in contract or tort, +REM including negligence, or under any other theory of +REM liability) for any loss or damage of any kind or nature +REM related to, arising under or in connection with these +REM materials, including for any direct, or any indirect, +REM special, incidental, or consequential loss or damage +REM (including loss of data, profits, goodwill, or any type of +REM loss or damage suffered as a result of any action brought +REM by a third party) even if such damage or loss was +REM reasonably foreseeable or Xilinx had been advised of the +REM possibility of the same. +REM +REM CRITICAL APPLICATIONS +REM Xilinx products are not designed or intended to be fail- +REM safe, or for use in any application requiring fail-safe +REM performance, such as life-support or safety devices or +REM systems, Class III medical devices, nuclear facilities, +REM applications related to the deployment of airbags, or any +REM other applications that could lead to death, personal +REM injury, or severe property or environmental damage +REM (individually and collectively, "Critical +REM Applications"). Customer assumes the sole risk and +REM liability of any use of Xilinx products in Critical +REM Applications, subject only to applicable laws and +REM regulations governing limitations on product liability. +REM +REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +REM PART OF THIS FILE AT ALL TIMES. +REM +# set up the working directory +set work work +vlib work + +REM compile all of the files +vlog -work work %XILINX%\verilog\src\glbl.v +vlog -work work ..\..\implement\results\routed.v +vlog -work work lcd_spi_clk_tb.v + +REM run the simulation +vsim -c -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax lcd_spi_clk_tb\dut=..\..\implement\results\routed.sdf +no_notifier work.lcd_spi_clk_tb work.glbl diff --git a/ipcore_dir/lcd_spi_clk/simulation/timing/simulate_mti.do b/ipcore_dir/lcd_spi_clk/simulation/timing/simulate_mti.do new file mode 100755 index 0000000..1003853 --- /dev/null +++ b/ipcore_dir/lcd_spi_clk/simulation/timing/simulate_mti.do @@ -0,0 +1,65 @@ +# file: simulate_mti.do +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# set up the working directory +set work work +vlib work + +# compile all of the files +vlog -work work $env(XILINX)/verilog/src/glbl.v +vlog -work work ../../implement/results/routed.v +vlog -work work lcd_spi_clk_tb.v + +# run the simulation +vsim -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax lcd_spi_clk_tb/dut=../../implement/results/routed.sdf +no_notifier work.lcd_spi_clk_tb work.glbl +#do wave.do +#log -r /* +run 50000ns + + diff --git a/ipcore_dir/lcd_spi_clk/simulation/timing/simulate_mti.sh b/ipcore_dir/lcd_spi_clk/simulation/timing/simulate_mti.sh new file mode 100755 index 0000000..f391aa8 --- /dev/null +++ b/ipcore_dir/lcd_spi_clk/simulation/timing/simulate_mti.sh @@ -0,0 +1,61 @@ +#/bin/sh +# file: simulate_mti.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# set up the working directory +set work work +vlib work + +# compile all of the files +vlog -work work $XILINX/verilog/src/glbl.v +vlog -work work ../../implement/results/routed.v +vlog -work work lcd_spi_clk_tb.v + +# run the simulation +vsim -c -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax lcd_spi_clk_tb/dut=../../implement/results/routed.sdf +no_notifier work.lcd_spi_clk_tb work.glbl diff --git a/ipcore_dir/lcd_spi_clk/simulation/timing/simulate_ncsim.sh b/ipcore_dir/lcd_spi_clk/simulation/timing/simulate_ncsim.sh new file mode 100755 index 0000000..73b3aed --- /dev/null +++ b/ipcore_dir/lcd_spi_clk/simulation/timing/simulate_ncsim.sh @@ -0,0 +1,64 @@ +#!/bin/sh +# file: simulate_ncsim.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# set up the working directory +mkdir work + +# compile all of the files +ncvlog -work work ${XILINX}/verilog/src/glbl.v +ncvlog -work work ../../implement/results/routed.v +ncvlog -work work lcd_spi_clk_tb.v + +# elaborate and run the simulation +ncsdfc ../../implement/results/routed.sdf + +ncelab -work work -access +wc -pulse_r 10 -nonotifier work.lcd_spi_clk_tb work.glbl -sdf_cmd_file sdf_cmd_file +ncsim -input "@database -open -shm nc; probe -create -database nc -all -depth all; run 50000ns; exit" work.lcd_spi_clk_tb + diff --git a/ipcore_dir/lcd_spi_clk/simulation/timing/simulate_vcs.sh b/ipcore_dir/lcd_spi_clk/simulation/timing/simulate_vcs.sh new file mode 100755 index 0000000..3a6b647 --- /dev/null +++ b/ipcore_dir/lcd_spi_clk/simulation/timing/simulate_vcs.sh @@ -0,0 +1,72 @@ +#!/bin/sh +# file: simulate_vcs.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# remove old files +rm -rf simv* csrc DVEfiles AN.DB + +# compile all of the files +# Note that -sverilog is not strictly required- You can +# remove the -sverilog if you change the type of the +# localparam for the periods in the testbench file to +# [63:0] from time + vlogan -sverilog \ + lcd_spi_clk_tb.v \ + ../../implement/results/routed.v + + +# prepare the simulation +vcs -sdf max:lcd_spi_clk_exdes:../../implement/results/routed.sdf +v2k -y $XILINX/verilog/src/simprims \ + +libext+.v -debug lcd_spi_clk_tb.v ../../implement/results/routed.v + +# run the simulation +./simv -ucli -i ucli_commands.key + +# launch the viewer +#dve -vpd vcdplus.vpd -session vcs_session.tcl diff --git a/ipcore_dir/lcd_spi_clk/simulation/timing/ucli_commands.key b/ipcore_dir/lcd_spi_clk/simulation/timing/ucli_commands.key new file mode 100755 index 0000000..0548d17 --- /dev/null +++ b/ipcore_dir/lcd_spi_clk/simulation/timing/ucli_commands.key @@ -0,0 +1,5 @@ + +call {$vcdpluson} +run 50000ns +call {$vcdplusclose} +quit diff --git a/ipcore_dir/lcd_spi_clk/simulation/timing/vcs_session.tcl b/ipcore_dir/lcd_spi_clk/simulation/timing/vcs_session.tcl new file mode 100755 index 0000000..1438f6b --- /dev/null +++ b/ipcore_dir/lcd_spi_clk/simulation/timing/vcs_session.tcl @@ -0,0 +1 @@ +gui_open_window Wave diff --git a/ipcore_dir/lcd_spi_clk/simulation/timing/wave.do b/ipcore_dir/lcd_spi_clk/simulation/timing/wave.do new file mode 100755 index 0000000..c8119c0 --- /dev/null +++ b/ipcore_dir/lcd_spi_clk/simulation/timing/wave.do @@ -0,0 +1,70 @@ +# file: wave.do +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /lcd_spi_clk_tb/CLK_IN1 +add wave -noupdate /lcd_spi_clk_tb/COUNT +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {3223025 ps} 0} +configure wave -namecolwidth 238 +configure wave -valuecolwidth 107 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ps +update +WaveRestoreZoom {0 ps} {74848022 ps} diff --git a/ipcore_dir/lcd_spi_clk_flist.txt b/ipcore_dir/lcd_spi_clk_flist.txt new file mode 100644 index 0000000..6e3d771 --- /dev/null +++ b/ipcore_dir/lcd_spi_clk_flist.txt @@ -0,0 +1,54 @@ +# Output products list for +_xmsgs/pn_parser.xmsgs +lcd_spi_clk/clk_wiz_v3_6_readme.txt +lcd_spi_clk/doc/clk_wiz_v3_6_readme.txt +lcd_spi_clk/doc/clk_wiz_v3_6_vinfo.html +lcd_spi_clk/doc/pg065_clk_wiz.pdf +lcd_spi_clk/example_design/lcd_spi_clk_exdes.ucf +lcd_spi_clk/example_design/lcd_spi_clk_exdes.v +lcd_spi_clk/example_design/lcd_spi_clk_exdes.xdc +lcd_spi_clk/implement/implement.bat +lcd_spi_clk/implement/implement.sh +lcd_spi_clk/implement/planAhead_ise.bat +lcd_spi_clk/implement/planAhead_ise.sh +lcd_spi_clk/implement/planAhead_ise.tcl +lcd_spi_clk/implement/planAhead_rdn.bat +lcd_spi_clk/implement/planAhead_rdn.sh +lcd_spi_clk/implement/planAhead_rdn.tcl +lcd_spi_clk/implement/xst.prj +lcd_spi_clk/implement/xst.scr +lcd_spi_clk/simulation/functional/simcmds.tcl +lcd_spi_clk/simulation/functional/simulate_isim.bat +lcd_spi_clk/simulation/functional/simulate_isim.sh +lcd_spi_clk/simulation/functional/simulate_mti.bat +lcd_spi_clk/simulation/functional/simulate_mti.do +lcd_spi_clk/simulation/functional/simulate_mti.sh +lcd_spi_clk/simulation/functional/simulate_ncsim.sh +lcd_spi_clk/simulation/functional/simulate_vcs.sh +lcd_spi_clk/simulation/functional/ucli_commands.key +lcd_spi_clk/simulation/functional/vcs_session.tcl +lcd_spi_clk/simulation/functional/wave.do +lcd_spi_clk/simulation/functional/wave.sv +lcd_spi_clk/simulation/lcd_spi_clk_tb.v +lcd_spi_clk/simulation/timing/lcd_spi_clk_tb.v +lcd_spi_clk/simulation/timing/sdf_cmd_file +lcd_spi_clk/simulation/timing/simcmds.tcl +lcd_spi_clk/simulation/timing/simulate_isim.sh +lcd_spi_clk/simulation/timing/simulate_mti.bat +lcd_spi_clk/simulation/timing/simulate_mti.do +lcd_spi_clk/simulation/timing/simulate_mti.sh +lcd_spi_clk/simulation/timing/simulate_ncsim.sh +lcd_spi_clk/simulation/timing/simulate_vcs.sh +lcd_spi_clk/simulation/timing/ucli_commands.key +lcd_spi_clk/simulation/timing/vcs_session.tcl +lcd_spi_clk/simulation/timing/wave.do +lcd_spi_clk.asy +lcd_spi_clk.gise +lcd_spi_clk.ucf +lcd_spi_clk.v +lcd_spi_clk.veo +lcd_spi_clk.xco +lcd_spi_clk.xdc +lcd_spi_clk.xise +lcd_spi_clk_flist.txt +lcd_spi_clk_xmdf.tcl diff --git a/ipcore_dir/lcd_spi_clk_xmdf.tcl b/ipcore_dir/lcd_spi_clk_xmdf.tcl new file mode 100755 index 0000000..6b255d0 --- /dev/null +++ b/ipcore_dir/lcd_spi_clk_xmdf.tcl @@ -0,0 +1,140 @@ +# The package naming convention is _xmdf +package provide lcd_spi_clk_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::lcd_spi_clk_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::lcd_spi_clk_xmdf::xmdfInit { instance } { +# Variable containg name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name lcd_spi_clk +} +# ::lcd_spi_clk_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::lcd_spi_clk_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be magically +# available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path lcd_spi_clk/clk_wiz_readme.txt +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path lcd_spi_clk/doc/clk_wiz_ds709.pdf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path lcd_spi_clk/doc/clk_wiz_gsg521.pdf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path lcd_spi_clk/implement/implement.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path lcd_spi_clk/implement/implement.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path lcd_spi_clk/implement/xst.prj +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path lcd_spi_clk/implement/xst.scr +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path lcd_spi_clk/simulation/lcd_spi_clk_tb.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path lcd_spi_clk/simulation/functional/simcmds.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path lcd_spi_clk/simulation/functional/simulate_isim.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path lcd_spi_clk/simulation/functional/simulate_mti.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path lcd_spi_clk/simulation/functional/simulate_ncsim.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path lcd_spi_clk/simulation/functional/simulate_vcs.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path lcd_spi_clk/simulation/functional/ucli_commands.key +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path lcd_spi_clk/simulation/functional/vcs_session.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path lcd_spi_clk/simulation/functional/wave.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path lcd_spi_clk/simulation/functional/wave.sv +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path lcd_spi_clk.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path lcd_spi_clk.ejp +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path lcd_spi_clk.ucf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ucf +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path lcd_spi_clk.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path lcd_spi_clk.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path lcd_spi_clk.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path lcd_spi_clk_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module lcd_spi_clk +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/iseconfig/Mojo-Base.projectmgr b/iseconfig/Mojo-Base.projectmgr new file mode 100644 index 0000000..52b44ba --- /dev/null +++ b/iseconfig/Mojo-Base.projectmgr @@ -0,0 +1,94 @@ + + + + + + + + + 2 + /avr_interface |home|justin|workspace|Mojo-Tutorials|Mojo-Base|src|avr_interface.v + + + mojo_top (/home/dormando/p/mojo/verilog-raycaster/src/mojo_top.v) + + 27 + 0 + 000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000001c7000000020000000000000000000000000200000064ffffffff000000810000000300000002000001c70000000100000003000000000000000100000003 + true + mojo_top (/home/dormando/p/mojo/verilog-raycaster/src/mojo_top.v) + + + + 1 + Configure Target Device + Design Utilities + Implement Design/Map + Implement Design/Place & Route + Implement Design/Translate + Synthesize - XST + User Constraints + + + + + 0 + 0 + 000000ff0000000000000001000000010000000000000000000000000000000000000000000000014c000000010000000100000000000000000000000064ffffffff0000008100000000000000010000014c0000000100000000 + false + + + + + 1 + + + 0 + 0 + 000000ff00000000000000010000000000000000010000000000000000000000000000000000000891000000040101000100000000000000000000000064ffffffff000000810000000000000004000000770000000100000000000000c50000000100000000000000790000000100000000000006dc0000000100000000 + false + avr_interface.v + + + + 1 + work + + + 0 + 0 + 000000ff0000000000000001000000000000000001000000000000000000000000000000000000011a000000010001000100000000000000000000000064ffffffff0000008100000000000000010000011a0000000100000000 + false + work + + 000000ff0000000000000002000001380000011b01000000040100000002 + Implementation + + + 1 + Design Utilities + + + + + 0 + 0 + 000000ff000000000000000100000001000000000000000000000000000000000000000000000000f6000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f60000000100000000 + false + + + + + 1 + User Constraints + + + + + 0 + 0 + 000000ff000000000000000100000001000000000000000000000000000000000000000000000000f6000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f60000000100000000 + false + + + diff --git a/iseconfig/mojo_top.xreport b/iseconfig/mojo_top.xreport new file mode 100644 index 0000000..9a71da7 --- /dev/null +++ b/iseconfig/mojo_top.xreport @@ -0,0 +1,215 @@ + + +
+ 2018-12-31T15:51:13 + mojo_top + 2013-04-16T10:54:27 + /home/dormando/p/mojo/verilog-raycaster/iseconfig/mojo_top.xreport + /home/dormando/p/mojo/verilog-raycaster/syn/ + 2012-11-08T12:38:20 + false +
+ + + + + + + + + + + + + + + + + + + + + + + + diff --git a/scripts/RULER b/scripts/RULER new file mode 100644 index 0000000..a86a0b2 --- /dev/null +++ b/scripts/RULER @@ -0,0 +1,7 @@ +because shifting fixed point math variables is hard on the brain. + +Q16 . 16 +16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 . 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 +REAL: +31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16.15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 + diff --git a/scripts/lcdserial.pl b/scripts/lcdserial.pl new file mode 100755 index 0000000..f8ec6d1 --- /dev/null +++ b/scripts/lcdserial.pl @@ -0,0 +1,198 @@ +#!/usr/bin/perl + +use warnings; +use strict; +use Device::SerialPort; + +my $port = Device::SerialPort->new("/dev/ttyACM0"); + +$port->baudrate(9600); +#$port->baudrate(115200); +$port->databits(8); +$port->parity("none"); +$port->stopbits(1); +# timeout stuff +$port->read_char_time(0); +$port->read_const_time(1000); + +# 0x36 , 1, 0b11001000, // Memory Access Control (orig: 0x48) +my $iblob = qq{0xEF, 3, 0x03, 0x80, 0x02, +0xCF, 3, 0x00, 0xC1, 0x30, +0xED, 4, 0x64, 0x03, 0x12, 0x81, +0xE8, 3, 0x85, 0x00, 0x78, +0xCB, 5, 0x39, 0x2C, 0x00, 0x34, 0x02, +0xF7, 1, 0x20, +0xEA, 2, 0x00, 0x00, +0xC0 , 1, 0x23, // Power control VRH[5:0] 0x23: 0b100011 4.60V ? +0xC1 , 1, 0x10, // Power control SAP[2:0];BT[3:0] 0b10000 +0xC5 , 2, 0x3e, 0x28, // VCM control 0b111110 0b101000 +0xC7, 1, 0x86, // VCM control2 +0x36 , 1, 0b11001000, // Memory Access Control (orig: 0x48) +0x37, 1, 0x00, // Vertical scroll zero +0x3A, 1, 0x55, // pixel format +0xB1, 2, 0x00, 0x18, +0xB6, 3, 0x08, 0x82, 0x27, // Display Function Control +0xF2, 1, 0x00, // 3Gamma Function Disable +0x26, 1, 0x01, // Gamma curve selected +0xE0, 15, 0x0F, 0x31, 0x2B, 0x0C, 0x0E, 0x08, 0x4E, 0xF1, 0x37, 0x07, 0x10, 0x03, 0x0E, 0x09, 0x00, // set gamma +0xE1, 15, 0x00, 0x0E, 0x14, 0x03, 0x11, 0x07, 0x31, 0xC1, 0x48, 0x08, 0x0F, 0x0C, 0x31, 0x36, 0x0F, // set gamma +0x11, 0x80, // Exit Sleep +0x29, 0x80, // Display on +}; + +my $BLACK = 0x0000; +my $MAROON = 0x7800; + +$iblob =~ s!//.*!!g; +$iblob =~ s/,/ /g; +$iblob =~ s/[ ]+/ /g; +#print $iblob; +open(my $dump, "> lcd_output") or die "meh: $!"; + +if ($ARGV[0]) { + mad_ctl(); +} else { + reset_lcd(); + init(); + write_bytes(); +} +exit; + +sub mad_ctl { + my $cmd = 0b10000101; + my $cbyte = 0x36; # MADCTL + my $packed = pack('CSLL', $cmd, 500, 0, $cbyte); + $port->write($packed); + $cbyte = 0b00001000; # BGR + $cbyte |= 0b00000000; # MX (column address order) + $packed = pack('CSLL', $cmd, 500, 0, $cbyte + 256); + $port->write($packed); + select undef, undef, undef, 0.1; +} + +# reset sequence. +sub reset_lcd { + print "resetting...\n"; + my $cmd = 0b00000101; + my $packed = pack('CSL', $cmd, 0, 1); + $port->write($packed); + select undef, undef, undef, 0.250; + my $junk = $port->read(255); + $packed = pack('CSL', $cmd, 0, 0); + $port->write($packed); + select undef, undef, undef, 0.250; + $junk = $port->read(255); + $packed = pack('CSL', $cmd, 0, 1); + $port->write($packed); + select undef, undef, undef, 0.250; + $junk = $port->read(255); + print "done reset.\n"; +} + +sub init { + for my $l (split /\n/, $iblob) { + my @d = split /\s+/, $l; + my $cbyte = eval(shift @d); + my $bcnt = shift @d; + + # register interface takes cmd with 9th bit low, data is all 9th bit high. + my $cmd = 0b10000101; + my $packed = pack('CSLL', $cmd, 0, 0, $cbyte); + print $dump $packed; + $port->write($packed); + select undef, undef, undef, 0.01; + + # now write out the arguments. + for (@d) { + my $byte = eval($_); # holy dangerous, batman :P + $byte += 256; # DCX to high for data. + my $packed = pack('CSLL', $cmd, 0, 0, $byte); + $port->write($packed); + print $dump $packed; + select undef, undef, undef, 0.01; + } + if ($bcnt eq '0x80') { + select undef, undef, undef, 0.25; + } + } +} + +#define ILI9341_CASET 0x2A +#define ILI9341_PASET 0x2B +#define ILI9341_RAMWR 0x2C + +# 0x28 off +# 0x29 on +sub power_cycle { + my $cmd = 0b10000101; + my $cbyte; + + # off + $cbyte = 0x28; + my $packed = pack('CSLL', $cmd, 0, 0, $cbyte); + $port->write($packed); + sleep 3; + $cbyte = 0x29; + $packed = pack('CSLL', $cmd, 0, 0, $cbyte); + $port->write($packed); + sleep 1; +} + +sub write_bytes { + print "ca/pa set\n"; + { + my $cmd = 0b10000101; + my $cbyte; + + $cbyte = 0x2A; + my $x0 = 0; + my $x1 = 240; + my $y0 = 0; + my $y1 = 320; + my $packed = pack('CSL', $cmd, 9); + $packed .= pack('L', $cbyte); + $packed .= pack('L', 256); + $packed .= pack('L', $x0 + 256); + $packed .= pack('L', 256); + $packed .= pack('L', ($x1 & 0x00FF) + 256); + $cbyte = 0x2B; + $packed .= pack('L', $cbyte); + $packed .= pack('L', 256); + $packed .= pack('L', $y0 + 256); + $packed .= pack('L', ($y1 >> 8) + 256); + $packed .= pack('L', ($y1 & 0x00FF) + 256); + $port->write($packed); + } + return; + + # Randomly try writing a bunch... + print "shove pixel\n"; + { + my $cmd = 0b10000101; + my $cbyte = 0x2C; + my $packed = pack('CSLL', $cmd, 500, 0, $cbyte); + $port->write($packed); + } + return; + for (1 .. 500) { + my $packed = pack('L', 256); + $packed .= pack('L', 256); + $port->write($packed); + } + sleep 1; + { + my $cmd = 0b10000101; + my $cbyte = 0x00; # NOP + my $packed = pack('CSLL', $cmd, 0, 0, $cbyte); + $port->write($packed); + } +} + +close($dump); + + +#my $cmd = 0b10000101; +#my $packed = pack('CSLL', $cmd, 0, 0, $leds); +#$port->write($packed); + + diff --git a/scripts/serialray.pl b/scripts/serialray.pl new file mode 100755 index 0000000..f0d9e14 --- /dev/null +++ b/scripts/serialray.pl @@ -0,0 +1,75 @@ +#!/usr/bin/perl + +use warnings; +use strict; +use Device::SerialPort; +use Data::Dumper qw/Dumper/; + +$|++; +my $port = Device::SerialPort->new("/dev/ttyACM0"); + +$port->baudrate(9600); +#$port->baudrate(115200); +#$port->baudrate(256000); +$port->databits(8); +$port->parity("none"); +$port->stopbits(1); +# timeout stuff +$port->read_char_time(0); +$port->read_const_time(1000); + +open(my $sout_line, "> sout_line") or die "meh: $!"; +$sout_line->autoflush(1); + +my $leds = $ARGV[0]; +my $map_x = $ARGV[1]; +my $map_y = $ARGV[2]; +my $turn = $ARGV[3]; +# show how many CPU cycles the frame took. +my $cycles = $ARGV[4] || 0; +# Blank LED's. +my $cmd = 0b10000000; +my $packed = pack('CSLL', $cmd, 0, 0, $leds); +$port->write($packed); +select undef, undef, undef, 0.1; + +print "casting rays...\n"; +cast_rays(); + +sub reduce { + my $f = int($_[0] * 2**8); + $f = -3200 if ($f < -32000); + $f = 32000 if ($f > 32000); + return $f; +} + +sub cast_rays { + my $cmd = 0b11000100; + my $map_pos = pack('ss', int($map_x * 2**8), int($map_y * 2**8)); + my $packed = pack('CSL', $cmd, 1, 0); + $port->write($packed . $map_pos . pack('L', $turn)); + return unless $cycles; + # Should be more or less instantly done, but sleep a bit anyway. + select undef, undef, undef, 0.1; + $cmd = 0b00000100; + $packed = pack('CSL', $cmd, 0, 0); + $port->write($packed); + { + my $buf = ''; + my $timeout = 2; + while ($timeout) { + my ($count, $got) = $port->read(255); + if ($count > 0) { + $buf .= $got; + last if length($buf) >= 4; + } else { + $timeout--; + } + print STDERR "cycle $count\n"; + } + print "cycle count: ", unpack('L', $buf), "\n"; + open(my $dump, "> cycle_output") or die "meh: $!"; + print $dump $buf; + close($dump); + } +} diff --git a/scripts/set_sprite.pl b/scripts/set_sprite.pl new file mode 100755 index 0000000..6f450de --- /dev/null +++ b/scripts/set_sprite.pl @@ -0,0 +1,30 @@ +#!/usr/bin/perl +# sets a sprite position. + +use warnings; +use strict; +use Device::SerialPort; +use Data::Dumper qw/Dumper/; + +$|++; +my $port = Device::SerialPort->new("/dev/ttyACM0"); + +#$port->baudrate(9600); +#$port->baudrate(115200); +$port->baudrate(256000); +$port->databits(8); +$port->parity("none"); +$port->stopbits(1); +# timeout stuff +$port->read_char_time(0); +$port->read_const_time(1000); + +my $map_x = $ARGV[0] or die "moo"; +my $map_y = $ARGV[1] or die "boo"; + +my $cmd = 0b10000110; +my $map_pos = pack('ss', int($map_x * 2**8), int($map_y * 2**8)); +# FIXME: hard coded texture ID + sprite id (also pick a position :P) +my $packed = pack('CScccc', $cmd, 0, 0, 8, 8, 0); +$port->write($packed . $map_pos); + diff --git a/scripts/sout_line b/scripts/sout_line new file mode 100644 index 0000000..e69de29 diff --git a/scripts/texloader.pl b/scripts/texloader.pl new file mode 100755 index 0000000..5eac0de --- /dev/null +++ b/scripts/texloader.pl @@ -0,0 +1,67 @@ +#!/usr/bin/perl + +use warnings; +use strict; +use Device::SerialPort; + +my $port = Device::SerialPort->new("/dev/ttyACM0"); + +#$port->baudrate(9600); +$port->baudrate(115200); +$port->databits(8); +$port->parity("none"); +$port->stopbits(1); +# timeout stuff +$port->read_char_time(0); +$port->read_const_time(1000); + +my $offset = 0; +my $poffset = 0; + +for my $file (@ARGV) { + load_tex($file, $offset); + my $pal = $file; + $pal =~ s/\.flat/.pal/; + load_pal($pal, $poffset); + $offset += 1024; + $poffset += 15; + select undef, undef, undef, 0.25; +} + +sub load_pal { + my $file = shift; + my $offset = shift; + print "$file...\n"; + open(my $fh, "<$file") or die "boop: $!"; + my $buf; + my $pbuf; + my $cnt = 0; + while (read($fh, $buf, 2)) { + $pbuf .= $buf . pack('n', 0); + $cnt++; + } + close($fh); + + my $cmd = 0b11000001; + my $packed = pack('CSL', $cmd, $cnt-1, $offset); + $port->write($packed); + $port->write($pbuf); +} + +sub load_tex { + my $file = shift; + my $offset = shift; + print "$file...\n"; + open(my $fh, "<$file") or die "boop: $!"; + my $buf; + my $pbuf; + while (read($fh, $buf, 1)) { + $pbuf .= pack('L', ord($buf)); + } + close($fh); + + my $cmd = 0b11000011; + my $packed = pack('CSL', $cmd, 1023, $offset); + $port->write($packed); + $port->write($pbuf); +} diff --git a/scripts/textureprep.pl b/scripts/textureprep.pl new file mode 100755 index 0000000..87d048d --- /dev/null +++ b/scripts/textureprep.pl @@ -0,0 +1,83 @@ +#!/usr/bin/perl +# parses textures/sprites into flat data loadable by the serial protocol, +# along with palette files for each. +# see: tload.sh and texloader.pl + +use warnings; +use strict; + +use GD; + +my $sdir = $ARGV[0]; +my $odir = $ARGV[1]; +my $sprite = $ARGV[2] || 0; + +opendir(my $dh, $sdir) or die "meh: $!"; +while (readdir($dh)) { + next unless $_ =~ m/\.png$/; + process($_); +} +closedir($dh); + +sub sixteenbit { + my @c = @_; + $c[0] = ($c[0] * 249 + 1024) >> 11; + $c[1] = ($c[1] * 253 + 505) >> 10; + $c[2] = ($c[2] * 249 + 1024) >> 11; + my $bin = pack('s', ($c[0] << 11) | ($c[1] << 5) | $c[2]); + return $bin; +} + +sub process { + my $file = shift; + my $im = GD::Image->newFromPng($sdir . $file, 1); + # 15 colors + alpha channel (always high color). + + my $nim = new GD::Image->newTrueColor(32, 32); + $nim->alphaBlending(0); + $nim->saveAlpha(1); + # we downsample to 32x32x4bit to save block RAM. + $nim->copyResampled($im, 0, 0, 0, 0, 32, 32, 64, 64); + $nim->trueColorToPalette(0, 14); + my $total = $nim->colorsTotal; + # some of the source sprites aren't 64x64 + if ($total == 256 || $im->width != 64 || $im->height != 64) { + print "Skipping: $file: $total\n"; + return; + } + print "$file: $total\n"; + + # Copy color index. + open(my $pal, "> $odir/$file.pal") or die "boop: $!"; + for (0 .. $total-1) { + print $pal sixteenbit($nim->rgb($_)); + } + close($pal); + + my @f; + open(my $flat, "> $odir/$file.flat") or die "boop: $!"; + # the alpha seems to get randomized during "dithering" above. + # in these particular source images the corner is always a transparent + # one, so find that index and re-slot it into our alpha channel number. + my $alpha = $nim->getPixel(0, 0); + for (my $x = 0; $x < $nim->width; $x++) { + for (my $y = 0; $y < $nim->height; $y++) { + my $c = $nim->getPixel($x, $y); + #print $flat $f[$x][$y], " "; + #print $flat $c, " "; + if ($c == $alpha && $sprite) { + # only for sprites! + # keep a consistent alpha channel. + $c = 15; + } + #print "C: $c\n"; + print $flat pack('C', $c); + } + } + + open(my $out, "> $odir/$file") or die "boop: $!"; + binmode $out; + print $out $nim->png; + close($out); + close($flat); +} diff --git a/scripts/tload.sh b/scripts/tload.sh new file mode 100755 index 0000000..7075cb3 --- /dev/null +++ b/scripts/tload.sh @@ -0,0 +1,2 @@ +#!/bin/bash +./texloader.pl tout/tile110.png.flat tout/tile082.png.flat tout/tile084.png.flat tout/tile085.png.flat tout/tile093.png.flat tout/tile096.png.flat tout/tile097.png.flat tout/tile106.png.flat sout/brain.png.flat diff --git a/src/angle.rom b/src/angle.rom new file mode 100644 index 0000000..b0cf1d7 --- /dev/null +++ b/src/angle.rom @@ -0,0 +1,126 @@ + angles[0] = 80'hff_00_00_00_00_00_00_a8_01_83; + angles[1] = 80'hff_01_00_0c_00_08_00_a8_01_83; + angles[2] = 80'hff_02_00_19_00_10_00_a8_01_83; + angles[3] = 80'hff_03_00_26_00_19_00_a7_01_83; + angles[4] = 80'hff_06_00_33_00_21_00_a5_01_83; + angles[5] = 80'hff_09_00_3f_00_2a_00_a3_01_83; + angles[6] = 80'hff_0c_00_4c_00_32_00_a1_01_83; + angles[7] = 80'hff_10_00_58_00_3a_00_9e_01_83; + angles[8] = 80'hff_15_00_64_00_42_00_9b_01_83; + angles[9] = 80'hff_1a_00_6f_00_49_00_97_01_83; + angles[10] = 80'hff_20_00_7b_00_51_00_94_01_83; + angles[11] = 80'hff_27_00_86_00_58_00_8f_01_83; + angles[12] = 80'hff_2e_00_91_00_5f_00_8b_01_83; + angles[13] = 80'hff_35_00_9b_00_66_00_86_01_83; + angles[14] = 80'hff_3d_00_a5_00_6d_00_80_01_83; + angles[15] = 80'hff_46_00_af_00_73_00_7b_01_83; + angles[16] = 80'hff_4f_00_b8_00_79_00_75_01_83; + angles[17] = 80'hff_58_00_c1_00_7f_00_6e_01_83; + angles[18] = 80'hff_62_00_c9_00_84_00_68_01_83; + angles[19] = 80'hff_6d_00_d0_00_89_00_61_01_83; + angles[20] = 80'hff_77_00_d8_00_8e_00_5a_01_83; + angles[21] = 80'hff_82_00_de_00_93_00_53_01_83; + angles[22] = 80'hff_8e_00_e4_00_97_00_4b_01_83; + angles[23] = 80'hff_99_00_ea_00_9a_00_44_01_83; + angles[24] = 80'hff_a5_00_ef_00_9d_00_3c_01_83; + angles[25] = 80'hff_b1_00_f3_00_a0_00_34_01_83; + angles[26] = 80'hff_be_00_f7_00_a3_00_2c_01_83; + angles[27] = 80'hff_ca_00_fa_00_a5_00_23_01_83; + angles[28] = 80'hff_d7_00_fc_00_a6_00_1b_01_83; + angles[29] = 80'hff_e4_00_fe_00_a7_00_13_01_83; + angles[30] = 80'hff_f0_00_ff_00_a8_00_0a_01_83; + angles[31] = 80'hff_fd_00_ff_00_a8_00_02_01_83; + angles[32] = 80'h00_09_00_ff_00_a8_ff_fa_01_83; + angles[33] = 80'h00_16_00_ff_00_a8_ff_f2_01_83; + angles[34] = 80'h00_23_00_fd_00_a7_ff_e9_01_83; + angles[35] = 80'h00_2f_00_fb_00_a5_ff_e1_01_83; + angles[36] = 80'h00_3c_00_f8_00_a4_ff_d9_01_83; + angles[37] = 80'h00_48_00_f5_00_a1_ff_d0_01_83; + angles[38] = 80'h00_55_00_f1_00_9f_ff_c8_01_83; + angles[39] = 80'h00_61_00_ec_00_9c_ff_c0_01_83; + angles[40] = 80'h00_6c_00_e7_00_98_ff_b9_01_83; + angles[41] = 80'h00_78_00_e1_00_95_ff_b1_01_83; + angles[42] = 80'h00_83_00_db_00_90_ff_aa_01_83; + angles[43] = 80'h00_8e_00_d4_00_8c_ff_a2_01_83; + angles[44] = 80'h00_99_00_cd_00_87_ff_9b_01_83; + angles[45] = 80'h00_a3_00_c5_00_82_ff_95_01_83; + angles[46] = 80'h00_ac_00_bc_00_7c_ff_8e_01_83; + angles[47] = 80'h00_b6_00_b3_00_76_ff_88_01_83; + angles[48] = 80'h00_be_00_aa_00_70_ff_82_01_83; + angles[49] = 80'h00_c7_00_a0_00_6a_ff_7d_01_83; + angles[50] = 80'h00_cf_00_96_00_63_ff_78_01_83; + angles[51] = 80'h00_d6_00_8b_00_5c_ff_73_01_83; + angles[52] = 80'h00_dd_00_80_00_55_ff_6f_01_83; + angles[53] = 80'h00_e3_00_75_00_4d_ff_6a_01_83; + angles[54] = 80'h00_e8_00_6a_00_46_ff_67_01_83; + angles[55] = 80'h00_ee_00_5e_00_3e_ff_63_01_83; + angles[56] = 80'h00_f2_00_52_00_36_ff_60_01_83; + angles[57] = 80'h00_f6_00_45_00_2e_ff_5e_01_83; + angles[58] = 80'h00_f9_00_39_00_25_ff_5c_01_83; + angles[59] = 80'h00_fc_00_2c_00_1d_ff_5a_01_83; + angles[60] = 80'h00_fd_00_20_00_15_ff_59_01_83; + angles[61] = 80'h00_ff_00_13_00_0c_ff_58_01_83; + angles[62] = 80'h00_ff_00_06_00_04_ff_58_01_83; + angles[63] = 80'h00_ff_ff_fa_ff_fc_ff_58_01_83; + angles[64] = 80'h00_ff_ff_ed_ff_f4_ff_58_01_83; + angles[65] = 80'h00_fd_ff_e0_ff_eb_ff_59_01_83; + angles[66] = 80'h00_fc_ff_d4_ff_e3_ff_5a_01_83; + angles[67] = 80'h00_f9_ff_c7_ff_db_ff_5c_01_83; + angles[68] = 80'h00_f6_ff_bb_ff_d2_ff_5e_01_83; + angles[69] = 80'h00_f2_ff_ae_ff_ca_ff_60_01_83; + angles[70] = 80'h00_ee_ff_a2_ff_c2_ff_63_01_83; + angles[71] = 80'h00_e8_ff_96_ff_bb_ff_67_01_83; + angles[72] = 80'h00_e3_ff_8b_ff_b3_ff_6a_01_83; + angles[73] = 80'h00_dd_ff_80_ff_ab_ff_6f_01_83; + angles[74] = 80'h00_d6_ff_75_ff_a4_ff_73_01_83; + angles[75] = 80'h00_cf_ff_6a_ff_9d_ff_78_01_83; + angles[76] = 80'h00_c7_ff_60_ff_96_ff_7d_01_83; + angles[77] = 80'h00_be_ff_56_ff_90_ff_82_01_83; + angles[78] = 80'h00_b6_ff_4d_ff_8a_ff_88_01_83; + angles[79] = 80'h00_ac_ff_44_ff_84_ff_8e_01_83; + angles[80] = 80'h00_a3_ff_3b_ff_7e_ff_95_01_83; + angles[81] = 80'h00_99_ff_33_ff_79_ff_9b_01_83; + angles[82] = 80'h00_8e_ff_2c_ff_74_ff_a2_01_83; + angles[83] = 80'h00_83_ff_25_ff_70_ff_aa_01_83; + angles[84] = 80'h00_78_ff_1f_ff_6b_ff_b1_01_83; + angles[85] = 80'h00_6d_ff_19_ff_68_ff_b9_01_83; + angles[86] = 80'h00_61_ff_14_ff_64_ff_c0_01_83; + angles[87] = 80'h00_55_ff_0f_ff_61_ff_c8_01_83; + angles[88] = 80'h00_48_ff_0b_ff_5f_ff_d0_01_83; + angles[89] = 80'h00_3c_ff_08_ff_5c_ff_d9_01_83; + angles[90] = 80'h00_30_ff_05_ff_5b_ff_e1_01_83; + angles[91] = 80'h00_23_ff_03_ff_59_ff_e9_01_83; + angles[92] = 80'h00_16_ff_01_ff_58_ff_f2_01_83; + angles[93] = 80'h00_09_ff_01_ff_58_ff_fa_01_83; + angles[94] = 80'hff_fd_ff_01_ff_58_00_02_01_83; + angles[95] = 80'hff_f0_ff_01_ff_58_00_0a_01_83; + angles[96] = 80'hff_e4_ff_02_ff_59_00_13_01_83; + angles[97] = 80'hff_d7_ff_04_ff_5a_00_1b_01_83; + angles[98] = 80'hff_ca_ff_06_ff_5b_00_23_01_83; + angles[99] = 80'hff_be_ff_09_ff_5d_00_2c_01_83; + angles[100] = 80'hff_b1_ff_0d_ff_60_00_34_01_83; + angles[101] = 80'hff_a5_ff_11_ff_63_00_3c_01_83; + angles[102] = 80'hff_99_ff_16_ff_66_00_44_01_83; + angles[103] = 80'hff_8e_ff_1c_ff_69_00_4b_01_83; + angles[104] = 80'hff_82_ff_22_ff_6d_00_53_01_83; + angles[105] = 80'hff_77_ff_28_ff_72_00_5a_01_83; + angles[106] = 80'hff_6d_ff_2f_ff_77_00_61_01_83; + angles[107] = 80'hff_62_ff_37_ff_7c_00_68_01_83; + angles[108] = 80'hff_58_ff_3f_ff_81_00_6e_01_83; + angles[109] = 80'hff_4f_ff_48_ff_87_00_75_01_83; + angles[110] = 80'hff_46_ff_51_ff_8d_00_7b_01_83; + angles[111] = 80'hff_3d_ff_5b_ff_93_00_80_01_83; + angles[112] = 80'hff_35_ff_65_ff_9a_00_86_01_83; + angles[113] = 80'hff_2e_ff_6f_ff_a1_00_8b_01_83; + angles[114] = 80'hff_27_ff_7a_ff_a8_00_8f_01_83; + angles[115] = 80'hff_20_ff_85_ff_af_00_94_01_83; + angles[116] = 80'hff_1a_ff_91_ff_b7_00_97_01_83; + angles[117] = 80'hff_15_ff_9c_ff_be_00_9b_01_83; + angles[118] = 80'hff_10_ff_a8_ff_c6_00_9e_01_83; + angles[119] = 80'hff_0c_ff_b4_ff_ce_00_a1_01_83; + angles[120] = 80'hff_09_ff_c1_ff_d6_00_a3_01_83; + angles[121] = 80'hff_06_ff_cd_ff_df_00_a5_01_83; + angles[122] = 80'hff_03_ff_da_ff_e7_00_a7_01_83; + angles[123] = 80'hff_02_ff_e7_ff_f0_00_a8_01_83; + angles[124] = 80'hff_01_ff_f4_ff_f8_00_a8_01_83; + angles[125] = 80'hff_01_00_00_00_00_00_a8_01_83; diff --git a/src/angle_rom.v b/src/angle_rom.v new file mode 100644 index 0000000..7336dd2 --- /dev/null +++ b/src/angle_rom.v @@ -0,0 +1,30 @@ +// Primary "turn" angles. Later adjusted by cameraX multiplier before turning +// into rays. +module angle_rom ( + input clk, + input [6:0] addr, + output [79:0] angle // dirX, dirY, planeX, planeY Q8.8, invDet Q8.8 + ); + +reg [79:0] angles [125:0]; + +reg [79:0] a_d, a_q; + +assign angle = a_q; + +initial begin +`include "angle.rom" +end + +always @(*) begin + if (addr < 7'd126) + a_d = angles[addr]; + else + a_d = 80'd0; +end + +always @(posedge clk) begin + a_q <= a_d; +end + +endmodule diff --git a/src/avr_interface.v b/src/avr_interface.v new file mode 100644 index 0000000..66bc347 --- /dev/null +++ b/src/avr_interface.v @@ -0,0 +1,159 @@ +// from embedded micro base project +module avr_interface #( + parameter CLK_RATE = 50000000, + parameter SERIAL_BAUD_RATE = 500000 + )( + input clk, + input rst, + + // cclk, or configuration clock is used when the FPGA is begin configured. + // The AVR will hold cclk high when it has finished initializing. + // It is important not to drive the lines connecting to the AVR + // until cclk is high for a short period of time to avoid contention. + input cclk, + + // AVR SPI Signals + output spi_miso, + input spi_mosi, + input spi_sck, + input spi_ss, + output [3:0] spi_channel, + + // AVR Serial Signals + output tx, + input rx, + + // ADC Interface Signals + input [3:0] channel, + output new_sample, + output [9:0] sample, + output [3:0] sample_channel, + + // Serial TX User Interface + input [7:0] tx_data, + input new_tx_data, + output tx_busy, + input tx_block, + + // Serial Rx User Interface + output [7:0] rx_data, + output new_rx_data + ); + + wire ready; + wire n_rdy = !ready; + wire spi_done; + wire [7:0] spi_dout; + + wire tx_m; + wire spi_miso_m; + + reg byte_ct_d, byte_ct_q; + reg [9:0] sample_d, sample_q; + reg new_sample_d, new_sample_q; + reg [3:0] sample_channel_d, sample_channel_q; + reg [3:0] block_d, block_q; + reg busy_d, busy_q; + + // cclk_detector is used to detect when cclk is high signaling when + // the AVR is ready + cclk_detector #(.CLK_RATE(CLK_RATE)) cclk_detector ( + .clk(clk), + .rst(rst), + .cclk(cclk), + .ready(ready) + ); + + spi_slave spi_slave ( + .clk(clk), + .rst(n_rdy), + .ss(spi_ss), + .mosi(spi_mosi), + .miso(spi_miso_m), + .sck(spi_sck), + .done(spi_done), + .din(8'hff), + .dout(spi_dout) + ); + + // CLK_PER_BIT is the number of cycles each 'bit' lasts for + // rtoi converts a 'real' number to an 'integer' + parameter CLK_PER_BIT = $rtoi($ceil(CLK_RATE/SERIAL_BAUD_RATE)); + + serial_rx #(.CLK_PER_BIT(CLK_PER_BIT)) serial_rx ( + .clk(clk), + .rst(n_rdy), + .rx(rx), + .data(rx_data), + .new_data(new_rx_data) + ); + + serial_tx #(.CLK_PER_BIT(CLK_PER_BIT)) serial_tx ( + .clk(clk), + .rst(n_rdy), + .tx(tx_m), + .block(busy_q), + .busy(tx_busy), + .data(tx_data), + .new_data(new_tx_data) + ); + + // Output declarations + assign new_sample = new_sample_q; + assign sample = sample_q; + assign sample_channel = sample_channel_q; + + // these signals connect to the AVR and should be Z when the AVR isn't ready + assign spi_channel = ready ? channel : 4'bZZZZ; + assign spi_miso = ready && !spi_ss ? spi_miso_m : 1'bZ; + assign tx = ready ? tx_m : 1'bZ; + + always @(*) begin + byte_ct_d = byte_ct_q; + sample_d = sample_q; + new_sample_d = 1'b0; + sample_channel_d = sample_channel_q; + + busy_d = busy_q; + block_d = {block_q[2:0], tx_block}; + + if (block_q[3] ^ block_q[2]) + busy_d = 1'b0; + + if (!tx_busy && new_tx_data) + busy_d = 1'b1; + + if (spi_ss) begin // device is not selected + byte_ct_d = 1'b0; + end + + if (spi_done) begin // sent/received data from SPI + if (byte_ct_q == 1'b0) begin + sample_d[7:0] = spi_dout; // first byte is the 8 LSB of the sample + byte_ct_d = 1'b1; + end else begin + sample_d[9:8] = spi_dout[1:0]; // second byte is the channel 2 MSB of the sample + sample_channel_d = spi_dout[7:4]; // and the channel that was sampled + byte_ct_d = 1'b1; // slave-select must be brought high before the next transfer + new_sample_d = 1'b1; + end + end + end + + always @(posedge clk) begin + if (n_rdy) begin + byte_ct_q <= 1'b0; + sample_q <= 10'b0; + new_sample_q <= 1'b0; + end else begin + byte_ct_q <= byte_ct_d; + sample_q <= sample_d; + new_sample_q <= new_sample_d; + end + + block_q <= block_d; + busy_q <= busy_d; + sample_channel_q <= sample_channel_d; + end + +endmodule diff --git a/src/camerax.rom b/src/camerax.rom new file mode 100644 index 0000000..1f51413 --- /dev/null +++ b/src/camerax.rom @@ -0,0 +1,320 @@ + camerax_pos[0] = 16'hff_00; + camerax_pos[1] = 16'hff_02; + camerax_pos[2] = 16'hff_04; + camerax_pos[3] = 16'hff_05; + camerax_pos[4] = 16'hff_07; + camerax_pos[5] = 16'hff_08; + camerax_pos[6] = 16'hff_0a; + camerax_pos[7] = 16'hff_0c; + camerax_pos[8] = 16'hff_0d; + camerax_pos[9] = 16'hff_0f; + camerax_pos[10] = 16'hff_10; + camerax_pos[11] = 16'hff_12; + camerax_pos[12] = 16'hff_14; + camerax_pos[13] = 16'hff_15; + camerax_pos[14] = 16'hff_17; + camerax_pos[15] = 16'hff_18; + camerax_pos[16] = 16'hff_1a; + camerax_pos[17] = 16'hff_1c; + camerax_pos[18] = 16'hff_1d; + camerax_pos[19] = 16'hff_1f; + camerax_pos[20] = 16'hff_20; + camerax_pos[21] = 16'hff_22; + camerax_pos[22] = 16'hff_24; + camerax_pos[23] = 16'hff_25; + camerax_pos[24] = 16'hff_27; + camerax_pos[25] = 16'hff_28; + camerax_pos[26] = 16'hff_2a; + camerax_pos[27] = 16'hff_2c; + camerax_pos[28] = 16'hff_2d; + camerax_pos[29] = 16'hff_2f; + camerax_pos[30] = 16'hff_30; + camerax_pos[31] = 16'hff_32; + camerax_pos[32] = 16'hff_34; + camerax_pos[33] = 16'hff_35; + camerax_pos[34] = 16'hff_37; + camerax_pos[35] = 16'hff_38; + camerax_pos[36] = 16'hff_3a; + camerax_pos[37] = 16'hff_3c; + camerax_pos[38] = 16'hff_3d; + camerax_pos[39] = 16'hff_3f; + camerax_pos[40] = 16'hff_40; + camerax_pos[41] = 16'hff_42; + camerax_pos[42] = 16'hff_44; + camerax_pos[43] = 16'hff_45; + camerax_pos[44] = 16'hff_47; + camerax_pos[45] = 16'hff_48; + camerax_pos[46] = 16'hff_4a; + camerax_pos[47] = 16'hff_4c; + camerax_pos[48] = 16'hff_4d; + camerax_pos[49] = 16'hff_4f; + camerax_pos[50] = 16'hff_50; + camerax_pos[51] = 16'hff_52; + camerax_pos[52] = 16'hff_54; + camerax_pos[53] = 16'hff_55; + camerax_pos[54] = 16'hff_57; + camerax_pos[55] = 16'hff_58; + camerax_pos[56] = 16'hff_5a; + camerax_pos[57] = 16'hff_5c; + camerax_pos[58] = 16'hff_5d; + camerax_pos[59] = 16'hff_5f; + camerax_pos[60] = 16'hff_60; + camerax_pos[61] = 16'hff_62; + camerax_pos[62] = 16'hff_64; + camerax_pos[63] = 16'hff_65; + camerax_pos[64] = 16'hff_67; + camerax_pos[65] = 16'hff_68; + camerax_pos[66] = 16'hff_6a; + camerax_pos[67] = 16'hff_6c; + camerax_pos[68] = 16'hff_6d; + camerax_pos[69] = 16'hff_6f; + camerax_pos[70] = 16'hff_70; + camerax_pos[71] = 16'hff_72; + camerax_pos[72] = 16'hff_74; + camerax_pos[73] = 16'hff_75; + camerax_pos[74] = 16'hff_77; + camerax_pos[75] = 16'hff_78; + camerax_pos[76] = 16'hff_7a; + camerax_pos[77] = 16'hff_7c; + camerax_pos[78] = 16'hff_7d; + camerax_pos[79] = 16'hff_7f; + camerax_pos[80] = 16'hff_80; + camerax_pos[81] = 16'hff_82; + camerax_pos[82] = 16'hff_84; + camerax_pos[83] = 16'hff_85; + camerax_pos[84] = 16'hff_87; + camerax_pos[85] = 16'hff_88; + camerax_pos[86] = 16'hff_8a; + camerax_pos[87] = 16'hff_8c; + camerax_pos[88] = 16'hff_8d; + camerax_pos[89] = 16'hff_8f; + camerax_pos[90] = 16'hff_90; + camerax_pos[91] = 16'hff_92; + camerax_pos[92] = 16'hff_94; + camerax_pos[93] = 16'hff_95; + camerax_pos[94] = 16'hff_97; + camerax_pos[95] = 16'hff_98; + camerax_pos[96] = 16'hff_9a; + camerax_pos[97] = 16'hff_9c; + camerax_pos[98] = 16'hff_9d; + camerax_pos[99] = 16'hff_9f; + camerax_pos[100] = 16'hff_a0; + camerax_pos[101] = 16'hff_a2; + camerax_pos[102] = 16'hff_a4; + camerax_pos[103] = 16'hff_a5; + camerax_pos[104] = 16'hff_a7; + camerax_pos[105] = 16'hff_a8; + camerax_pos[106] = 16'hff_aa; + camerax_pos[107] = 16'hff_ac; + camerax_pos[108] = 16'hff_ad; + camerax_pos[109] = 16'hff_af; + camerax_pos[110] = 16'hff_b0; + camerax_pos[111] = 16'hff_b2; + camerax_pos[112] = 16'hff_b4; + camerax_pos[113] = 16'hff_b5; + camerax_pos[114] = 16'hff_b7; + camerax_pos[115] = 16'hff_b8; + camerax_pos[116] = 16'hff_ba; + camerax_pos[117] = 16'hff_bc; + camerax_pos[118] = 16'hff_bd; + camerax_pos[119] = 16'hff_bf; + camerax_pos[120] = 16'hff_c0; + camerax_pos[121] = 16'hff_c2; + camerax_pos[122] = 16'hff_c4; + camerax_pos[123] = 16'hff_c5; + camerax_pos[124] = 16'hff_c7; + camerax_pos[125] = 16'hff_c8; + camerax_pos[126] = 16'hff_ca; + camerax_pos[127] = 16'hff_cc; + camerax_pos[128] = 16'hff_cd; + camerax_pos[129] = 16'hff_cf; + camerax_pos[130] = 16'hff_d0; + camerax_pos[131] = 16'hff_d2; + camerax_pos[132] = 16'hff_d4; + camerax_pos[133] = 16'hff_d5; + camerax_pos[134] = 16'hff_d7; + camerax_pos[135] = 16'hff_d8; + camerax_pos[136] = 16'hff_da; + camerax_pos[137] = 16'hff_dc; + camerax_pos[138] = 16'hff_dd; + camerax_pos[139] = 16'hff_df; + camerax_pos[140] = 16'hff_e0; + camerax_pos[141] = 16'hff_e2; + camerax_pos[142] = 16'hff_e4; + camerax_pos[143] = 16'hff_e5; + camerax_pos[144] = 16'hff_e7; + camerax_pos[145] = 16'hff_e8; + camerax_pos[146] = 16'hff_ea; + camerax_pos[147] = 16'hff_ec; + camerax_pos[148] = 16'hff_ed; + camerax_pos[149] = 16'hff_ef; + camerax_pos[150] = 16'hff_f0; + camerax_pos[151] = 16'hff_f2; + camerax_pos[152] = 16'hff_f4; + camerax_pos[153] = 16'hff_f5; + camerax_pos[154] = 16'hff_f7; + camerax_pos[155] = 16'hff_f8; + camerax_pos[156] = 16'hff_fa; + camerax_pos[157] = 16'hff_fc; + camerax_pos[158] = 16'hff_fd; + camerax_pos[159] = 16'hff_ff; + camerax_pos[160] = 16'h00_00; + camerax_pos[161] = 16'h00_01; + camerax_pos[162] = 16'h00_03; + camerax_pos[163] = 16'h00_04; + camerax_pos[164] = 16'h00_06; + camerax_pos[165] = 16'h00_08; + camerax_pos[166] = 16'h00_09; + camerax_pos[167] = 16'h00_0b; + camerax_pos[168] = 16'h00_0c; + camerax_pos[169] = 16'h00_0e; + camerax_pos[170] = 16'h00_10; + camerax_pos[171] = 16'h00_11; + camerax_pos[172] = 16'h00_13; + camerax_pos[173] = 16'h00_14; + camerax_pos[174] = 16'h00_16; + camerax_pos[175] = 16'h00_18; + camerax_pos[176] = 16'h00_19; + camerax_pos[177] = 16'h00_1b; + camerax_pos[178] = 16'h00_1c; + camerax_pos[179] = 16'h00_1e; + camerax_pos[180] = 16'h00_20; + camerax_pos[181] = 16'h00_21; + camerax_pos[182] = 16'h00_23; + camerax_pos[183] = 16'h00_24; + camerax_pos[184] = 16'h00_26; + camerax_pos[185] = 16'h00_28; + camerax_pos[186] = 16'h00_29; + camerax_pos[187] = 16'h00_2b; + camerax_pos[188] = 16'h00_2c; + camerax_pos[189] = 16'h00_2e; + camerax_pos[190] = 16'h00_30; + camerax_pos[191] = 16'h00_31; + camerax_pos[192] = 16'h00_33; + camerax_pos[193] = 16'h00_34; + camerax_pos[194] = 16'h00_36; + camerax_pos[195] = 16'h00_38; + camerax_pos[196] = 16'h00_39; + camerax_pos[197] = 16'h00_3b; + camerax_pos[198] = 16'h00_3c; + camerax_pos[199] = 16'h00_3e; + camerax_pos[200] = 16'h00_40; + camerax_pos[201] = 16'h00_41; + camerax_pos[202] = 16'h00_43; + camerax_pos[203] = 16'h00_44; + camerax_pos[204] = 16'h00_46; + camerax_pos[205] = 16'h00_48; + camerax_pos[206] = 16'h00_49; + camerax_pos[207] = 16'h00_4b; + camerax_pos[208] = 16'h00_4c; + camerax_pos[209] = 16'h00_4e; + camerax_pos[210] = 16'h00_50; + camerax_pos[211] = 16'h00_51; + camerax_pos[212] = 16'h00_53; + camerax_pos[213] = 16'h00_54; + camerax_pos[214] = 16'h00_56; + camerax_pos[215] = 16'h00_58; + camerax_pos[216] = 16'h00_59; + camerax_pos[217] = 16'h00_5b; + camerax_pos[218] = 16'h00_5c; + camerax_pos[219] = 16'h00_5e; + camerax_pos[220] = 16'h00_60; + camerax_pos[221] = 16'h00_61; + camerax_pos[222] = 16'h00_63; + camerax_pos[223] = 16'h00_64; + camerax_pos[224] = 16'h00_66; + camerax_pos[225] = 16'h00_68; + camerax_pos[226] = 16'h00_69; + camerax_pos[227] = 16'h00_6b; + camerax_pos[228] = 16'h00_6c; + camerax_pos[229] = 16'h00_6e; + camerax_pos[230] = 16'h00_70; + camerax_pos[231] = 16'h00_71; + camerax_pos[232] = 16'h00_73; + camerax_pos[233] = 16'h00_74; + camerax_pos[234] = 16'h00_76; + camerax_pos[235] = 16'h00_78; + camerax_pos[236] = 16'h00_79; + camerax_pos[237] = 16'h00_7b; + camerax_pos[238] = 16'h00_7c; + camerax_pos[239] = 16'h00_7e; + camerax_pos[240] = 16'h00_80; + camerax_pos[241] = 16'h00_81; + camerax_pos[242] = 16'h00_83; + camerax_pos[243] = 16'h00_84; + camerax_pos[244] = 16'h00_86; + camerax_pos[245] = 16'h00_88; + camerax_pos[246] = 16'h00_89; + camerax_pos[247] = 16'h00_8b; + camerax_pos[248] = 16'h00_8c; + camerax_pos[249] = 16'h00_8e; + camerax_pos[250] = 16'h00_90; + camerax_pos[251] = 16'h00_91; + camerax_pos[252] = 16'h00_93; + camerax_pos[253] = 16'h00_94; + camerax_pos[254] = 16'h00_96; + camerax_pos[255] = 16'h00_98; + camerax_pos[256] = 16'h00_99; + camerax_pos[257] = 16'h00_9b; + camerax_pos[258] = 16'h00_9c; + camerax_pos[259] = 16'h00_9e; + camerax_pos[260] = 16'h00_a0; + camerax_pos[261] = 16'h00_a1; + camerax_pos[262] = 16'h00_a3; + camerax_pos[263] = 16'h00_a4; + camerax_pos[264] = 16'h00_a6; + camerax_pos[265] = 16'h00_a8; + camerax_pos[266] = 16'h00_a9; + camerax_pos[267] = 16'h00_ab; + camerax_pos[268] = 16'h00_ac; + camerax_pos[269] = 16'h00_ae; + camerax_pos[270] = 16'h00_b0; + camerax_pos[271] = 16'h00_b1; + camerax_pos[272] = 16'h00_b3; + camerax_pos[273] = 16'h00_b4; + camerax_pos[274] = 16'h00_b6; + camerax_pos[275] = 16'h00_b8; + camerax_pos[276] = 16'h00_b9; + camerax_pos[277] = 16'h00_bb; + camerax_pos[278] = 16'h00_bc; + camerax_pos[279] = 16'h00_be; + camerax_pos[280] = 16'h00_c0; + camerax_pos[281] = 16'h00_c1; + camerax_pos[282] = 16'h00_c3; + camerax_pos[283] = 16'h00_c4; + camerax_pos[284] = 16'h00_c6; + camerax_pos[285] = 16'h00_c8; + camerax_pos[286] = 16'h00_c9; + camerax_pos[287] = 16'h00_cb; + camerax_pos[288] = 16'h00_cc; + camerax_pos[289] = 16'h00_ce; + camerax_pos[290] = 16'h00_d0; + camerax_pos[291] = 16'h00_d1; + camerax_pos[292] = 16'h00_d3; + camerax_pos[293] = 16'h00_d4; + camerax_pos[294] = 16'h00_d6; + camerax_pos[295] = 16'h00_d8; + camerax_pos[296] = 16'h00_d9; + camerax_pos[297] = 16'h00_db; + camerax_pos[298] = 16'h00_dc; + camerax_pos[299] = 16'h00_de; + camerax_pos[300] = 16'h00_e0; + camerax_pos[301] = 16'h00_e1; + camerax_pos[302] = 16'h00_e3; + camerax_pos[303] = 16'h00_e4; + camerax_pos[304] = 16'h00_e6; + camerax_pos[305] = 16'h00_e8; + camerax_pos[306] = 16'h00_e9; + camerax_pos[307] = 16'h00_eb; + camerax_pos[308] = 16'h00_ec; + camerax_pos[309] = 16'h00_ee; + camerax_pos[310] = 16'h00_f0; + camerax_pos[311] = 16'h00_f1; + camerax_pos[312] = 16'h00_f3; + camerax_pos[313] = 16'h00_f4; + camerax_pos[314] = 16'h00_f6; + camerax_pos[315] = 16'h00_f8; + camerax_pos[316] = 16'h00_f9; + camerax_pos[317] = 16'h00_fb; + camerax_pos[318] = 16'h00_fc; + camerax_pos[319] = 16'h00_fe; diff --git a/src/camerax_rom.v b/src/camerax_rom.v new file mode 100644 index 0000000..aca31e9 --- /dev/null +++ b/src/camerax_rom.v @@ -0,0 +1,30 @@ +// not using signed values here since I had some bugs. +// users of this data need to treat it as signed. +module camerax_rom ( + input clk, + input [8:0] addr, + output [15:0] camerax // Q8.8 + ); + +reg [15:0] camerax_pos [319:0]; + +reg [15:0] cx_d, cx_q; + +assign camerax = cx_q; + +initial begin +`include "camerax.rom" +end + +always @(*) begin + if (addr < 9'd320) + cx_d = camerax_pos[addr]; + else + cx_d = 16'd0; +end + +always @(posedge clk) begin + cx_q <= cx_d; +end + +endmodule diff --git a/src/cast_ray.v b/src/cast_ray.v new file mode 100644 index 0000000..bc1c2f4 --- /dev/null +++ b/src/cast_ray.v @@ -0,0 +1,553 @@ +// Q8.8 numerics +// ray caster algorithm adapted from https://lodev.org/cgtutor/raycasting.html + +module cast_ray ( + input clk, + input rst, + + input [8:0] x, // camera X position + input [79:0] angle, // directional position + + input [15:0] map_pos_x, + input [15:0] map_pos_y, + + input start, + output reg busy, + output reg done, + + // line writer wires. + output [39:0] line_height, + output [7:0] line_color, + output [6:0] line_tex_x, + output [15:0] line_floor_x, + output [15:0] line_floor_y, + output [15:0] line_pos_x, + output [15:0] line_pos_y, + output [15:0] wall_z +); + +localparam TEX_WIDTH = 16'd32; + +// map ROM +reg [7:0] map_rom_x, map_rom_y; +wire [3:0] map_point; +map_rom map_rom ( + .x(map_rom_x), + .y(map_rom_y), + .point(map_point) +); + +// camera X ROM. +reg [8:0] camerax_addr; +wire [15:0] camerax; // Q2.14 +reg signed [15:0] camerax_d, camerax_q; // internal registers +camerax_rom camerax_rom ( + .clk(clk), + .addr(camerax_addr), + .camerax(camerax) +); + +// internal registers +reg signed [15:0] dirx_d, dirx_q; +reg signed [15:0] diry_d, diry_q; +reg signed [15:0] planex_d, planex_q; +reg signed [15:0] planey_d, planey_q; + +// height ROM +wire [9:0] height_addr; +reg [39:0] line_height_d, line_height_q; +wire [39:0] line_height_read; +height_rom height_rom ( + .clk(clk), + .addr(height_addr), + .height(line_height_read) +); + +// divider +reg div_valid; +wire div_out_valid, div_ready; +reg [23:0] dividend; +reg [15:0] divisor; +reg [15:0] divisor_hold; +reg [15:0] divres_hold; +wire [39:0] div_result; +div_8_dot_8_nodsp div ( + .aclk(clk), + .s_axis_divisor_tvalid(div_valid), + .s_axis_dividend_tvalid(div_valid), + .m_axis_dout_tvalid(div_out_valid), + .s_axis_dividend_tdata(dividend), + .s_axis_divisor_tdata(divisor), + .s_axis_divisor_tready(div_ready), + .m_axis_dout_tdata(div_result) +); +// simple bit flags to track which delta's been loaded/processed +// for division. +reg [2:0] cdelta_d, cdelta_q; + +reg signed [15:0] raydir_x_d, raydir_x_q; +reg signed [15:0] raydir_y_d, raydir_y_q; +reg [15:0] delta_dist_x_d, delta_dist_x_q; +reg [15:0] delta_dist_y_d, delta_dist_y_q; +reg signed [15:0] delta_dist_n_x_d, delta_dist_n_x_q; +reg signed [15:0] delta_dist_n_y_d, delta_dist_n_y_q; +reg [15:0] map_pos_x_d, map_pos_x_q; +reg [15:0] map_pos_y_d, map_pos_y_q; + +reg [15:0] step_x_d, step_x_q; +reg [15:0] step_y_d, step_y_q; +reg [15:0] sidestep_x_d, sidestep_x_q; +reg [15:0] sidestep_y_d, sidestep_y_q; + +reg [15:0] map_x_d, map_x_q, map_y_d, map_y_q; +reg side_d, side_q; + +// 32bit to hold multiplication +reg [15:0] side_dist_x_d, side_dist_x_q; +reg [15:0] side_dist_y_d, side_dist_y_q; +reg signed [15:0] p_wall_dist_d, p_wall_dist_q; + +// texture indexes +reg [15:0] wall_x_d, wall_x_q; +reg [6:0] texture_x_d, texture_x_q; +reg [7:0] color_d, color_q; +reg [15:0] floor_x_wall_d, floor_x_wall_q; +reg [15:0] floor_y_wall_d, floor_y_wall_q; + +// shared multiplier +reg signed [15:0] mul_res_d, mul_res_q; +reg signed [15:0] mul_arg1_d, mul_arg1_q; +reg signed [15:0] mul_arg2_d, mul_arg2_q; + +initial begin + sidestep_x_q = 16'd0; + sidestep_y_q = 16'd0; + step_x_q = 8'd0; + step_y_q = 8'd0; +end + +// FIXME: organize these combinatorial bits better. +assign line_height = line_height_q; +assign line_tex_x = texture_x_q; +assign line_color = color_q; +assign line_floor_x = floor_x_wall_q; +assign line_floor_y = floor_y_wall_q; +assign line_pos_x = map_pos_x_q; +assign line_pos_y = map_pos_y_q; +// height address is actually 10 bit. using Q5.5 out of wall dist. +assign height_addr[9:0] = p_wall_dist_q[12:3]; +assign wall_z = p_wall_dist_q; + +reg [4:0] state_d, state_q; // FIXME: clog2/etc +reg [4:0] next_state_d, next_state_q; +localparam IDLE = 0, + START_CAST = 1, + DDA_DIST_CALC = 2, + DDA_FIND_HIT = 3, + CALC_WALLDIST = 6, + FIND_LINEHEIGHT = 8, + DRAW_LINE_GO = 9, + WAIT_LINE = 10, + CALC_WALLDIST2 = 11, + ROM_LOOKUP = 12, + RAY_CALC = 13, + DELTADIST_CALC = 14, + DDA_DIST_CALCX_SETUP = 15, + DDA_DIST_CALCY_SETUP = 16, + DDA_DIST_CALC_FINAL = 17, + WALL_TEX = 18, + WALL_TEX2 = 19, + WALL_TEX3 = 20, + MULTIPLY = 21, + RAY_CALC_ADDX = 22, + RAY_CALC_ADDY = 23; + +always @(*) begin + state_d = state_q; + delta_dist_x_d = delta_dist_x_q; + delta_dist_y_d = delta_dist_y_q; + delta_dist_n_x_d = delta_dist_n_x_q; + delta_dist_n_y_d = delta_dist_n_y_q; + sidestep_x_d = sidestep_x_q; + sidestep_y_d = sidestep_y_q; + step_x_d = step_x_q; + step_y_d = step_y_q; + side_dist_x_d = side_dist_x_q; + side_dist_y_d = side_dist_y_q; + map_x_d = map_x_q; + map_y_d = map_y_q; + map_pos_x_d = map_pos_x_q; + map_pos_y_d = map_pos_y_q; + map_rom_x = 0; + map_rom_y = 0; + side_d = side_q; + p_wall_dist_d = p_wall_dist_q; + // texture/line info + wall_x_d = wall_x_q; + texture_x_d = texture_x_q; + color_d = color_q; + line_height_d = line_height_q; + floor_x_wall_d = floor_x_wall_q; + floor_y_wall_d = floor_y_wall_q; + // divider + div_valid = 1'b0; + dividend = 24'h01_00_00; // ray calculations are "1 / raydir[xy]" + divisor = 16'h00_01; // dummy value, overwritten when used. + divisor_hold = 16'd0; + cdelta_d = cdelta_q; + // ROM indexes + camerax_addr = x; + // plane and rays. + raydir_x_d = raydir_x_q; + raydir_y_d = raydir_y_q; + dirx_d = dirx_q; + diry_d = diry_q; + planex_d = planex_q; + planey_d = planey_q; + camerax_d = camerax_q; + busy = 1'b1; + done = 1'b0; + // multiplier + mul_res_d = mul_res_q; + mul_arg1_d = mul_arg1_q; + mul_arg2_d = mul_arg2_q; + next_state_d = next_state_q; + + case (state_q) + IDLE: begin + busy = 1'b0; + if (start) begin + map_pos_x_d = map_pos_x; + map_pos_y_d = map_pos_y; + state_d = ROM_LOOKUP; + end + end + MULTIPLY: begin + mul_res_d = trunc_fixed_mul(mul_arg1_q * mul_arg2_q); + state_d = next_state_q; + end + ROM_LOOKUP: begin + // grab/split cameraX and directionals + camerax_d = camerax; + dirx_d = angle[79:64]; + diry_d = angle[63:48]; + planex_d = angle[47:32]; + planey_d = angle[31:16]; + // move on to ray calculations + state_d = RAY_CALC; + end + RAY_CALC: begin + // calculate rayDirX, rayDirY + // original simpler calculation. + /*raydir_x_d = dirx_q + trunc_fixed_mul(planex_q * camerax_q); + raydir_y_d = diry_q + trunc_fixed_mul(planey_q * camerax_q); + state_d = DELTADIST_CALC;*/ + // want to share the multiplier, so we step through one at a time. + mul_arg1_d = planex_q; + mul_arg2_d = camerax_q; + next_state_d = RAY_CALC_ADDX; + state_d = MULTIPLY; + end + RAY_CALC_ADDX: begin + // finalize result of first multiply. + raydir_x_d = dirx_q + mul_res_q; + // prepare the next multiply. + mul_arg1_d = planey_q; + // arg2 is still camerax_q + next_state_d = RAY_CALC_ADDY; + state_d = MULTIPLY; + end + RAY_CALC_ADDY: begin + // reset counter for tracking division progress. + cdelta_d = 2'b00; + // finalize the y direction. + raydir_y_d = diry_q + mul_res_q; + state_d = DELTADIST_CALC; + end + DELTADIST_CALC: begin + // the divider is ready and gives a result every 4 cycles, with + // a long (~30 cycle) delay. This queues up our divisions as the + // divider becomes ready, so we don't have to wait for the full + // delay twice. + if (div_ready && !cdelta_q[2]) begin + if (!cdelta_q[0]) begin + divisor_hold = raydir_x_q; + cdelta_d[0] = 1'b1; + end else begin + divisor_hold = raydir_y_q; + // all divisions queued. + cdelta_d[2] = 1'b1; + end + + // avoid divide by zero. + if (divisor_hold != 16'd0) begin + divisor = divisor_hold; + end else begin + // TODO: Can skip the division in this case since we + // divisor/dividend are both static. + divisor = 16'd00_01; + end + div_valid = 1'b1; + end + + // divisions come home to roost. + if (div_out_valid) begin + // handle special cases where we overflow our 16bit results. + // the division is 24bit so we can detect this situation. + if (div_result[31:16] == 16'd0) begin + // to infinity, and beyond! + if (div_result[39]) begin // negative max + divres_hold = 16'h8000; + end else begin // positive max + divres_hold = 16'h7FFF; + end + end else begin + divres_hold = div_result[31:16]; + end + + if (!cdelta_q[1]) begin + delta_dist_n_x_d = divres_hold; + cdelta_d[1] = 1'b1; + end else begin + delta_dist_n_y_d = divres_hold; + // all divisions are done. resume processing. + state_d = START_CAST; + end + end + end + START_CAST: begin + // keep positive values of delta distance + // hold step and sidestep for DDA calculations + if (delta_dist_n_x_q[15]) begin // negative + delta_dist_x_d = (~delta_dist_n_x_q) + 16'h00_01; + step_x_d = 16'b1111_1111_0000_0000; + sidestep_x_d = 16'b0000_0001_0000_0000; + end else begin // pos + delta_dist_x_d = delta_dist_n_x_q; + step_x_d = 16'b0000_0001_0000_0000; + sidestep_x_d = 16'b0000_0000_0000_0000; + end + if (delta_dist_n_y_q[15]) begin // n + delta_dist_y_d = (~delta_dist_n_y_q) + 16'h00_01; + step_y_d = 16'b1111_1111_0000_0000; + sidestep_y_d = 16'b0000_0001_0000_0000; + end else begin // p + delta_dist_y_d = delta_dist_n_y_q; + step_y_d = 16'b0000_0001_0000_0000; + sidestep_y_d = 16'b0000_0000_0000_0000; + end + map_x_d = (map_pos_x_q & 16'hFF_00); + map_y_d = (map_pos_y_q & 16'hFF_00); + state_d = DDA_DIST_CALCX_SETUP; + end + DDA_DIST_CALCX_SETUP: begin + mul_arg2_d = delta_dist_x_q; + if (delta_dist_n_x_q[15]) begin // negative + mul_arg1_d = map_pos_x_q & 16'h00_FF; + end else begin // pos + mul_arg1_d = (map_pos_x_q & 16'hFF_00) + 16'h01_00 - map_pos_x_q; + end + next_state_d = DDA_DIST_CALCY_SETUP; + state_d = MULTIPLY; + end + DDA_DIST_CALCY_SETUP: begin + // result of last multiply. + side_dist_x_d = mul_res_q; + // setup next multiply. + mul_arg2_d = delta_dist_y_q; + if (delta_dist_n_y_q[15]) begin // negative + mul_arg1_d = map_pos_y_q & 16'h00_FF; + end else begin // pos + mul_arg1_d = (map_pos_y_q & 16'hFF_00) + 16'h01_00 - map_pos_y_q; + end + next_state_d = DDA_DIST_CALC_FINAL; + state_d = MULTIPLY; + end + DDA_DIST_CALC_FINAL: begin + side_dist_y_d = mul_res_q; + state_d = DDA_FIND_HIT; + end + // The actual DDA loop (single cycle!)! + // we implement the map by slice memory, so a combinatorial lookup can + // happen so long as the logic isn't too deep. + // if we want to run the design at a higher clock rate, would likely + // have to split this into multiple cycles. + // or, if we want to use block ram (single cycle delay), it would have + // to pipeline the map lookup for the next check ahead of time. + DDA_FIND_HIT: begin + if (side_dist_x_q < side_dist_y_q) begin + side_dist_x_d = side_dist_x_q + (delta_dist_x_q); + map_x_d = map_x_q + step_x_q; + side_d = 0; + end else begin + side_dist_y_d = side_dist_y_q + (delta_dist_y_q); + map_y_d = map_y_q + step_y_q; + side_d = 1'b1; + end + + map_rom_x = map_x_d[15:8]; + map_rom_y = map_y_d[15:8]; + + if (map_point != 4'd0) begin + color_d[3:0] = map_point; // placeholder "color" + color_d[7] = side_d; // change color depending on side hit + state_d = CALC_WALLDIST; + end + end + // DDA is done now. Prepare a few calculations for floor/ceiling + // casting, grab the wall line height, etc. + CALC_WALLDIST: begin + // use the shared multiplier to find the wall distance. + if (side_q == 1'b0) begin + mul_arg1_d = (map_x_q - map_pos_x_q + sidestep_x_q); + mul_arg2_d = delta_dist_n_x_q; + end else begin + mul_arg1_d = (map_y_q - map_pos_y_q + sidestep_y_q); + mul_arg2_d = delta_dist_n_y_q; + end + state_d = MULTIPLY; + next_state_d = CALC_WALLDIST2; + end + CALC_WALLDIST2: begin + p_wall_dist_d = mul_res_q; + state_d = FIND_LINEHEIGHT; + end + FIND_LINEHEIGHT: begin + // while we're loading the line height, we also need to calculate + // the texture x offset. + // first, take the fractional part after calculating in the angle + mul_arg1_d = p_wall_dist_q; + if (side_q == 1'b0) begin + mul_arg2_d = raydir_y_q; + end else begin + mul_arg2_d = raydir_x_q; + end + state_d = MULTIPLY; + next_state_d = WALL_TEX; + end + WALL_TEX: begin + // grab line height lookup while we're here. + line_height_d = line_height_read; + if (side_q == 1'b0) begin + wall_x_d = (map_pos_y_q + mul_res_q) & 16'h00_FF; + end else begin + wall_x_d = (map_pos_x_q + mul_res_q) & 16'h00_FF; + end + state_d = WALL_TEX2; + end + WALL_TEX2: begin + state_d = WALL_TEX3; + // finish the wall calculation. + // take the fractional part of wallx and multiply by the texture + // width. + // TODO: shared multiplier? as of writing this module is only + // using a single DSP, so it should be fine to leave this here. + wall_x_d = trunc_fixed_mul(wall_x_q * (TEX_WIDTH << 8)); + // while we're here, also prep the floor x offset. + // doing this now since further modifying wall_x after this cycle. + if (side_q == 1'b0 && !raydir_x_q[15]) begin + floor_x_wall_d = map_x_q; + floor_y_wall_d = map_y_q + wall_x_q; + end else if (side_q == 1'b0 && raydir_x_q[15]) begin + floor_x_wall_d = map_x_q + 16'h01_00; + floor_y_wall_d = map_y_q + wall_x_q; + end else if (side_q == 1'b1 && !raydir_y_q[15]) begin + floor_x_wall_d = map_x_q + wall_x_q; + floor_y_wall_d = map_y_q; + end else begin + floor_x_wall_d = map_x_q + wall_x_q; + floor_y_wall_d = map_y_q + 16'h01_00; + end + end + WALL_TEX3: begin + // inverse the x coordinate for certain angles. + if (side_q == 1'b0 && !raydir_x_q[15]) begin + texture_x_d = TEX_WIDTH - wall_x_q[15:8] - 1'b1; + end else if (side_q == 1'b1 && raydir_y_q[15]) begin + texture_x_d = TEX_WIDTH - wall_x_q[15:8] - 1'b1; + end else begin + texture_x_d = wall_x_q[15:8]; + end + state_d = DRAW_LINE_GO; + end + DRAW_LINE_GO: begin + // line_height_q and texture_x_q should be correct now. + state_d = IDLE; + done = 1'b1; + end + default: begin + state_d = IDLE; + end + endcase +end + +always @(posedge clk) begin + if (rst) begin + state_q = IDLE; + delta_dist_x_q <= 0; + delta_dist_y_q <= 0; + delta_dist_n_x_q <= 0; + delta_dist_n_y_q <= 0; + sidestep_x_q <= 0; + sidestep_y_q <= 0; + step_x_q <= 0; + step_y_q <= 0; + side_dist_x_q <= 0; + side_dist_y_q <= 0; + map_x_q <= 0; + map_y_q <= 0; + side_q <= 0; + p_wall_dist_q <= 0; + color_q <= 0; + line_height_q <= 0; + map_pos_x_q <= 0; + map_pos_y_q <= 0; + end else begin + state_q = state_d; + delta_dist_x_q <= delta_dist_x_d; + delta_dist_y_q <= delta_dist_y_d; + delta_dist_n_x_q <= delta_dist_n_x_d; + delta_dist_n_y_q <= delta_dist_n_y_d; + sidestep_x_q <= sidestep_x_d; + sidestep_y_q <= sidestep_y_d; + step_x_q <= step_x_d; + step_y_q <= step_y_d; + side_dist_x_q <= side_dist_x_d; + side_dist_y_q <= side_dist_y_d; + map_x_q <= map_x_d; + map_y_q <= map_y_d; + p_wall_dist_q <= p_wall_dist_d; + side_q <= side_d; + color_q <= color_d; + line_height_q <= line_height_d; + map_pos_x_q <= map_pos_x_d; + map_pos_y_q <= map_pos_y_d; + end + raydir_x_q <= raydir_x_d; + raydir_y_q <= raydir_y_d; + dirx_q <= dirx_d; + diry_q <= diry_d; + planex_q <= planex_d; + planey_q <= planey_d; + camerax_q <= camerax_d; + wall_x_q <= wall_x_d; + texture_x_q <= texture_x_d; + floor_x_wall_q <= floor_x_wall_d; + floor_y_wall_q <= floor_y_wall_d; + mul_res_q <= mul_res_d; + mul_arg1_q <= mul_arg1_d; + mul_arg2_q <= mul_arg2_d; + next_state_q <= next_state_d; + cdelta_q <= cdelta_d; +end + +// middle result of a Q8.8 multiplication is the actual result. +// verilog complains a lot about unused bits in registers unless you use +// a function like this. +// should also simplify the rest of the math. +// FIXME: use it for sidedist calc. +function signed [15:0] trunc_fixed_mul(input signed [31:0] mulres); + trunc_fixed_mul = mulres[23:8]; +endfunction + +endmodule diff --git a/src/cast_ray_tb.v b/src/cast_ray_tb.v new file mode 100644 index 0000000..7b58f65 --- /dev/null +++ b/src/cast_ray_tb.v @@ -0,0 +1,71 @@ +`timescale 1ns / 1ps + +module cast_ray_tb( + ); + +reg clk; +reg rst; + +reg [8:0] x; +reg [6:0] turn; + +reg [15:0] map_pos_x; +reg [15:0] map_pos_y; + +reg start; +wire busy; +wire [23:0] line_height; +wire [7:0] line_color; +wire [6:0] line_tex_x; + +cast_ray DUT ( + .clk(clk), + .rst(rst), + .x(x), + .turn(turn), + .map_pos_x(map_pos_x), + .map_pos_y(map_pos_y), + .start(start), + .busy(busy), + .line_height(line_height), + .line_color(line_color), + .line_tex_x(line_tex_x) +); + + // wait by delay for clocks rather than manually run them. + initial begin + clk = 0; + forever #10 clk = ~clk; + end + + initial begin + rst = 1'b1; + repeat(6) @(posedge clk); + rst = 1'b0; + repeat(2) @(posedge clk); + /*delta_dist_n_x = 16'hFF_00; + delta_dist_n_y = 16'hFE_7D; + map_pos_x = 16'h16_00; + map_pos_y = 16'h16_00;*/ + // 37 fe d0 fe + //delta_dist_n_y = 16'hFE_37; + //delta_dist_n_x = 16'hFE_D0; + // 0c 13 90 14 + x = 9'd30; + turn = 7'd16; + map_pos_x = 16'h13_0c; + map_pos_y = 16'h14_90; + start = 1'b1; + @(posedge clk); + start = 1'b0; + repeat(100) @(posedge clk); + // done and line_height should be set. + #5000 + $finish; + end + + initial begin + #500000000 + $finish; + end +endmodule diff --git a/src/cclk_detector.v b/src/cclk_detector.v new file mode 100644 index 0000000..398ac96 --- /dev/null +++ b/src/cclk_detector.v @@ -0,0 +1,43 @@ +// from embedded micro base project + +module cclk_detector #( + parameter CLK_RATE = 50000000 + )( + input clk, + input rst, + input cclk, + output ready +); + + parameter CTR_SIZE = $clog2(CLK_RATE/50000); + + reg [CTR_SIZE-1:0] ctr_d, ctr_q; + reg ready_d, ready_q; + + assign ready = ready_q; + + // ready should only go high once cclk has been high for a while + // if cclk ever falls, ready should go low again + always @(ctr_q or cclk) begin + ready_d = 1'b0; + if (cclk == 1'b0) begin // when cclk is 0 reset the counter + ctr_d = 1'b0; + end else if (ctr_q != {CTR_SIZE{1'b1}}) begin + ctr_d = ctr_q + 1'b1; // counter isn't max value yet + end else begin + ctr_d = ctr_q; + ready_d = 1'b1; // counter reached the max, we are ready + end + + end + + always @(posedge clk) begin + if (rst) begin + ctr_q <= 1'b0; + ready_q <= 1'b0; + end else begin + ctr_q <= ctr_d; + ready_q <= ready_d; + end + end +endmodule diff --git a/src/floordist.rom b/src/floordist.rom new file mode 100644 index 0000000..4b2df02 --- /dev/null +++ b/src/floordist.rom @@ -0,0 +1,120 @@ + floor_dist[0] = 16'h78_00; + floor_dist[1] = 16'h3c_00; + floor_dist[2] = 16'h28_00; + floor_dist[3] = 16'h1e_00; + floor_dist[4] = 16'h18_00; + floor_dist[5] = 16'h14_00; + floor_dist[6] = 16'h11_24; + floor_dist[7] = 16'h0f_00; + floor_dist[8] = 16'h0d_55; + floor_dist[9] = 16'h0c_00; + floor_dist[10] = 16'h0a_e8; + floor_dist[11] = 16'h0a_00; + floor_dist[12] = 16'h09_3b; + floor_dist[13] = 16'h08_92; + floor_dist[14] = 16'h08_00; + floor_dist[15] = 16'h07_80; + floor_dist[16] = 16'h07_0f; + floor_dist[17] = 16'h06_aa; + floor_dist[18] = 16'h06_50; + floor_dist[19] = 16'h06_00; + floor_dist[20] = 16'h05_b6; + floor_dist[21] = 16'h05_74; + floor_dist[22] = 16'h05_37; + floor_dist[23] = 16'h05_00; + floor_dist[24] = 16'h04_cc; + floor_dist[25] = 16'h04_9d; + floor_dist[26] = 16'h04_71; + floor_dist[27] = 16'h04_49; + floor_dist[28] = 16'h04_23; + floor_dist[29] = 16'h04_00; + floor_dist[30] = 16'h03_de; + floor_dist[31] = 16'h03_c0; + floor_dist[32] = 16'h03_a2; + floor_dist[33] = 16'h03_87; + floor_dist[34] = 16'h03_6d; + floor_dist[35] = 16'h03_55; + floor_dist[36] = 16'h03_3e; + floor_dist[37] = 16'h03_28; + floor_dist[38] = 16'h03_13; + floor_dist[39] = 16'h03_00; + floor_dist[40] = 16'h02_ed; + floor_dist[41] = 16'h02_db; + floor_dist[42] = 16'h02_ca; + floor_dist[43] = 16'h02_ba; + floor_dist[44] = 16'h02_aa; + floor_dist[45] = 16'h02_9b; + floor_dist[46] = 16'h02_8d; + floor_dist[47] = 16'h02_80; + floor_dist[48] = 16'h02_72; + floor_dist[49] = 16'h02_66; + floor_dist[50] = 16'h02_5a; + floor_dist[51] = 16'h02_4e; + floor_dist[52] = 16'h02_43; + floor_dist[53] = 16'h02_38; + floor_dist[54] = 16'h02_2e; + floor_dist[55] = 16'h02_24; + floor_dist[56] = 16'h02_1a; + floor_dist[57] = 16'h02_11; + floor_dist[58] = 16'h02_08; + floor_dist[59] = 16'h02_00; + floor_dist[60] = 16'h01_f7; + floor_dist[61] = 16'h01_ef; + floor_dist[62] = 16'h01_e7; + floor_dist[63] = 16'h01_e0; + floor_dist[64] = 16'h01_d8; + floor_dist[65] = 16'h01_d1; + floor_dist[66] = 16'h01_ca; + floor_dist[67] = 16'h01_c3; + floor_dist[68] = 16'h01_bd; + floor_dist[69] = 16'h01_b6; + floor_dist[70] = 16'h01_b0; + floor_dist[71] = 16'h01_aa; + floor_dist[72] = 16'h01_a4; + floor_dist[73] = 16'h01_9f; + floor_dist[74] = 16'h01_99; + floor_dist[75] = 16'h01_94; + floor_dist[76] = 16'h01_8e; + floor_dist[77] = 16'h01_89; + floor_dist[78] = 16'h01_84; + floor_dist[79] = 16'h01_80; + floor_dist[80] = 16'h01_7b; + floor_dist[81] = 16'h01_76; + floor_dist[82] = 16'h01_72; + floor_dist[83] = 16'h01_6d; + floor_dist[84] = 16'h01_69; + floor_dist[85] = 16'h01_65; + floor_dist[86] = 16'h01_61; + floor_dist[87] = 16'h01_5d; + floor_dist[88] = 16'h01_59; + floor_dist[89] = 16'h01_55; + floor_dist[90] = 16'h01_51; + floor_dist[91] = 16'h01_4d; + floor_dist[92] = 16'h01_4a; + floor_dist[93] = 16'h01_46; + floor_dist[94] = 16'h01_43; + floor_dist[95] = 16'h01_40; + floor_dist[96] = 16'h01_3c; + floor_dist[97] = 16'h01_39; + floor_dist[98] = 16'h01_36; + floor_dist[99] = 16'h01_33; + floor_dist[100] = 16'h01_30; + floor_dist[101] = 16'h01_2d; + floor_dist[102] = 16'h01_2a; + floor_dist[103] = 16'h01_27; + floor_dist[104] = 16'h01_24; + floor_dist[105] = 16'h01_21; + floor_dist[106] = 16'h01_1f; + floor_dist[107] = 16'h01_1c; + floor_dist[108] = 16'h01_19; + floor_dist[109] = 16'h01_17; + floor_dist[110] = 16'h01_14; + floor_dist[111] = 16'h01_12; + floor_dist[112] = 16'h01_0f; + floor_dist[113] = 16'h01_0d; + floor_dist[114] = 16'h01_0b; + floor_dist[115] = 16'h01_08; + floor_dist[116] = 16'h01_06; + floor_dist[117] = 16'h01_04; + floor_dist[118] = 16'h01_02; + floor_dist[119] = 16'h01_00; diff --git a/src/floordist_rom.v b/src/floordist_rom.v new file mode 100644 index 0000000..618a526 --- /dev/null +++ b/src/floordist_rom.v @@ -0,0 +1,28 @@ +module floordist_rom ( + input clk, + input [8:0] addr, + output [15:0] floordist // Q8.8 + ); + +reg [15:0] floor_dist [119:0]; + +reg [15:0] fd_d, fd_q; + +assign floordist = fd_q; + +initial begin +`include "floordist.rom" +end + +always @(*) begin + if (addr < 8'd120) + fd_d = floor_dist[8'd119 - addr]; + else + fd_d = floor_dist[addr - 8'd119]; +end + +always @(posedge clk) begin + fd_q <= fd_d; +end + +endmodule diff --git a/src/genroms.pl b/src/genroms.pl new file mode 100755 index 0000000..de089fd --- /dev/null +++ b/src/genroms.pl @@ -0,0 +1,162 @@ +#!/usr/bin/perl +# generates the various .rom lookup tables + +use warnings; +use strict; + +my $odir = $ARGV[0] || './'; + +camerax(); +floordist(); +angle(); +idist(); +iheight(); +height(); + +sub height { + # 32 / 1024 (32 == max distance) + # convert distance to wall height. + # FIXME: caps out too early. causes distortion when too close to a wall. + my $fh = outfile('height.rom'); + my $scale = 0.03125; + my $tot = $scale; + for (my $x = 0; $x < 1024; $x++) { + my $cur = int(240 / $tot); + # height + $cur = 238 if ($cur > 238); + # also the Q8.8 inverse of height + my $icur = int((1 / $tot) * 2**8); + # texture scale + my $tscale = int((32 << 8) / $cur); + my $bin = pack('Cnn', $cur, $tscale, $icur); + my $str = hexstr($bin); + + print $fh " heights[$x] = 40'h$str;\n"; + $tot += $scale; + } + close($fh); +} + +sub iheight { + # inverse height for sprite scaler (32 / height) + # wall scaling should really use this table. they cap out too low which + # causes distortion when close to a wall. + my $fh = outfile('iheight.rom'); + for (my $x = 0; $x < 512; $x++) { + # inverse of resultant height for picking pixels + # 32 being the sprite/texture original size. + my $ih = int((32 / ($x != 0 ? $x : 1)) * 2**8); + my $bin = pack('n', $ih); + my $str = hexstr($bin); + + print $fh " iheights[$x] = 16'h$str;\n"; + } + close($fh); +} + +sub idist { + my $fh = outfile('idist.rom'); + # 32 / 1024 (32 == max distance. also the tile/sprite size :P) + my $scale = 0.03125; + my $tot = $scale; + for (my $x = 0; $x < 1024; $x++) { + # Q8.8 inverse of distance + my $icur = int((1 / $tot) * 2**8); + my $bin = pack('n', $icur); + my $str = hexstr($bin); + + print $fh " idists[$x] = 16'h$str;\n"; + $tot += $scale; + } + close($fh); +} + +sub angle { + my $fh = outfile('angle.rom'); + # pre-generated turn angles. This is me avoiding cos/sin/tan/atan tables. + # current camera angle is simply determined by an array position. + my $dirX = -1; + my $dirY = 0; + my $planeX = 0; + my $planeY = 0.66; + my $rotSpeed = 0.050264; # 1 / 60 * 3.0 + + my $inverse = sub { + # for sprite matrix transform. + return 1.0 / ($planeX * $dirY - $dirX * $planeY); + }; + + my $invDet = $inverse->(); + + my $idx = 0; + + my $binpack = sub { + my $bin = pack('nnnnn', int($dirX * (2**8)), + int($dirY * (2**8)), + int($planeX * (2**8)), + int($planeY * (2**8)), + int($invDet * (2**8))); + my $str = hexstr($bin); + # too lazy to batch by 2 but this looks better than them all mashed up. + printf $fh " angles[$idx] = 80'h$str;\n"; + $idx++; + }; + + $binpack->(); + + # FIXME: reverse? meh. + for (my $x = 0; $x < 125; $x++) { + my $ox = $dirX; + $dirX = $dirX * cos(-$rotSpeed) - $dirY * sin(-$rotSpeed); + $dirY = $ox * sin(-$rotSpeed) + $dirY * cos(-$rotSpeed); + my $opx = $planeX; + $planeX = $planeX * cos(-$rotSpeed) - $planeY * sin(-$rotSpeed); + $planeY = $opx * sin(-$rotSpeed) + $planeY * cos(-$rotSpeed); + $invDet = $inverse->(); + + $binpack->(); + } + close($fh); +} + +sub floordist { + # similar inverse distance for floor heights. + # table is halved since it's mirrored 0-119 and 120-240 + my $fh = outfile('floordist.rom'); + for (my $x = 121; $x <= 240; $x++) { + my $cur = eval{240 / (2.0 * $x - 240)}; + my $bin = pack('n', int($cur * 2**8)); + my $str = hexstr($bin); + + my $off = $x - 121; + print $fh " floor_dist[$off] = 16'h$str;\n"; + } + + close($fh); +} + +sub camerax { + # generates an inverse range -1 to 1 over the width of the screen. + my $fh = outfile('camerax.rom'); + for (my $x = 0; $x < 320; $x++) { + my $cur = 2 * $x / 320 - 1; + my $bin = pack('n', int($cur * 2**8)); + my $str = hexstr($bin); + + print $fh " camerax_pos[$x] = 16'h$str;\n"; + } + close($fh); +} + +sub hexstr { + my $b = shift; + my $str = join("", map { sprintf("%02x_", ord($_)) } split(//, $b)); + chop($str); + return $str; +} + +sub outfile { + my $f = shift; + open(my $fh, "> $odir/$f") or die "couldn't open: $odir/$f for writing: $!"; + return $fh; +} diff --git a/src/height.rom b/src/height.rom new file mode 100644 index 0000000..32d373e --- /dev/null +++ b/src/height.rom @@ -0,0 +1,1024 @@ + heights[0] = 40'hee_00_22_20_00; + heights[1] = 40'hee_00_22_10_00; + heights[2] = 40'hee_00_22_0a_aa; + heights[3] = 40'hee_00_22_08_00; + heights[4] = 40'hee_00_22_06_66; + heights[5] = 40'hee_00_22_05_55; + heights[6] = 40'hee_00_22_04_92; + heights[7] = 40'hee_00_22_04_00; + heights[8] = 40'hee_00_22_03_8e; + heights[9] = 40'hee_00_22_03_33; + heights[10] = 40'hee_00_22_02_e8; + heights[11] = 40'hee_00_22_02_aa; + heights[12] = 40'hee_00_22_02_76; + heights[13] = 40'hee_00_22_02_49; + heights[14] = 40'hee_00_22_02_22; + heights[15] = 40'hee_00_22_02_00; + heights[16] = 40'hee_00_22_01_e1; + heights[17] = 40'hee_00_22_01_c7; + heights[18] = 40'hee_00_22_01_af; + heights[19] = 40'hee_00_22_01_99; + heights[20] = 40'hee_00_22_01_86; + heights[21] = 40'hee_00_22_01_74; + heights[22] = 40'hee_00_22_01_64; + heights[23] = 40'hee_00_22_01_55; + heights[24] = 40'hee_00_22_01_47; + heights[25] = 40'hee_00_22_01_3b; + heights[26] = 40'hee_00_22_01_2f; + heights[27] = 40'hee_00_22_01_24; + heights[28] = 40'hee_00_22_01_1a; + heights[29] = 40'hee_00_22_01_11; + heights[30] = 40'hee_00_22_01_08; + heights[31] = 40'hee_00_22_01_00; + heights[32] = 40'he8_00_23_00_f8; + heights[33] = 40'he1_00_24_00_f0; + heights[34] = 40'hdb_00_25_00_ea; + heights[35] = 40'hd5_00_26_00_e3; + heights[36] = 40'hcf_00_27_00_dd; + heights[37] = 40'hca_00_28_00_d7; + heights[38] = 40'hc4_00_29_00_d2; + heights[39] = 40'hc0_00_2a_00_cc; + heights[40] = 40'hbb_00_2b_00_c7; + heights[41] = 40'hb6_00_2d_00_c3; + heights[42] = 40'hb2_00_2e_00_be; + heights[43] = 40'hae_00_2f_00_ba; + heights[44] = 40'haa_00_30_00_b6; + heights[45] = 40'ha6_00_31_00_b2; + heights[46] = 40'ha3_00_32_00_ae; + heights[47] = 40'ha0_00_33_00_aa; + heights[48] = 40'h9c_00_34_00_a7; + heights[49] = 40'h99_00_35_00_a3; + heights[50] = 40'h96_00_36_00_a0; + heights[51] = 40'h93_00_37_00_9d; + heights[52] = 40'h90_00_38_00_9a; + heights[53] = 40'h8e_00_39_00_97; + heights[54] = 40'h8b_00_3a_00_94; + heights[55] = 40'h89_00_3b_00_92; + heights[56] = 40'h86_00_3d_00_8f; + heights[57] = 40'h84_00_3e_00_8d; + heights[58] = 40'h82_00_3f_00_8a; + heights[59] = 40'h80_00_40_00_88; + heights[60] = 40'h7d_00_41_00_86; + heights[61] = 40'h7b_00_42_00_84; + heights[62] = 40'h79_00_43_00_82; + heights[63] = 40'h78_00_44_00_80; + heights[64] = 40'h76_00_45_00_7e; + heights[65] = 40'h74_00_46_00_7c; + heights[66] = 40'h72_00_47_00_7a; + heights[67] = 40'h70_00_49_00_78; + heights[68] = 40'h6f_00_49_00_76; + heights[69] = 40'h6d_00_4b_00_75; + heights[70] = 40'h6c_00_4b_00_73; + heights[71] = 40'h6a_00_4d_00_71; + heights[72] = 40'h69_00_4e_00_70; + heights[73] = 40'h67_00_4f_00_6e; + heights[74] = 40'h66_00_50_00_6d; + heights[75] = 40'h65_00_51_00_6b; + heights[76] = 40'h63_00_52_00_6a; + heights[77] = 40'h62_00_53_00_69; + heights[78] = 40'h61_00_54_00_67; + heights[79] = 40'h60_00_55_00_66; + heights[80] = 40'h5e_00_57_00_65; + heights[81] = 40'h5d_00_58_00_63; + heights[82] = 40'h5c_00_59_00_62; + heights[83] = 40'h5b_00_5a_00_61; + heights[84] = 40'h5a_00_5b_00_60; + heights[85] = 40'h59_00_5c_00_5f; + heights[86] = 40'h58_00_5d_00_5e; + heights[87] = 40'h57_00_5e_00_5d; + heights[88] = 40'h56_00_5f_00_5c; + heights[89] = 40'h55_00_60_00_5b; + heights[90] = 40'h54_00_61_00_5a; + heights[91] = 40'h53_00_62_00_59; + heights[92] = 40'h52_00_63_00_58; + heights[93] = 40'h51_00_65_00_57; + heights[94] = 40'h50_00_66_00_56; + heights[95] = 40'h50_00_66_00_55; + heights[96] = 40'h4f_00_67_00_54; + heights[97] = 40'h4e_00_69_00_53; + heights[98] = 40'h4d_00_6a_00_52; + heights[99] = 40'h4c_00_6b_00_51; + heights[100] = 40'h4c_00_6b_00_51; + heights[101] = 40'h4b_00_6d_00_50; + heights[102] = 40'h4a_00_6e_00_4f; + heights[103] = 40'h49_00_70_00_4e; + heights[104] = 40'h49_00_70_00_4e; + heights[105] = 40'h48_00_71_00_4d; + heights[106] = 40'h47_00_73_00_4c; + heights[107] = 40'h47_00_73_00_4b; + heights[108] = 40'h46_00_75_00_4b; + heights[109] = 40'h45_00_76_00_4a; + heights[110] = 40'h45_00_76_00_49; + heights[111] = 40'h44_00_78_00_49; + heights[112] = 40'h43_00_7a_00_48; + heights[113] = 40'h43_00_7a_00_47; + heights[114] = 40'h42_00_7c_00_47; + heights[115] = 40'h42_00_7c_00_46; + heights[116] = 40'h41_00_7e_00_46; + heights[117] = 40'h41_00_7e_00_45; + heights[118] = 40'h40_00_80_00_44; + heights[119] = 40'h40_00_80_00_44; + heights[120] = 40'h3f_00_82_00_43; + heights[121] = 40'h3e_00_84_00_43; + heights[122] = 40'h3e_00_84_00_42; + heights[123] = 40'h3d_00_86_00_42; + heights[124] = 40'h3d_00_86_00_41; + heights[125] = 40'h3c_00_88_00_41; + heights[126] = 40'h3c_00_88_00_40; + heights[127] = 40'h3c_00_88_00_40; + heights[128] = 40'h3b_00_8a_00_3f; + heights[129] = 40'h3b_00_8a_00_3f; + heights[130] = 40'h3a_00_8d_00_3e; + heights[131] = 40'h3a_00_8d_00_3e; + heights[132] = 40'h39_00_8f_00_3d; + heights[133] = 40'h39_00_8f_00_3d; + heights[134] = 40'h38_00_92_00_3c; + heights[135] = 40'h38_00_92_00_3c; + heights[136] = 40'h38_00_92_00_3b; + heights[137] = 40'h37_00_94_00_3b; + heights[138] = 40'h37_00_94_00_3a; + heights[139] = 40'h36_00_97_00_3a; + heights[140] = 40'h36_00_97_00_3a; + heights[141] = 40'h36_00_97_00_39; + heights[142] = 40'h35_00_9a_00_39; + heights[143] = 40'h35_00_9a_00_38; + heights[144] = 40'h34_00_9d_00_38; + heights[145] = 40'h34_00_9d_00_38; + heights[146] = 40'h34_00_9d_00_37; + heights[147] = 40'h33_00_a0_00_37; + heights[148] = 40'h33_00_a0_00_36; + heights[149] = 40'h33_00_a0_00_36; + heights[150] = 40'h32_00_a3_00_36; + heights[151] = 40'h32_00_a3_00_35; + heights[152] = 40'h32_00_a3_00_35; + heights[153] = 40'h31_00_a7_00_35; + heights[154] = 40'h31_00_a7_00_34; + heights[155] = 40'h31_00_a7_00_34; + heights[156] = 40'h30_00_aa_00_34; + heights[157] = 40'h30_00_aa_00_33; + heights[158] = 40'h30_00_aa_00_33; + heights[159] = 40'h30_00_aa_00_33; + heights[160] = 40'h2f_00_ae_00_32; + heights[161] = 40'h2f_00_ae_00_32; + heights[162] = 40'h2f_00_ae_00_32; + heights[163] = 40'h2e_00_b2_00_31; + heights[164] = 40'h2e_00_b2_00_31; + heights[165] = 40'h2e_00_b2_00_31; + heights[166] = 40'h2d_00_b6_00_31; + heights[167] = 40'h2d_00_b6_00_30; + heights[168] = 40'h2d_00_b6_00_30; + heights[169] = 40'h2d_00_b6_00_30; + heights[170] = 40'h2c_00_ba_00_2f; + heights[171] = 40'h2c_00_ba_00_2f; + heights[172] = 40'h2c_00_ba_00_2f; + heights[173] = 40'h2c_00_ba_00_2f; + heights[174] = 40'h2b_00_be_00_2e; + heights[175] = 40'h2b_00_be_00_2e; + heights[176] = 40'h2b_00_be_00_2e; + heights[177] = 40'h2b_00_be_00_2e; + heights[178] = 40'h2a_00_c3_00_2d; + heights[179] = 40'h2a_00_c3_00_2d; + heights[180] = 40'h2a_00_c3_00_2d; + heights[181] = 40'h2a_00_c3_00_2d; + heights[182] = 40'h29_00_c7_00_2c; + heights[183] = 40'h29_00_c7_00_2c; + heights[184] = 40'h29_00_c7_00_2c; + heights[185] = 40'h29_00_c7_00_2c; + heights[186] = 40'h29_00_c7_00_2b; + heights[187] = 40'h28_00_cc_00_2b; + heights[188] = 40'h28_00_cc_00_2b; + heights[189] = 40'h28_00_cc_00_2b; + heights[190] = 40'h28_00_cc_00_2a; + heights[191] = 40'h28_00_cc_00_2a; + heights[192] = 40'h27_00_d2_00_2a; + heights[193] = 40'h27_00_d2_00_2a; + heights[194] = 40'h27_00_d2_00_2a; + heights[195] = 40'h27_00_d2_00_29; + heights[196] = 40'h26_00_d7_00_29; + heights[197] = 40'h26_00_d7_00_29; + heights[198] = 40'h26_00_d7_00_29; + heights[199] = 40'h26_00_d7_00_28; + heights[200] = 40'h26_00_d7_00_28; + heights[201] = 40'h26_00_d7_00_28; + heights[202] = 40'h25_00_dd_00_28; + heights[203] = 40'h25_00_dd_00_28; + heights[204] = 40'h25_00_dd_00_27; + heights[205] = 40'h25_00_dd_00_27; + heights[206] = 40'h25_00_dd_00_27; + heights[207] = 40'h24_00_e3_00_27; + heights[208] = 40'h24_00_e3_00_27; + heights[209] = 40'h24_00_e3_00_27; + heights[210] = 40'h24_00_e3_00_26; + heights[211] = 40'h24_00_e3_00_26; + heights[212] = 40'h24_00_e3_00_26; + heights[213] = 40'h23_00_ea_00_26; + heights[214] = 40'h23_00_ea_00_26; + heights[215] = 40'h23_00_ea_00_25; + heights[216] = 40'h23_00_ea_00_25; + heights[217] = 40'h23_00_ea_00_25; + heights[218] = 40'h23_00_ea_00_25; + heights[219] = 40'h22_00_f0_00_25; + heights[220] = 40'h22_00_f0_00_25; + heights[221] = 40'h22_00_f0_00_24; + heights[222] = 40'h22_00_f0_00_24; + heights[223] = 40'h22_00_f0_00_24; + heights[224] = 40'h22_00_f0_00_24; + heights[225] = 40'h21_00_f8_00_24; + heights[226] = 40'h21_00_f8_00_24; + heights[227] = 40'h21_00_f8_00_23; + heights[228] = 40'h21_00_f8_00_23; + heights[229] = 40'h21_00_f8_00_23; + heights[230] = 40'h21_00_f8_00_23; + heights[231] = 40'h21_00_f8_00_23; + heights[232] = 40'h20_01_00_00_23; + heights[233] = 40'h20_01_00_00_23; + heights[234] = 40'h20_01_00_00_22; + heights[235] = 40'h20_01_00_00_22; + heights[236] = 40'h20_01_00_00_22; + heights[237] = 40'h20_01_00_00_22; + heights[238] = 40'h20_01_00_00_22; + heights[239] = 40'h20_01_00_00_22; + heights[240] = 40'h1f_01_08_00_21; + heights[241] = 40'h1f_01_08_00_21; + heights[242] = 40'h1f_01_08_00_21; + heights[243] = 40'h1f_01_08_00_21; + heights[244] = 40'h1f_01_08_00_21; + heights[245] = 40'h1f_01_08_00_21; + heights[246] = 40'h1f_01_08_00_21; + heights[247] = 40'h1e_01_11_00_21; + heights[248] = 40'h1e_01_11_00_20; + heights[249] = 40'h1e_01_11_00_20; + heights[250] = 40'h1e_01_11_00_20; + heights[251] = 40'h1e_01_11_00_20; + heights[252] = 40'h1e_01_11_00_20; + heights[253] = 40'h1e_01_11_00_20; + heights[254] = 40'h1e_01_11_00_20; + heights[255] = 40'h1e_01_11_00_20; + heights[256] = 40'h1d_01_1a_00_1f; + heights[257] = 40'h1d_01_1a_00_1f; + heights[258] = 40'h1d_01_1a_00_1f; + heights[259] = 40'h1d_01_1a_00_1f; + heights[260] = 40'h1d_01_1a_00_1f; + heights[261] = 40'h1d_01_1a_00_1f; + heights[262] = 40'h1d_01_1a_00_1f; + heights[263] = 40'h1d_01_1a_00_1f; + heights[264] = 40'h1c_01_24_00_1e; + heights[265] = 40'h1c_01_24_00_1e; + heights[266] = 40'h1c_01_24_00_1e; + heights[267] = 40'h1c_01_24_00_1e; + heights[268] = 40'h1c_01_24_00_1e; + heights[269] = 40'h1c_01_24_00_1e; + heights[270] = 40'h1c_01_24_00_1e; + heights[271] = 40'h1c_01_24_00_1e; + heights[272] = 40'h1c_01_24_00_1e; + heights[273] = 40'h1c_01_24_00_1d; + heights[274] = 40'h1b_01_2f_00_1d; + heights[275] = 40'h1b_01_2f_00_1d; + heights[276] = 40'h1b_01_2f_00_1d; + heights[277] = 40'h1b_01_2f_00_1d; + heights[278] = 40'h1b_01_2f_00_1d; + heights[279] = 40'h1b_01_2f_00_1d; + heights[280] = 40'h1b_01_2f_00_1d; + heights[281] = 40'h1b_01_2f_00_1d; + heights[282] = 40'h1b_01_2f_00_1c; + heights[283] = 40'h1b_01_2f_00_1c; + heights[284] = 40'h1a_01_3b_00_1c; + heights[285] = 40'h1a_01_3b_00_1c; + heights[286] = 40'h1a_01_3b_00_1c; + heights[287] = 40'h1a_01_3b_00_1c; + heights[288] = 40'h1a_01_3b_00_1c; + heights[289] = 40'h1a_01_3b_00_1c; + heights[290] = 40'h1a_01_3b_00_1c; + heights[291] = 40'h1a_01_3b_00_1c; + heights[292] = 40'h1a_01_3b_00_1b; + heights[293] = 40'h1a_01_3b_00_1b; + heights[294] = 40'h1a_01_3b_00_1b; + heights[295] = 40'h19_01_47_00_1b; + heights[296] = 40'h19_01_47_00_1b; + heights[297] = 40'h19_01_47_00_1b; + heights[298] = 40'h19_01_47_00_1b; + heights[299] = 40'h19_01_47_00_1b; + heights[300] = 40'h19_01_47_00_1b; + heights[301] = 40'h19_01_47_00_1b; + heights[302] = 40'h19_01_47_00_1b; + heights[303] = 40'h19_01_47_00_1a; + heights[304] = 40'h19_01_47_00_1a; + heights[305] = 40'h19_01_47_00_1a; + heights[306] = 40'h19_01_47_00_1a; + heights[307] = 40'h18_01_55_00_1a; + heights[308] = 40'h18_01_55_00_1a; + heights[309] = 40'h18_01_55_00_1a; + heights[310] = 40'h18_01_55_00_1a; + heights[311] = 40'h18_01_55_00_1a; + heights[312] = 40'h18_01_55_00_1a; + heights[313] = 40'h18_01_55_00_1a; + heights[314] = 40'h18_01_55_00_1a; + heights[315] = 40'h18_01_55_00_19; + heights[316] = 40'h18_01_55_00_19; + heights[317] = 40'h18_01_55_00_19; + heights[318] = 40'h18_01_55_00_19; + heights[319] = 40'h18_01_55_00_19; + heights[320] = 40'h17_01_64_00_19; + heights[321] = 40'h17_01_64_00_19; + heights[322] = 40'h17_01_64_00_19; + heights[323] = 40'h17_01_64_00_19; + heights[324] = 40'h17_01_64_00_19; + heights[325] = 40'h17_01_64_00_19; + heights[326] = 40'h17_01_64_00_19; + heights[327] = 40'h17_01_64_00_18; + heights[328] = 40'h17_01_64_00_18; + heights[329] = 40'h17_01_64_00_18; + heights[330] = 40'h17_01_64_00_18; + heights[331] = 40'h17_01_64_00_18; + heights[332] = 40'h17_01_64_00_18; + heights[333] = 40'h16_01_74_00_18; + heights[334] = 40'h16_01_74_00_18; + heights[335] = 40'h16_01_74_00_18; + heights[336] = 40'h16_01_74_00_18; + heights[337] = 40'h16_01_74_00_18; + heights[338] = 40'h16_01_74_00_18; + heights[339] = 40'h16_01_74_00_18; + heights[340] = 40'h16_01_74_00_18; + heights[341] = 40'h16_01_74_00_17; + heights[342] = 40'h16_01_74_00_17; + heights[343] = 40'h16_01_74_00_17; + heights[344] = 40'h16_01_74_00_17; + heights[345] = 40'h16_01_74_00_17; + heights[346] = 40'h16_01_74_00_17; + heights[347] = 40'h16_01_74_00_17; + heights[348] = 40'h16_01_74_00_17; + heights[349] = 40'h15_01_86_00_17; + heights[350] = 40'h15_01_86_00_17; + heights[351] = 40'h15_01_86_00_17; + heights[352] = 40'h15_01_86_00_17; + heights[353] = 40'h15_01_86_00_17; + heights[354] = 40'h15_01_86_00_17; + heights[355] = 40'h15_01_86_00_17; + heights[356] = 40'h15_01_86_00_16; + heights[357] = 40'h15_01_86_00_16; + heights[358] = 40'h15_01_86_00_16; + heights[359] = 40'h15_01_86_00_16; + heights[360] = 40'h15_01_86_00_16; + heights[361] = 40'h15_01_86_00_16; + heights[362] = 40'h15_01_86_00_16; + heights[363] = 40'h15_01_86_00_16; + heights[364] = 40'h15_01_86_00_16; + heights[365] = 40'h14_01_99_00_16; + heights[366] = 40'h14_01_99_00_16; + heights[367] = 40'h14_01_99_00_16; + heights[368] = 40'h14_01_99_00_16; + heights[369] = 40'h14_01_99_00_16; + heights[370] = 40'h14_01_99_00_16; + heights[371] = 40'h14_01_99_00_16; + heights[372] = 40'h14_01_99_00_15; + heights[373] = 40'h14_01_99_00_15; + heights[374] = 40'h14_01_99_00_15; + heights[375] = 40'h14_01_99_00_15; + heights[376] = 40'h14_01_99_00_15; + heights[377] = 40'h14_01_99_00_15; + heights[378] = 40'h14_01_99_00_15; + heights[379] = 40'h14_01_99_00_15; + heights[380] = 40'h14_01_99_00_15; + heights[381] = 40'h14_01_99_00_15; + heights[382] = 40'h14_01_99_00_15; + heights[383] = 40'h14_01_99_00_15; + heights[384] = 40'h13_01_af_00_15; + heights[385] = 40'h13_01_af_00_15; + heights[386] = 40'h13_01_af_00_15; + heights[387] = 40'h13_01_af_00_15; + heights[388] = 40'h13_01_af_00_15; + heights[389] = 40'h13_01_af_00_15; + heights[390] = 40'h13_01_af_00_14; + heights[391] = 40'h13_01_af_00_14; + heights[392] = 40'h13_01_af_00_14; + heights[393] = 40'h13_01_af_00_14; + heights[394] = 40'h13_01_af_00_14; + heights[395] = 40'h13_01_af_00_14; + heights[396] = 40'h13_01_af_00_14; + heights[397] = 40'h13_01_af_00_14; + heights[398] = 40'h13_01_af_00_14; + heights[399] = 40'h13_01_af_00_14; + heights[400] = 40'h13_01_af_00_14; + heights[401] = 40'h13_01_af_00_14; + heights[402] = 40'h13_01_af_00_14; + heights[403] = 40'h13_01_af_00_14; + heights[404] = 40'h12_01_c7_00_14; + heights[405] = 40'h12_01_c7_00_14; + heights[406] = 40'h12_01_c7_00_14; + heights[407] = 40'h12_01_c7_00_14; + heights[408] = 40'h12_01_c7_00_14; + heights[409] = 40'h12_01_c7_00_13; + heights[410] = 40'h12_01_c7_00_13; + heights[411] = 40'h12_01_c7_00_13; + heights[412] = 40'h12_01_c7_00_13; + heights[413] = 40'h12_01_c7_00_13; + heights[414] = 40'h12_01_c7_00_13; + heights[415] = 40'h12_01_c7_00_13; + heights[416] = 40'h12_01_c7_00_13; + heights[417] = 40'h12_01_c7_00_13; + heights[418] = 40'h12_01_c7_00_13; + heights[419] = 40'h12_01_c7_00_13; + heights[420] = 40'h12_01_c7_00_13; + heights[421] = 40'h12_01_c7_00_13; + heights[422] = 40'h12_01_c7_00_13; + heights[423] = 40'h12_01_c7_00_13; + heights[424] = 40'h12_01_c7_00_13; + heights[425] = 40'h12_01_c7_00_13; + heights[426] = 40'h11_01_e1_00_13; + heights[427] = 40'h11_01_e1_00_13; + heights[428] = 40'h11_01_e1_00_13; + heights[429] = 40'h11_01_e1_00_13; + heights[430] = 40'h11_01_e1_00_13; + heights[431] = 40'h11_01_e1_00_12; + heights[432] = 40'h11_01_e1_00_12; + heights[433] = 40'h11_01_e1_00_12; + heights[434] = 40'h11_01_e1_00_12; + heights[435] = 40'h11_01_e1_00_12; + heights[436] = 40'h11_01_e1_00_12; + heights[437] = 40'h11_01_e1_00_12; + heights[438] = 40'h11_01_e1_00_12; + heights[439] = 40'h11_01_e1_00_12; + heights[440] = 40'h11_01_e1_00_12; + heights[441] = 40'h11_01_e1_00_12; + heights[442] = 40'h11_01_e1_00_12; + heights[443] = 40'h11_01_e1_00_12; + heights[444] = 40'h11_01_e1_00_12; + heights[445] = 40'h11_01_e1_00_12; + heights[446] = 40'h11_01_e1_00_12; + heights[447] = 40'h11_01_e1_00_12; + heights[448] = 40'h11_01_e1_00_12; + heights[449] = 40'h11_01_e1_00_12; + heights[450] = 40'h11_01_e1_00_12; + heights[451] = 40'h10_02_00_00_12; + heights[452] = 40'h10_02_00_00_12; + heights[453] = 40'h10_02_00_00_12; + heights[454] = 40'h10_02_00_00_12; + heights[455] = 40'h10_02_00_00_11; + heights[456] = 40'h10_02_00_00_11; + heights[457] = 40'h10_02_00_00_11; + heights[458] = 40'h10_02_00_00_11; + heights[459] = 40'h10_02_00_00_11; + heights[460] = 40'h10_02_00_00_11; + heights[461] = 40'h10_02_00_00_11; + heights[462] = 40'h10_02_00_00_11; + heights[463] = 40'h10_02_00_00_11; + heights[464] = 40'h10_02_00_00_11; + heights[465] = 40'h10_02_00_00_11; + heights[466] = 40'h10_02_00_00_11; + heights[467] = 40'h10_02_00_00_11; + heights[468] = 40'h10_02_00_00_11; + heights[469] = 40'h10_02_00_00_11; + heights[470] = 40'h10_02_00_00_11; + heights[471] = 40'h10_02_00_00_11; + heights[472] = 40'h10_02_00_00_11; + heights[473] = 40'h10_02_00_00_11; + heights[474] = 40'h10_02_00_00_11; + heights[475] = 40'h10_02_00_00_11; + heights[476] = 40'h10_02_00_00_11; + heights[477] = 40'h10_02_00_00_11; + heights[478] = 40'h10_02_00_00_11; + heights[479] = 40'h10_02_00_00_11; + heights[480] = 40'h0f_02_22_00_11; + heights[481] = 40'h0f_02_22_00_10; + heights[482] = 40'h0f_02_22_00_10; + heights[483] = 40'h0f_02_22_00_10; + heights[484] = 40'h0f_02_22_00_10; + heights[485] = 40'h0f_02_22_00_10; + heights[486] = 40'h0f_02_22_00_10; + heights[487] = 40'h0f_02_22_00_10; + heights[488] = 40'h0f_02_22_00_10; + heights[489] = 40'h0f_02_22_00_10; + heights[490] = 40'h0f_02_22_00_10; + heights[491] = 40'h0f_02_22_00_10; + heights[492] = 40'h0f_02_22_00_10; + heights[493] = 40'h0f_02_22_00_10; + heights[494] = 40'h0f_02_22_00_10; + heights[495] = 40'h0f_02_22_00_10; + heights[496] = 40'h0f_02_22_00_10; + heights[497] = 40'h0f_02_22_00_10; + heights[498] = 40'h0f_02_22_00_10; + heights[499] = 40'h0f_02_22_00_10; + heights[500] = 40'h0f_02_22_00_10; + heights[501] = 40'h0f_02_22_00_10; + heights[502] = 40'h0f_02_22_00_10; + heights[503] = 40'h0f_02_22_00_10; + heights[504] = 40'h0f_02_22_00_10; + heights[505] = 40'h0f_02_22_00_10; + heights[506] = 40'h0f_02_22_00_10; + heights[507] = 40'h0f_02_22_00_10; + heights[508] = 40'h0f_02_22_00_10; + heights[509] = 40'h0f_02_22_00_10; + heights[510] = 40'h0f_02_22_00_10; + heights[511] = 40'h0f_02_22_00_10; + heights[512] = 40'h0e_02_49_00_0f; + heights[513] = 40'h0e_02_49_00_0f; + heights[514] = 40'h0e_02_49_00_0f; + heights[515] = 40'h0e_02_49_00_0f; + heights[516] = 40'h0e_02_49_00_0f; + heights[517] = 40'h0e_02_49_00_0f; + heights[518] = 40'h0e_02_49_00_0f; + heights[519] = 40'h0e_02_49_00_0f; + heights[520] = 40'h0e_02_49_00_0f; + heights[521] = 40'h0e_02_49_00_0f; + heights[522] = 40'h0e_02_49_00_0f; + heights[523] = 40'h0e_02_49_00_0f; + heights[524] = 40'h0e_02_49_00_0f; + heights[525] = 40'h0e_02_49_00_0f; + heights[526] = 40'h0e_02_49_00_0f; + heights[527] = 40'h0e_02_49_00_0f; + heights[528] = 40'h0e_02_49_00_0f; + heights[529] = 40'h0e_02_49_00_0f; + heights[530] = 40'h0e_02_49_00_0f; + heights[531] = 40'h0e_02_49_00_0f; + heights[532] = 40'h0e_02_49_00_0f; + heights[533] = 40'h0e_02_49_00_0f; + heights[534] = 40'h0e_02_49_00_0f; + heights[535] = 40'h0e_02_49_00_0f; + heights[536] = 40'h0e_02_49_00_0f; + heights[537] = 40'h0e_02_49_00_0f; + heights[538] = 40'h0e_02_49_00_0f; + heights[539] = 40'h0e_02_49_00_0f; + heights[540] = 40'h0e_02_49_00_0f; + heights[541] = 40'h0e_02_49_00_0f; + heights[542] = 40'h0e_02_49_00_0f; + heights[543] = 40'h0e_02_49_00_0f; + heights[544] = 40'h0e_02_49_00_0f; + heights[545] = 40'h0e_02_49_00_0f; + heights[546] = 40'h0e_02_49_00_0e; + heights[547] = 40'h0e_02_49_00_0e; + heights[548] = 40'h0d_02_76_00_0e; + heights[549] = 40'h0d_02_76_00_0e; + heights[550] = 40'h0d_02_76_00_0e; + heights[551] = 40'h0d_02_76_00_0e; + heights[552] = 40'h0d_02_76_00_0e; + heights[553] = 40'h0d_02_76_00_0e; + heights[554] = 40'h0d_02_76_00_0e; + heights[555] = 40'h0d_02_76_00_0e; + heights[556] = 40'h0d_02_76_00_0e; + heights[557] = 40'h0d_02_76_00_0e; + heights[558] = 40'h0d_02_76_00_0e; + heights[559] = 40'h0d_02_76_00_0e; + heights[560] = 40'h0d_02_76_00_0e; + heights[561] = 40'h0d_02_76_00_0e; + heights[562] = 40'h0d_02_76_00_0e; + heights[563] = 40'h0d_02_76_00_0e; + heights[564] = 40'h0d_02_76_00_0e; + heights[565] = 40'h0d_02_76_00_0e; + heights[566] = 40'h0d_02_76_00_0e; + heights[567] = 40'h0d_02_76_00_0e; + heights[568] = 40'h0d_02_76_00_0e; + heights[569] = 40'h0d_02_76_00_0e; + heights[570] = 40'h0d_02_76_00_0e; + heights[571] = 40'h0d_02_76_00_0e; + heights[572] = 40'h0d_02_76_00_0e; + heights[573] = 40'h0d_02_76_00_0e; + heights[574] = 40'h0d_02_76_00_0e; + heights[575] = 40'h0d_02_76_00_0e; + heights[576] = 40'h0d_02_76_00_0e; + heights[577] = 40'h0d_02_76_00_0e; + heights[578] = 40'h0d_02_76_00_0e; + heights[579] = 40'h0d_02_76_00_0e; + heights[580] = 40'h0d_02_76_00_0e; + heights[581] = 40'h0d_02_76_00_0e; + heights[582] = 40'h0d_02_76_00_0e; + heights[583] = 40'h0d_02_76_00_0e; + heights[584] = 40'h0d_02_76_00_0e; + heights[585] = 40'h0d_02_76_00_0d; + heights[586] = 40'h0d_02_76_00_0d; + heights[587] = 40'h0d_02_76_00_0d; + heights[588] = 40'h0d_02_76_00_0d; + heights[589] = 40'h0d_02_76_00_0d; + heights[590] = 40'h0c_02_aa_00_0d; + heights[591] = 40'h0c_02_aa_00_0d; + heights[592] = 40'h0c_02_aa_00_0d; + heights[593] = 40'h0c_02_aa_00_0d; + heights[594] = 40'h0c_02_aa_00_0d; + heights[595] = 40'h0c_02_aa_00_0d; + heights[596] = 40'h0c_02_aa_00_0d; + heights[597] = 40'h0c_02_aa_00_0d; + heights[598] = 40'h0c_02_aa_00_0d; + heights[599] = 40'h0c_02_aa_00_0d; + heights[600] = 40'h0c_02_aa_00_0d; + heights[601] = 40'h0c_02_aa_00_0d; + heights[602] = 40'h0c_02_aa_00_0d; + heights[603] = 40'h0c_02_aa_00_0d; + heights[604] = 40'h0c_02_aa_00_0d; + heights[605] = 40'h0c_02_aa_00_0d; + heights[606] = 40'h0c_02_aa_00_0d; + heights[607] = 40'h0c_02_aa_00_0d; + heights[608] = 40'h0c_02_aa_00_0d; + heights[609] = 40'h0c_02_aa_00_0d; + heights[610] = 40'h0c_02_aa_00_0d; + heights[611] = 40'h0c_02_aa_00_0d; + heights[612] = 40'h0c_02_aa_00_0d; + heights[613] = 40'h0c_02_aa_00_0d; + heights[614] = 40'h0c_02_aa_00_0d; + heights[615] = 40'h0c_02_aa_00_0d; + heights[616] = 40'h0c_02_aa_00_0d; + heights[617] = 40'h0c_02_aa_00_0d; + heights[618] = 40'h0c_02_aa_00_0d; + heights[619] = 40'h0c_02_aa_00_0d; + heights[620] = 40'h0c_02_aa_00_0d; + heights[621] = 40'h0c_02_aa_00_0d; + heights[622] = 40'h0c_02_aa_00_0d; + heights[623] = 40'h0c_02_aa_00_0d; + heights[624] = 40'h0c_02_aa_00_0d; + heights[625] = 40'h0c_02_aa_00_0d; + heights[626] = 40'h0c_02_aa_00_0d; + heights[627] = 40'h0c_02_aa_00_0d; + heights[628] = 40'h0c_02_aa_00_0d; + heights[629] = 40'h0c_02_aa_00_0d; + heights[630] = 40'h0c_02_aa_00_0c; + heights[631] = 40'h0c_02_aa_00_0c; + heights[632] = 40'h0c_02_aa_00_0c; + heights[633] = 40'h0c_02_aa_00_0c; + heights[634] = 40'h0c_02_aa_00_0c; + heights[635] = 40'h0c_02_aa_00_0c; + heights[636] = 40'h0c_02_aa_00_0c; + heights[637] = 40'h0c_02_aa_00_0c; + heights[638] = 40'h0c_02_aa_00_0c; + heights[639] = 40'h0c_02_aa_00_0c; + heights[640] = 40'h0b_02_e8_00_0c; + heights[641] = 40'h0b_02_e8_00_0c; + heights[642] = 40'h0b_02_e8_00_0c; + heights[643] = 40'h0b_02_e8_00_0c; + heights[644] = 40'h0b_02_e8_00_0c; + heights[645] = 40'h0b_02_e8_00_0c; + heights[646] = 40'h0b_02_e8_00_0c; + heights[647] = 40'h0b_02_e8_00_0c; + heights[648] = 40'h0b_02_e8_00_0c; + heights[649] = 40'h0b_02_e8_00_0c; + heights[650] = 40'h0b_02_e8_00_0c; + heights[651] = 40'h0b_02_e8_00_0c; + heights[652] = 40'h0b_02_e8_00_0c; + heights[653] = 40'h0b_02_e8_00_0c; + heights[654] = 40'h0b_02_e8_00_0c; + heights[655] = 40'h0b_02_e8_00_0c; + heights[656] = 40'h0b_02_e8_00_0c; + heights[657] = 40'h0b_02_e8_00_0c; + heights[658] = 40'h0b_02_e8_00_0c; + heights[659] = 40'h0b_02_e8_00_0c; + heights[660] = 40'h0b_02_e8_00_0c; + heights[661] = 40'h0b_02_e8_00_0c; + heights[662] = 40'h0b_02_e8_00_0c; + heights[663] = 40'h0b_02_e8_00_0c; + heights[664] = 40'h0b_02_e8_00_0c; + heights[665] = 40'h0b_02_e8_00_0c; + heights[666] = 40'h0b_02_e8_00_0c; + heights[667] = 40'h0b_02_e8_00_0c; + heights[668] = 40'h0b_02_e8_00_0c; + heights[669] = 40'h0b_02_e8_00_0c; + heights[670] = 40'h0b_02_e8_00_0c; + heights[671] = 40'h0b_02_e8_00_0c; + heights[672] = 40'h0b_02_e8_00_0c; + heights[673] = 40'h0b_02_e8_00_0c; + heights[674] = 40'h0b_02_e8_00_0c; + heights[675] = 40'h0b_02_e8_00_0c; + heights[676] = 40'h0b_02_e8_00_0c; + heights[677] = 40'h0b_02_e8_00_0c; + heights[678] = 40'h0b_02_e8_00_0c; + heights[679] = 40'h0b_02_e8_00_0c; + heights[680] = 40'h0b_02_e8_00_0c; + heights[681] = 40'h0b_02_e8_00_0c; + heights[682] = 40'h0b_02_e8_00_0b; + heights[683] = 40'h0b_02_e8_00_0b; + heights[684] = 40'h0b_02_e8_00_0b; + heights[685] = 40'h0b_02_e8_00_0b; + heights[686] = 40'h0b_02_e8_00_0b; + heights[687] = 40'h0b_02_e8_00_0b; + heights[688] = 40'h0b_02_e8_00_0b; + heights[689] = 40'h0b_02_e8_00_0b; + heights[690] = 40'h0b_02_e8_00_0b; + heights[691] = 40'h0b_02_e8_00_0b; + heights[692] = 40'h0b_02_e8_00_0b; + heights[693] = 40'h0b_02_e8_00_0b; + heights[694] = 40'h0b_02_e8_00_0b; + heights[695] = 40'h0b_02_e8_00_0b; + heights[696] = 40'h0b_02_e8_00_0b; + heights[697] = 40'h0b_02_e8_00_0b; + heights[698] = 40'h0a_03_33_00_0b; + heights[699] = 40'h0a_03_33_00_0b; + heights[700] = 40'h0a_03_33_00_0b; + heights[701] = 40'h0a_03_33_00_0b; + heights[702] = 40'h0a_03_33_00_0b; + heights[703] = 40'h0a_03_33_00_0b; + heights[704] = 40'h0a_03_33_00_0b; + heights[705] = 40'h0a_03_33_00_0b; + heights[706] = 40'h0a_03_33_00_0b; + heights[707] = 40'h0a_03_33_00_0b; + heights[708] = 40'h0a_03_33_00_0b; + heights[709] = 40'h0a_03_33_00_0b; + heights[710] = 40'h0a_03_33_00_0b; + heights[711] = 40'h0a_03_33_00_0b; + heights[712] = 40'h0a_03_33_00_0b; + heights[713] = 40'h0a_03_33_00_0b; + heights[714] = 40'h0a_03_33_00_0b; + heights[715] = 40'h0a_03_33_00_0b; + heights[716] = 40'h0a_03_33_00_0b; + heights[717] = 40'h0a_03_33_00_0b; + heights[718] = 40'h0a_03_33_00_0b; + heights[719] = 40'h0a_03_33_00_0b; + heights[720] = 40'h0a_03_33_00_0b; + heights[721] = 40'h0a_03_33_00_0b; + heights[722] = 40'h0a_03_33_00_0b; + heights[723] = 40'h0a_03_33_00_0b; + heights[724] = 40'h0a_03_33_00_0b; + heights[725] = 40'h0a_03_33_00_0b; + heights[726] = 40'h0a_03_33_00_0b; + heights[727] = 40'h0a_03_33_00_0b; + heights[728] = 40'h0a_03_33_00_0b; + heights[729] = 40'h0a_03_33_00_0b; + heights[730] = 40'h0a_03_33_00_0b; + heights[731] = 40'h0a_03_33_00_0b; + heights[732] = 40'h0a_03_33_00_0b; + heights[733] = 40'h0a_03_33_00_0b; + heights[734] = 40'h0a_03_33_00_0b; + heights[735] = 40'h0a_03_33_00_0b; + heights[736] = 40'h0a_03_33_00_0b; + heights[737] = 40'h0a_03_33_00_0b; + heights[738] = 40'h0a_03_33_00_0b; + heights[739] = 40'h0a_03_33_00_0b; + heights[740] = 40'h0a_03_33_00_0b; + heights[741] = 40'h0a_03_33_00_0b; + heights[742] = 40'h0a_03_33_00_0b; + heights[743] = 40'h0a_03_33_00_0b; + heights[744] = 40'h0a_03_33_00_0a; + heights[745] = 40'h0a_03_33_00_0a; + heights[746] = 40'h0a_03_33_00_0a; + heights[747] = 40'h0a_03_33_00_0a; + heights[748] = 40'h0a_03_33_00_0a; + heights[749] = 40'h0a_03_33_00_0a; + heights[750] = 40'h0a_03_33_00_0a; + heights[751] = 40'h0a_03_33_00_0a; + heights[752] = 40'h0a_03_33_00_0a; + heights[753] = 40'h0a_03_33_00_0a; + heights[754] = 40'h0a_03_33_00_0a; + heights[755] = 40'h0a_03_33_00_0a; + heights[756] = 40'h0a_03_33_00_0a; + heights[757] = 40'h0a_03_33_00_0a; + heights[758] = 40'h0a_03_33_00_0a; + heights[759] = 40'h0a_03_33_00_0a; + heights[760] = 40'h0a_03_33_00_0a; + heights[761] = 40'h0a_03_33_00_0a; + heights[762] = 40'h0a_03_33_00_0a; + heights[763] = 40'h0a_03_33_00_0a; + heights[764] = 40'h0a_03_33_00_0a; + heights[765] = 40'h0a_03_33_00_0a; + heights[766] = 40'h0a_03_33_00_0a; + heights[767] = 40'h0a_03_33_00_0a; + heights[768] = 40'h09_03_8e_00_0a; + heights[769] = 40'h09_03_8e_00_0a; + heights[770] = 40'h09_03_8e_00_0a; + heights[771] = 40'h09_03_8e_00_0a; + heights[772] = 40'h09_03_8e_00_0a; + heights[773] = 40'h09_03_8e_00_0a; + heights[774] = 40'h09_03_8e_00_0a; + heights[775] = 40'h09_03_8e_00_0a; + heights[776] = 40'h09_03_8e_00_0a; + heights[777] = 40'h09_03_8e_00_0a; + heights[778] = 40'h09_03_8e_00_0a; + heights[779] = 40'h09_03_8e_00_0a; + heights[780] = 40'h09_03_8e_00_0a; + heights[781] = 40'h09_03_8e_00_0a; + heights[782] = 40'h09_03_8e_00_0a; + heights[783] = 40'h09_03_8e_00_0a; + heights[784] = 40'h09_03_8e_00_0a; + heights[785] = 40'h09_03_8e_00_0a; + heights[786] = 40'h09_03_8e_00_0a; + heights[787] = 40'h09_03_8e_00_0a; + heights[788] = 40'h09_03_8e_00_0a; + heights[789] = 40'h09_03_8e_00_0a; + heights[790] = 40'h09_03_8e_00_0a; + heights[791] = 40'h09_03_8e_00_0a; + heights[792] = 40'h09_03_8e_00_0a; + heights[793] = 40'h09_03_8e_00_0a; + heights[794] = 40'h09_03_8e_00_0a; + heights[795] = 40'h09_03_8e_00_0a; + heights[796] = 40'h09_03_8e_00_0a; + heights[797] = 40'h09_03_8e_00_0a; + heights[798] = 40'h09_03_8e_00_0a; + heights[799] = 40'h09_03_8e_00_0a; + heights[800] = 40'h09_03_8e_00_0a; + heights[801] = 40'h09_03_8e_00_0a; + heights[802] = 40'h09_03_8e_00_0a; + heights[803] = 40'h09_03_8e_00_0a; + heights[804] = 40'h09_03_8e_00_0a; + heights[805] = 40'h09_03_8e_00_0a; + heights[806] = 40'h09_03_8e_00_0a; + heights[807] = 40'h09_03_8e_00_0a; + heights[808] = 40'h09_03_8e_00_0a; + heights[809] = 40'h09_03_8e_00_0a; + heights[810] = 40'h09_03_8e_00_0a; + heights[811] = 40'h09_03_8e_00_0a; + heights[812] = 40'h09_03_8e_00_0a; + heights[813] = 40'h09_03_8e_00_0a; + heights[814] = 40'h09_03_8e_00_0a; + heights[815] = 40'h09_03_8e_00_0a; + heights[816] = 40'h09_03_8e_00_0a; + heights[817] = 40'h09_03_8e_00_0a; + heights[818] = 40'h09_03_8e_00_0a; + heights[819] = 40'h09_03_8e_00_09; + heights[820] = 40'h09_03_8e_00_09; + heights[821] = 40'h09_03_8e_00_09; + heights[822] = 40'h09_03_8e_00_09; + heights[823] = 40'h09_03_8e_00_09; + heights[824] = 40'h09_03_8e_00_09; + heights[825] = 40'h09_03_8e_00_09; + heights[826] = 40'h09_03_8e_00_09; + heights[827] = 40'h09_03_8e_00_09; + heights[828] = 40'h09_03_8e_00_09; + heights[829] = 40'h09_03_8e_00_09; + heights[830] = 40'h09_03_8e_00_09; + heights[831] = 40'h09_03_8e_00_09; + heights[832] = 40'h09_03_8e_00_09; + heights[833] = 40'h09_03_8e_00_09; + heights[834] = 40'h09_03_8e_00_09; + heights[835] = 40'h09_03_8e_00_09; + heights[836] = 40'h09_03_8e_00_09; + heights[837] = 40'h09_03_8e_00_09; + heights[838] = 40'h09_03_8e_00_09; + heights[839] = 40'h09_03_8e_00_09; + heights[840] = 40'h09_03_8e_00_09; + heights[841] = 40'h09_03_8e_00_09; + heights[842] = 40'h09_03_8e_00_09; + heights[843] = 40'h09_03_8e_00_09; + heights[844] = 40'h09_03_8e_00_09; + heights[845] = 40'h09_03_8e_00_09; + heights[846] = 40'h09_03_8e_00_09; + heights[847] = 40'h09_03_8e_00_09; + heights[848] = 40'h09_03_8e_00_09; + heights[849] = 40'h09_03_8e_00_09; + heights[850] = 40'h09_03_8e_00_09; + heights[851] = 40'h09_03_8e_00_09; + heights[852] = 40'h09_03_8e_00_09; + heights[853] = 40'h08_04_00_00_09; + heights[854] = 40'h08_04_00_00_09; + heights[855] = 40'h08_04_00_00_09; + heights[856] = 40'h08_04_00_00_09; + heights[857] = 40'h08_04_00_00_09; + heights[858] = 40'h08_04_00_00_09; + heights[859] = 40'h08_04_00_00_09; + heights[860] = 40'h08_04_00_00_09; + heights[861] = 40'h08_04_00_00_09; + heights[862] = 40'h08_04_00_00_09; + heights[863] = 40'h08_04_00_00_09; + heights[864] = 40'h08_04_00_00_09; + heights[865] = 40'h08_04_00_00_09; + heights[866] = 40'h08_04_00_00_09; + heights[867] = 40'h08_04_00_00_09; + heights[868] = 40'h08_04_00_00_09; + heights[869] = 40'h08_04_00_00_09; + heights[870] = 40'h08_04_00_00_09; + heights[871] = 40'h08_04_00_00_09; + heights[872] = 40'h08_04_00_00_09; + heights[873] = 40'h08_04_00_00_09; + heights[874] = 40'h08_04_00_00_09; + heights[875] = 40'h08_04_00_00_09; + heights[876] = 40'h08_04_00_00_09; + heights[877] = 40'h08_04_00_00_09; + heights[878] = 40'h08_04_00_00_09; + heights[879] = 40'h08_04_00_00_09; + heights[880] = 40'h08_04_00_00_09; + heights[881] = 40'h08_04_00_00_09; + heights[882] = 40'h08_04_00_00_09; + heights[883] = 40'h08_04_00_00_09; + heights[884] = 40'h08_04_00_00_09; + heights[885] = 40'h08_04_00_00_09; + heights[886] = 40'h08_04_00_00_09; + heights[887] = 40'h08_04_00_00_09; + heights[888] = 40'h08_04_00_00_09; + heights[889] = 40'h08_04_00_00_09; + heights[890] = 40'h08_04_00_00_09; + heights[891] = 40'h08_04_00_00_09; + heights[892] = 40'h08_04_00_00_09; + heights[893] = 40'h08_04_00_00_09; + heights[894] = 40'h08_04_00_00_09; + heights[895] = 40'h08_04_00_00_09; + heights[896] = 40'h08_04_00_00_09; + heights[897] = 40'h08_04_00_00_09; + heights[898] = 40'h08_04_00_00_09; + heights[899] = 40'h08_04_00_00_09; + heights[900] = 40'h08_04_00_00_09; + heights[901] = 40'h08_04_00_00_09; + heights[902] = 40'h08_04_00_00_09; + heights[903] = 40'h08_04_00_00_09; + heights[904] = 40'h08_04_00_00_09; + heights[905] = 40'h08_04_00_00_09; + heights[906] = 40'h08_04_00_00_09; + heights[907] = 40'h08_04_00_00_09; + heights[908] = 40'h08_04_00_00_09; + heights[909] = 40'h08_04_00_00_09; + heights[910] = 40'h08_04_00_00_08; + heights[911] = 40'h08_04_00_00_08; + heights[912] = 40'h08_04_00_00_08; + heights[913] = 40'h08_04_00_00_08; + heights[914] = 40'h08_04_00_00_08; + heights[915] = 40'h08_04_00_00_08; + heights[916] = 40'h08_04_00_00_08; + heights[917] = 40'h08_04_00_00_08; + heights[918] = 40'h08_04_00_00_08; + heights[919] = 40'h08_04_00_00_08; + heights[920] = 40'h08_04_00_00_08; + heights[921] = 40'h08_04_00_00_08; + heights[922] = 40'h08_04_00_00_08; + heights[923] = 40'h08_04_00_00_08; + heights[924] = 40'h08_04_00_00_08; + heights[925] = 40'h08_04_00_00_08; + heights[926] = 40'h08_04_00_00_08; + heights[927] = 40'h08_04_00_00_08; + heights[928] = 40'h08_04_00_00_08; + heights[929] = 40'h08_04_00_00_08; + heights[930] = 40'h08_04_00_00_08; + heights[931] = 40'h08_04_00_00_08; + heights[932] = 40'h08_04_00_00_08; + heights[933] = 40'h08_04_00_00_08; + heights[934] = 40'h08_04_00_00_08; + heights[935] = 40'h08_04_00_00_08; + heights[936] = 40'h08_04_00_00_08; + heights[937] = 40'h08_04_00_00_08; + heights[938] = 40'h08_04_00_00_08; + heights[939] = 40'h08_04_00_00_08; + heights[940] = 40'h08_04_00_00_08; + heights[941] = 40'h08_04_00_00_08; + heights[942] = 40'h08_04_00_00_08; + heights[943] = 40'h08_04_00_00_08; + heights[944] = 40'h08_04_00_00_08; + heights[945] = 40'h08_04_00_00_08; + heights[946] = 40'h08_04_00_00_08; + heights[947] = 40'h08_04_00_00_08; + heights[948] = 40'h08_04_00_00_08; + heights[949] = 40'h08_04_00_00_08; + heights[950] = 40'h08_04_00_00_08; + heights[951] = 40'h08_04_00_00_08; + heights[952] = 40'h08_04_00_00_08; + heights[953] = 40'h08_04_00_00_08; + heights[954] = 40'h08_04_00_00_08; + heights[955] = 40'h08_04_00_00_08; + heights[956] = 40'h08_04_00_00_08; + heights[957] = 40'h08_04_00_00_08; + heights[958] = 40'h08_04_00_00_08; + heights[959] = 40'h08_04_00_00_08; + heights[960] = 40'h07_04_92_00_08; + heights[961] = 40'h07_04_92_00_08; + heights[962] = 40'h07_04_92_00_08; + heights[963] = 40'h07_04_92_00_08; + heights[964] = 40'h07_04_92_00_08; + heights[965] = 40'h07_04_92_00_08; + heights[966] = 40'h07_04_92_00_08; + heights[967] = 40'h07_04_92_00_08; + heights[968] = 40'h07_04_92_00_08; + heights[969] = 40'h07_04_92_00_08; + heights[970] = 40'h07_04_92_00_08; + heights[971] = 40'h07_04_92_00_08; + heights[972] = 40'h07_04_92_00_08; + heights[973] = 40'h07_04_92_00_08; + heights[974] = 40'h07_04_92_00_08; + heights[975] = 40'h07_04_92_00_08; + heights[976] = 40'h07_04_92_00_08; + heights[977] = 40'h07_04_92_00_08; + heights[978] = 40'h07_04_92_00_08; + heights[979] = 40'h07_04_92_00_08; + heights[980] = 40'h07_04_92_00_08; + heights[981] = 40'h07_04_92_00_08; + heights[982] = 40'h07_04_92_00_08; + heights[983] = 40'h07_04_92_00_08; + heights[984] = 40'h07_04_92_00_08; + heights[985] = 40'h07_04_92_00_08; + heights[986] = 40'h07_04_92_00_08; + heights[987] = 40'h07_04_92_00_08; + heights[988] = 40'h07_04_92_00_08; + heights[989] = 40'h07_04_92_00_08; + heights[990] = 40'h07_04_92_00_08; + heights[991] = 40'h07_04_92_00_08; + heights[992] = 40'h07_04_92_00_08; + heights[993] = 40'h07_04_92_00_08; + heights[994] = 40'h07_04_92_00_08; + heights[995] = 40'h07_04_92_00_08; + heights[996] = 40'h07_04_92_00_08; + heights[997] = 40'h07_04_92_00_08; + heights[998] = 40'h07_04_92_00_08; + heights[999] = 40'h07_04_92_00_08; + heights[1000] = 40'h07_04_92_00_08; + heights[1001] = 40'h07_04_92_00_08; + heights[1002] = 40'h07_04_92_00_08; + heights[1003] = 40'h07_04_92_00_08; + heights[1004] = 40'h07_04_92_00_08; + heights[1005] = 40'h07_04_92_00_08; + heights[1006] = 40'h07_04_92_00_08; + heights[1007] = 40'h07_04_92_00_08; + heights[1008] = 40'h07_04_92_00_08; + heights[1009] = 40'h07_04_92_00_08; + heights[1010] = 40'h07_04_92_00_08; + heights[1011] = 40'h07_04_92_00_08; + heights[1012] = 40'h07_04_92_00_08; + heights[1013] = 40'h07_04_92_00_08; + heights[1014] = 40'h07_04_92_00_08; + heights[1015] = 40'h07_04_92_00_08; + heights[1016] = 40'h07_04_92_00_08; + heights[1017] = 40'h07_04_92_00_08; + heights[1018] = 40'h07_04_92_00_08; + heights[1019] = 40'h07_04_92_00_08; + heights[1020] = 40'h07_04_92_00_08; + heights[1021] = 40'h07_04_92_00_08; + heights[1022] = 40'h07_04_92_00_08; + heights[1023] = 40'h07_04_92_00_08; diff --git a/src/height_rom.v b/src/height_rom.v new file mode 100644 index 0000000..075dbf3 --- /dev/null +++ b/src/height_rom.v @@ -0,0 +1,28 @@ +module height_rom ( + input clk, + input [9:0] addr, + output [39:0] height // 8bit height, Q8.8 texture scale, Q8.8 inverse distance + ); + +reg [39:0] heights [1023:0]; + +reg [39:0] height_d, height_q; + +assign height = height_q; + +initial begin +`include "height.rom" +end + +always @(*) begin + if (addr < 16'd1023) + height_d = heights[addr]; + else + height_d = 40'd0; +end + +always @(posedge clk) begin + height_q <= height_d; +end + +endmodule diff --git a/src/idist.rom b/src/idist.rom new file mode 100644 index 0000000..441431d --- /dev/null +++ b/src/idist.rom @@ -0,0 +1,1024 @@ + idists[0] = 16'h20_00; + idists[1] = 16'h10_00; + idists[2] = 16'h0a_aa; + idists[3] = 16'h08_00; + idists[4] = 16'h06_66; + idists[5] = 16'h05_55; + idists[6] = 16'h04_92; + idists[7] = 16'h04_00; + idists[8] = 16'h03_8e; + idists[9] = 16'h03_33; + idists[10] = 16'h02_e8; + idists[11] = 16'h02_aa; + idists[12] = 16'h02_76; + idists[13] = 16'h02_49; + idists[14] = 16'h02_22; + idists[15] = 16'h02_00; + idists[16] = 16'h01_e1; + idists[17] = 16'h01_c7; + idists[18] = 16'h01_af; + idists[19] = 16'h01_99; + idists[20] = 16'h01_86; + idists[21] = 16'h01_74; + idists[22] = 16'h01_64; + idists[23] = 16'h01_55; + idists[24] = 16'h01_47; + idists[25] = 16'h01_3b; + idists[26] = 16'h01_2f; + idists[27] = 16'h01_24; + idists[28] = 16'h01_1a; + idists[29] = 16'h01_11; + idists[30] = 16'h01_08; + idists[31] = 16'h01_00; + idists[32] = 16'h00_f8; + idists[33] = 16'h00_f0; + idists[34] = 16'h00_ea; + idists[35] = 16'h00_e3; + idists[36] = 16'h00_dd; + idists[37] = 16'h00_d7; + idists[38] = 16'h00_d2; + idists[39] = 16'h00_cc; + idists[40] = 16'h00_c7; + idists[41] = 16'h00_c3; + idists[42] = 16'h00_be; + idists[43] = 16'h00_ba; + idists[44] = 16'h00_b6; + idists[45] = 16'h00_b2; + idists[46] = 16'h00_ae; + idists[47] = 16'h00_aa; + idists[48] = 16'h00_a7; + idists[49] = 16'h00_a3; + idists[50] = 16'h00_a0; + idists[51] = 16'h00_9d; + idists[52] = 16'h00_9a; + idists[53] = 16'h00_97; + idists[54] = 16'h00_94; + idists[55] = 16'h00_92; + idists[56] = 16'h00_8f; + idists[57] = 16'h00_8d; + idists[58] = 16'h00_8a; + idists[59] = 16'h00_88; + idists[60] = 16'h00_86; + idists[61] = 16'h00_84; + idists[62] = 16'h00_82; + idists[63] = 16'h00_80; + idists[64] = 16'h00_7e; + idists[65] = 16'h00_7c; + idists[66] = 16'h00_7a; + idists[67] = 16'h00_78; + idists[68] = 16'h00_76; + idists[69] = 16'h00_75; + idists[70] = 16'h00_73; + idists[71] = 16'h00_71; + idists[72] = 16'h00_70; + idists[73] = 16'h00_6e; + idists[74] = 16'h00_6d; + idists[75] = 16'h00_6b; + idists[76] = 16'h00_6a; + idists[77] = 16'h00_69; + idists[78] = 16'h00_67; + idists[79] = 16'h00_66; + idists[80] = 16'h00_65; + idists[81] = 16'h00_63; + idists[82] = 16'h00_62; + idists[83] = 16'h00_61; + idists[84] = 16'h00_60; + idists[85] = 16'h00_5f; + idists[86] = 16'h00_5e; + idists[87] = 16'h00_5d; + idists[88] = 16'h00_5c; + idists[89] = 16'h00_5b; + idists[90] = 16'h00_5a; + idists[91] = 16'h00_59; + idists[92] = 16'h00_58; + idists[93] = 16'h00_57; + idists[94] = 16'h00_56; + idists[95] = 16'h00_55; + idists[96] = 16'h00_54; + idists[97] = 16'h00_53; + idists[98] = 16'h00_52; + idists[99] = 16'h00_51; + idists[100] = 16'h00_51; + idists[101] = 16'h00_50; + idists[102] = 16'h00_4f; + idists[103] = 16'h00_4e; + idists[104] = 16'h00_4e; + idists[105] = 16'h00_4d; + idists[106] = 16'h00_4c; + idists[107] = 16'h00_4b; + idists[108] = 16'h00_4b; + idists[109] = 16'h00_4a; + idists[110] = 16'h00_49; + idists[111] = 16'h00_49; + idists[112] = 16'h00_48; + idists[113] = 16'h00_47; + idists[114] = 16'h00_47; + idists[115] = 16'h00_46; + idists[116] = 16'h00_46; + idists[117] = 16'h00_45; + idists[118] = 16'h00_44; + idists[119] = 16'h00_44; + idists[120] = 16'h00_43; + idists[121] = 16'h00_43; + idists[122] = 16'h00_42; + idists[123] = 16'h00_42; + idists[124] = 16'h00_41; + idists[125] = 16'h00_41; + idists[126] = 16'h00_40; + idists[127] = 16'h00_40; + idists[128] = 16'h00_3f; + idists[129] = 16'h00_3f; + idists[130] = 16'h00_3e; + idists[131] = 16'h00_3e; + idists[132] = 16'h00_3d; + idists[133] = 16'h00_3d; + idists[134] = 16'h00_3c; + idists[135] = 16'h00_3c; + idists[136] = 16'h00_3b; + idists[137] = 16'h00_3b; + idists[138] = 16'h00_3a; + idists[139] = 16'h00_3a; + idists[140] = 16'h00_3a; + idists[141] = 16'h00_39; + idists[142] = 16'h00_39; + idists[143] = 16'h00_38; + idists[144] = 16'h00_38; + idists[145] = 16'h00_38; + idists[146] = 16'h00_37; + idists[147] = 16'h00_37; + idists[148] = 16'h00_36; + idists[149] = 16'h00_36; + idists[150] = 16'h00_36; + idists[151] = 16'h00_35; + idists[152] = 16'h00_35; + idists[153] = 16'h00_35; + idists[154] = 16'h00_34; + idists[155] = 16'h00_34; + idists[156] = 16'h00_34; + idists[157] = 16'h00_33; + idists[158] = 16'h00_33; + idists[159] = 16'h00_33; + idists[160] = 16'h00_32; + idists[161] = 16'h00_32; + idists[162] = 16'h00_32; + idists[163] = 16'h00_31; + idists[164] = 16'h00_31; + idists[165] = 16'h00_31; + idists[166] = 16'h00_31; + idists[167] = 16'h00_30; + idists[168] = 16'h00_30; + idists[169] = 16'h00_30; + idists[170] = 16'h00_2f; + idists[171] = 16'h00_2f; + idists[172] = 16'h00_2f; + idists[173] = 16'h00_2f; + idists[174] = 16'h00_2e; + idists[175] = 16'h00_2e; + idists[176] = 16'h00_2e; + idists[177] = 16'h00_2e; + idists[178] = 16'h00_2d; + idists[179] = 16'h00_2d; + idists[180] = 16'h00_2d; + idists[181] = 16'h00_2d; + idists[182] = 16'h00_2c; + idists[183] = 16'h00_2c; + idists[184] = 16'h00_2c; + idists[185] = 16'h00_2c; + idists[186] = 16'h00_2b; + idists[187] = 16'h00_2b; + idists[188] = 16'h00_2b; + idists[189] = 16'h00_2b; + idists[190] = 16'h00_2a; + idists[191] = 16'h00_2a; + idists[192] = 16'h00_2a; + idists[193] = 16'h00_2a; + idists[194] = 16'h00_2a; + idists[195] = 16'h00_29; + idists[196] = 16'h00_29; + idists[197] = 16'h00_29; + idists[198] = 16'h00_29; + idists[199] = 16'h00_28; + idists[200] = 16'h00_28; + idists[201] = 16'h00_28; + idists[202] = 16'h00_28; + idists[203] = 16'h00_28; + idists[204] = 16'h00_27; + idists[205] = 16'h00_27; + idists[206] = 16'h00_27; + idists[207] = 16'h00_27; + idists[208] = 16'h00_27; + idists[209] = 16'h00_27; + idists[210] = 16'h00_26; + idists[211] = 16'h00_26; + idists[212] = 16'h00_26; + idists[213] = 16'h00_26; + idists[214] = 16'h00_26; + idists[215] = 16'h00_25; + idists[216] = 16'h00_25; + idists[217] = 16'h00_25; + idists[218] = 16'h00_25; + idists[219] = 16'h00_25; + idists[220] = 16'h00_25; + idists[221] = 16'h00_24; + idists[222] = 16'h00_24; + idists[223] = 16'h00_24; + idists[224] = 16'h00_24; + idists[225] = 16'h00_24; + idists[226] = 16'h00_24; + idists[227] = 16'h00_23; + idists[228] = 16'h00_23; + idists[229] = 16'h00_23; + idists[230] = 16'h00_23; + idists[231] = 16'h00_23; + idists[232] = 16'h00_23; + idists[233] = 16'h00_23; + idists[234] = 16'h00_22; + idists[235] = 16'h00_22; + idists[236] = 16'h00_22; + idists[237] = 16'h00_22; + idists[238] = 16'h00_22; + idists[239] = 16'h00_22; + idists[240] = 16'h00_21; + idists[241] = 16'h00_21; + idists[242] = 16'h00_21; + idists[243] = 16'h00_21; + idists[244] = 16'h00_21; + idists[245] = 16'h00_21; + idists[246] = 16'h00_21; + idists[247] = 16'h00_21; + idists[248] = 16'h00_20; + idists[249] = 16'h00_20; + idists[250] = 16'h00_20; + idists[251] = 16'h00_20; + idists[252] = 16'h00_20; + idists[253] = 16'h00_20; + idists[254] = 16'h00_20; + idists[255] = 16'h00_20; + idists[256] = 16'h00_1f; + idists[257] = 16'h00_1f; + idists[258] = 16'h00_1f; + idists[259] = 16'h00_1f; + idists[260] = 16'h00_1f; + idists[261] = 16'h00_1f; + idists[262] = 16'h00_1f; + idists[263] = 16'h00_1f; + idists[264] = 16'h00_1e; + idists[265] = 16'h00_1e; + idists[266] = 16'h00_1e; + idists[267] = 16'h00_1e; + idists[268] = 16'h00_1e; + idists[269] = 16'h00_1e; + idists[270] = 16'h00_1e; + idists[271] = 16'h00_1e; + idists[272] = 16'h00_1e; + idists[273] = 16'h00_1d; + idists[274] = 16'h00_1d; + idists[275] = 16'h00_1d; + idists[276] = 16'h00_1d; + idists[277] = 16'h00_1d; + idists[278] = 16'h00_1d; + idists[279] = 16'h00_1d; + idists[280] = 16'h00_1d; + idists[281] = 16'h00_1d; + idists[282] = 16'h00_1c; + idists[283] = 16'h00_1c; + idists[284] = 16'h00_1c; + idists[285] = 16'h00_1c; + idists[286] = 16'h00_1c; + idists[287] = 16'h00_1c; + idists[288] = 16'h00_1c; + idists[289] = 16'h00_1c; + idists[290] = 16'h00_1c; + idists[291] = 16'h00_1c; + idists[292] = 16'h00_1b; + idists[293] = 16'h00_1b; + idists[294] = 16'h00_1b; + idists[295] = 16'h00_1b; + idists[296] = 16'h00_1b; + idists[297] = 16'h00_1b; + idists[298] = 16'h00_1b; + idists[299] = 16'h00_1b; + idists[300] = 16'h00_1b; + idists[301] = 16'h00_1b; + idists[302] = 16'h00_1b; + idists[303] = 16'h00_1a; + idists[304] = 16'h00_1a; + idists[305] = 16'h00_1a; + idists[306] = 16'h00_1a; + idists[307] = 16'h00_1a; + idists[308] = 16'h00_1a; + idists[309] = 16'h00_1a; + idists[310] = 16'h00_1a; + idists[311] = 16'h00_1a; + idists[312] = 16'h00_1a; + idists[313] = 16'h00_1a; + idists[314] = 16'h00_1a; + idists[315] = 16'h00_19; + idists[316] = 16'h00_19; + idists[317] = 16'h00_19; + idists[318] = 16'h00_19; + idists[319] = 16'h00_19; + idists[320] = 16'h00_19; + idists[321] = 16'h00_19; + idists[322] = 16'h00_19; + idists[323] = 16'h00_19; + idists[324] = 16'h00_19; + idists[325] = 16'h00_19; + idists[326] = 16'h00_19; + idists[327] = 16'h00_18; + idists[328] = 16'h00_18; + idists[329] = 16'h00_18; + idists[330] = 16'h00_18; + idists[331] = 16'h00_18; + idists[332] = 16'h00_18; + idists[333] = 16'h00_18; + idists[334] = 16'h00_18; + idists[335] = 16'h00_18; + idists[336] = 16'h00_18; + idists[337] = 16'h00_18; + idists[338] = 16'h00_18; + idists[339] = 16'h00_18; + idists[340] = 16'h00_18; + idists[341] = 16'h00_17; + idists[342] = 16'h00_17; + idists[343] = 16'h00_17; + idists[344] = 16'h00_17; + idists[345] = 16'h00_17; + idists[346] = 16'h00_17; + idists[347] = 16'h00_17; + idists[348] = 16'h00_17; + idists[349] = 16'h00_17; + idists[350] = 16'h00_17; + idists[351] = 16'h00_17; + idists[352] = 16'h00_17; + idists[353] = 16'h00_17; + idists[354] = 16'h00_17; + idists[355] = 16'h00_17; + idists[356] = 16'h00_16; + idists[357] = 16'h00_16; + idists[358] = 16'h00_16; + idists[359] = 16'h00_16; + idists[360] = 16'h00_16; + idists[361] = 16'h00_16; + idists[362] = 16'h00_16; + idists[363] = 16'h00_16; + idists[364] = 16'h00_16; + idists[365] = 16'h00_16; + idists[366] = 16'h00_16; + idists[367] = 16'h00_16; + idists[368] = 16'h00_16; + idists[369] = 16'h00_16; + idists[370] = 16'h00_16; + idists[371] = 16'h00_16; + idists[372] = 16'h00_15; + idists[373] = 16'h00_15; + idists[374] = 16'h00_15; + idists[375] = 16'h00_15; + idists[376] = 16'h00_15; + idists[377] = 16'h00_15; + idists[378] = 16'h00_15; + idists[379] = 16'h00_15; + idists[380] = 16'h00_15; + idists[381] = 16'h00_15; + idists[382] = 16'h00_15; + idists[383] = 16'h00_15; + idists[384] = 16'h00_15; + idists[385] = 16'h00_15; + idists[386] = 16'h00_15; + idists[387] = 16'h00_15; + idists[388] = 16'h00_15; + idists[389] = 16'h00_15; + idists[390] = 16'h00_14; + idists[391] = 16'h00_14; + idists[392] = 16'h00_14; + idists[393] = 16'h00_14; + idists[394] = 16'h00_14; + idists[395] = 16'h00_14; + idists[396] = 16'h00_14; + idists[397] = 16'h00_14; + idists[398] = 16'h00_14; + idists[399] = 16'h00_14; + idists[400] = 16'h00_14; + idists[401] = 16'h00_14; + idists[402] = 16'h00_14; + idists[403] = 16'h00_14; + idists[404] = 16'h00_14; + idists[405] = 16'h00_14; + idists[406] = 16'h00_14; + idists[407] = 16'h00_14; + idists[408] = 16'h00_14; + idists[409] = 16'h00_13; + idists[410] = 16'h00_13; + idists[411] = 16'h00_13; + idists[412] = 16'h00_13; + idists[413] = 16'h00_13; + idists[414] = 16'h00_13; + idists[415] = 16'h00_13; + idists[416] = 16'h00_13; + idists[417] = 16'h00_13; + idists[418] = 16'h00_13; + idists[419] = 16'h00_13; + idists[420] = 16'h00_13; + idists[421] = 16'h00_13; + idists[422] = 16'h00_13; + idists[423] = 16'h00_13; + idists[424] = 16'h00_13; + idists[425] = 16'h00_13; + idists[426] = 16'h00_13; + idists[427] = 16'h00_13; + idists[428] = 16'h00_13; + idists[429] = 16'h00_13; + idists[430] = 16'h00_13; + idists[431] = 16'h00_12; + idists[432] = 16'h00_12; + idists[433] = 16'h00_12; + idists[434] = 16'h00_12; + idists[435] = 16'h00_12; + idists[436] = 16'h00_12; + idists[437] = 16'h00_12; + idists[438] = 16'h00_12; + idists[439] = 16'h00_12; + idists[440] = 16'h00_12; + idists[441] = 16'h00_12; + idists[442] = 16'h00_12; + idists[443] = 16'h00_12; + idists[444] = 16'h00_12; + idists[445] = 16'h00_12; + idists[446] = 16'h00_12; + idists[447] = 16'h00_12; + idists[448] = 16'h00_12; + idists[449] = 16'h00_12; + idists[450] = 16'h00_12; + idists[451] = 16'h00_12; + idists[452] = 16'h00_12; + idists[453] = 16'h00_12; + idists[454] = 16'h00_12; + idists[455] = 16'h00_11; + idists[456] = 16'h00_11; + idists[457] = 16'h00_11; + idists[458] = 16'h00_11; + idists[459] = 16'h00_11; + idists[460] = 16'h00_11; + idists[461] = 16'h00_11; + idists[462] = 16'h00_11; + idists[463] = 16'h00_11; + idists[464] = 16'h00_11; + idists[465] = 16'h00_11; + idists[466] = 16'h00_11; + idists[467] = 16'h00_11; + idists[468] = 16'h00_11; + idists[469] = 16'h00_11; + idists[470] = 16'h00_11; + idists[471] = 16'h00_11; + idists[472] = 16'h00_11; + idists[473] = 16'h00_11; + idists[474] = 16'h00_11; + idists[475] = 16'h00_11; + idists[476] = 16'h00_11; + idists[477] = 16'h00_11; + idists[478] = 16'h00_11; + idists[479] = 16'h00_11; + idists[480] = 16'h00_11; + idists[481] = 16'h00_10; + idists[482] = 16'h00_10; + idists[483] = 16'h00_10; + idists[484] = 16'h00_10; + idists[485] = 16'h00_10; + idists[486] = 16'h00_10; + idists[487] = 16'h00_10; + idists[488] = 16'h00_10; + idists[489] = 16'h00_10; + idists[490] = 16'h00_10; + idists[491] = 16'h00_10; + idists[492] = 16'h00_10; + idists[493] = 16'h00_10; + idists[494] = 16'h00_10; + idists[495] = 16'h00_10; + idists[496] = 16'h00_10; + idists[497] = 16'h00_10; + idists[498] = 16'h00_10; + idists[499] = 16'h00_10; + idists[500] = 16'h00_10; + idists[501] = 16'h00_10; + idists[502] = 16'h00_10; + idists[503] = 16'h00_10; + idists[504] = 16'h00_10; + idists[505] = 16'h00_10; + idists[506] = 16'h00_10; + idists[507] = 16'h00_10; + idists[508] = 16'h00_10; + idists[509] = 16'h00_10; + idists[510] = 16'h00_10; + idists[511] = 16'h00_10; + idists[512] = 16'h00_0f; + idists[513] = 16'h00_0f; + idists[514] = 16'h00_0f; + idists[515] = 16'h00_0f; + idists[516] = 16'h00_0f; + idists[517] = 16'h00_0f; + idists[518] = 16'h00_0f; + idists[519] = 16'h00_0f; + idists[520] = 16'h00_0f; + idists[521] = 16'h00_0f; + idists[522] = 16'h00_0f; + idists[523] = 16'h00_0f; + idists[524] = 16'h00_0f; + idists[525] = 16'h00_0f; + idists[526] = 16'h00_0f; + idists[527] = 16'h00_0f; + idists[528] = 16'h00_0f; + idists[529] = 16'h00_0f; + idists[530] = 16'h00_0f; + idists[531] = 16'h00_0f; + idists[532] = 16'h00_0f; + idists[533] = 16'h00_0f; + idists[534] = 16'h00_0f; + idists[535] = 16'h00_0f; + idists[536] = 16'h00_0f; + idists[537] = 16'h00_0f; + idists[538] = 16'h00_0f; + idists[539] = 16'h00_0f; + idists[540] = 16'h00_0f; + idists[541] = 16'h00_0f; + idists[542] = 16'h00_0f; + idists[543] = 16'h00_0f; + idists[544] = 16'h00_0f; + idists[545] = 16'h00_0f; + idists[546] = 16'h00_0e; + idists[547] = 16'h00_0e; + idists[548] = 16'h00_0e; + idists[549] = 16'h00_0e; + idists[550] = 16'h00_0e; + idists[551] = 16'h00_0e; + idists[552] = 16'h00_0e; + idists[553] = 16'h00_0e; + idists[554] = 16'h00_0e; + idists[555] = 16'h00_0e; + idists[556] = 16'h00_0e; + idists[557] = 16'h00_0e; + idists[558] = 16'h00_0e; + idists[559] = 16'h00_0e; + idists[560] = 16'h00_0e; + idists[561] = 16'h00_0e; + idists[562] = 16'h00_0e; + idists[563] = 16'h00_0e; + idists[564] = 16'h00_0e; + idists[565] = 16'h00_0e; + idists[566] = 16'h00_0e; + idists[567] = 16'h00_0e; + idists[568] = 16'h00_0e; + idists[569] = 16'h00_0e; + idists[570] = 16'h00_0e; + idists[571] = 16'h00_0e; + idists[572] = 16'h00_0e; + idists[573] = 16'h00_0e; + idists[574] = 16'h00_0e; + idists[575] = 16'h00_0e; + idists[576] = 16'h00_0e; + idists[577] = 16'h00_0e; + idists[578] = 16'h00_0e; + idists[579] = 16'h00_0e; + idists[580] = 16'h00_0e; + idists[581] = 16'h00_0e; + idists[582] = 16'h00_0e; + idists[583] = 16'h00_0e; + idists[584] = 16'h00_0e; + idists[585] = 16'h00_0d; + idists[586] = 16'h00_0d; + idists[587] = 16'h00_0d; + idists[588] = 16'h00_0d; + idists[589] = 16'h00_0d; + idists[590] = 16'h00_0d; + idists[591] = 16'h00_0d; + idists[592] = 16'h00_0d; + idists[593] = 16'h00_0d; + idists[594] = 16'h00_0d; + idists[595] = 16'h00_0d; + idists[596] = 16'h00_0d; + idists[597] = 16'h00_0d; + idists[598] = 16'h00_0d; + idists[599] = 16'h00_0d; + idists[600] = 16'h00_0d; + idists[601] = 16'h00_0d; + idists[602] = 16'h00_0d; + idists[603] = 16'h00_0d; + idists[604] = 16'h00_0d; + idists[605] = 16'h00_0d; + idists[606] = 16'h00_0d; + idists[607] = 16'h00_0d; + idists[608] = 16'h00_0d; + idists[609] = 16'h00_0d; + idists[610] = 16'h00_0d; + idists[611] = 16'h00_0d; + idists[612] = 16'h00_0d; + idists[613] = 16'h00_0d; + idists[614] = 16'h00_0d; + idists[615] = 16'h00_0d; + idists[616] = 16'h00_0d; + idists[617] = 16'h00_0d; + idists[618] = 16'h00_0d; + idists[619] = 16'h00_0d; + idists[620] = 16'h00_0d; + idists[621] = 16'h00_0d; + idists[622] = 16'h00_0d; + idists[623] = 16'h00_0d; + idists[624] = 16'h00_0d; + idists[625] = 16'h00_0d; + idists[626] = 16'h00_0d; + idists[627] = 16'h00_0d; + idists[628] = 16'h00_0d; + idists[629] = 16'h00_0d; + idists[630] = 16'h00_0c; + idists[631] = 16'h00_0c; + idists[632] = 16'h00_0c; + idists[633] = 16'h00_0c; + idists[634] = 16'h00_0c; + idists[635] = 16'h00_0c; + idists[636] = 16'h00_0c; + idists[637] = 16'h00_0c; + idists[638] = 16'h00_0c; + idists[639] = 16'h00_0c; + idists[640] = 16'h00_0c; + idists[641] = 16'h00_0c; + idists[642] = 16'h00_0c; + idists[643] = 16'h00_0c; + idists[644] = 16'h00_0c; + idists[645] = 16'h00_0c; + idists[646] = 16'h00_0c; + idists[647] = 16'h00_0c; + idists[648] = 16'h00_0c; + idists[649] = 16'h00_0c; + idists[650] = 16'h00_0c; + idists[651] = 16'h00_0c; + idists[652] = 16'h00_0c; + idists[653] = 16'h00_0c; + idists[654] = 16'h00_0c; + idists[655] = 16'h00_0c; + idists[656] = 16'h00_0c; + idists[657] = 16'h00_0c; + idists[658] = 16'h00_0c; + idists[659] = 16'h00_0c; + idists[660] = 16'h00_0c; + idists[661] = 16'h00_0c; + idists[662] = 16'h00_0c; + idists[663] = 16'h00_0c; + idists[664] = 16'h00_0c; + idists[665] = 16'h00_0c; + idists[666] = 16'h00_0c; + idists[667] = 16'h00_0c; + idists[668] = 16'h00_0c; + idists[669] = 16'h00_0c; + idists[670] = 16'h00_0c; + idists[671] = 16'h00_0c; + idists[672] = 16'h00_0c; + idists[673] = 16'h00_0c; + idists[674] = 16'h00_0c; + idists[675] = 16'h00_0c; + idists[676] = 16'h00_0c; + idists[677] = 16'h00_0c; + idists[678] = 16'h00_0c; + idists[679] = 16'h00_0c; + idists[680] = 16'h00_0c; + idists[681] = 16'h00_0c; + idists[682] = 16'h00_0b; + idists[683] = 16'h00_0b; + idists[684] = 16'h00_0b; + idists[685] = 16'h00_0b; + idists[686] = 16'h00_0b; + idists[687] = 16'h00_0b; + idists[688] = 16'h00_0b; + idists[689] = 16'h00_0b; + idists[690] = 16'h00_0b; + idists[691] = 16'h00_0b; + idists[692] = 16'h00_0b; + idists[693] = 16'h00_0b; + idists[694] = 16'h00_0b; + idists[695] = 16'h00_0b; + idists[696] = 16'h00_0b; + idists[697] = 16'h00_0b; + idists[698] = 16'h00_0b; + idists[699] = 16'h00_0b; + idists[700] = 16'h00_0b; + idists[701] = 16'h00_0b; + idists[702] = 16'h00_0b; + idists[703] = 16'h00_0b; + idists[704] = 16'h00_0b; + idists[705] = 16'h00_0b; + idists[706] = 16'h00_0b; + idists[707] = 16'h00_0b; + idists[708] = 16'h00_0b; + idists[709] = 16'h00_0b; + idists[710] = 16'h00_0b; + idists[711] = 16'h00_0b; + idists[712] = 16'h00_0b; + idists[713] = 16'h00_0b; + idists[714] = 16'h00_0b; + idists[715] = 16'h00_0b; + idists[716] = 16'h00_0b; + idists[717] = 16'h00_0b; + idists[718] = 16'h00_0b; + idists[719] = 16'h00_0b; + idists[720] = 16'h00_0b; + idists[721] = 16'h00_0b; + idists[722] = 16'h00_0b; + idists[723] = 16'h00_0b; + idists[724] = 16'h00_0b; + idists[725] = 16'h00_0b; + idists[726] = 16'h00_0b; + idists[727] = 16'h00_0b; + idists[728] = 16'h00_0b; + idists[729] = 16'h00_0b; + idists[730] = 16'h00_0b; + idists[731] = 16'h00_0b; + idists[732] = 16'h00_0b; + idists[733] = 16'h00_0b; + idists[734] = 16'h00_0b; + idists[735] = 16'h00_0b; + idists[736] = 16'h00_0b; + idists[737] = 16'h00_0b; + idists[738] = 16'h00_0b; + idists[739] = 16'h00_0b; + idists[740] = 16'h00_0b; + idists[741] = 16'h00_0b; + idists[742] = 16'h00_0b; + idists[743] = 16'h00_0b; + idists[744] = 16'h00_0a; + idists[745] = 16'h00_0a; + idists[746] = 16'h00_0a; + idists[747] = 16'h00_0a; + idists[748] = 16'h00_0a; + idists[749] = 16'h00_0a; + idists[750] = 16'h00_0a; + idists[751] = 16'h00_0a; + idists[752] = 16'h00_0a; + idists[753] = 16'h00_0a; + idists[754] = 16'h00_0a; + idists[755] = 16'h00_0a; + idists[756] = 16'h00_0a; + idists[757] = 16'h00_0a; + idists[758] = 16'h00_0a; + idists[759] = 16'h00_0a; + idists[760] = 16'h00_0a; + idists[761] = 16'h00_0a; + idists[762] = 16'h00_0a; + idists[763] = 16'h00_0a; + idists[764] = 16'h00_0a; + idists[765] = 16'h00_0a; + idists[766] = 16'h00_0a; + idists[767] = 16'h00_0a; + idists[768] = 16'h00_0a; + idists[769] = 16'h00_0a; + idists[770] = 16'h00_0a; + idists[771] = 16'h00_0a; + idists[772] = 16'h00_0a; + idists[773] = 16'h00_0a; + idists[774] = 16'h00_0a; + idists[775] = 16'h00_0a; + idists[776] = 16'h00_0a; + idists[777] = 16'h00_0a; + idists[778] = 16'h00_0a; + idists[779] = 16'h00_0a; + idists[780] = 16'h00_0a; + idists[781] = 16'h00_0a; + idists[782] = 16'h00_0a; + idists[783] = 16'h00_0a; + idists[784] = 16'h00_0a; + idists[785] = 16'h00_0a; + idists[786] = 16'h00_0a; + idists[787] = 16'h00_0a; + idists[788] = 16'h00_0a; + idists[789] = 16'h00_0a; + idists[790] = 16'h00_0a; + idists[791] = 16'h00_0a; + idists[792] = 16'h00_0a; + idists[793] = 16'h00_0a; + idists[794] = 16'h00_0a; + idists[795] = 16'h00_0a; + idists[796] = 16'h00_0a; + idists[797] = 16'h00_0a; + idists[798] = 16'h00_0a; + idists[799] = 16'h00_0a; + idists[800] = 16'h00_0a; + idists[801] = 16'h00_0a; + idists[802] = 16'h00_0a; + idists[803] = 16'h00_0a; + idists[804] = 16'h00_0a; + idists[805] = 16'h00_0a; + idists[806] = 16'h00_0a; + idists[807] = 16'h00_0a; + idists[808] = 16'h00_0a; + idists[809] = 16'h00_0a; + idists[810] = 16'h00_0a; + idists[811] = 16'h00_0a; + idists[812] = 16'h00_0a; + idists[813] = 16'h00_0a; + idists[814] = 16'h00_0a; + idists[815] = 16'h00_0a; + idists[816] = 16'h00_0a; + idists[817] = 16'h00_0a; + idists[818] = 16'h00_0a; + idists[819] = 16'h00_09; + idists[820] = 16'h00_09; + idists[821] = 16'h00_09; + idists[822] = 16'h00_09; + idists[823] = 16'h00_09; + idists[824] = 16'h00_09; + idists[825] = 16'h00_09; + idists[826] = 16'h00_09; + idists[827] = 16'h00_09; + idists[828] = 16'h00_09; + idists[829] = 16'h00_09; + idists[830] = 16'h00_09; + idists[831] = 16'h00_09; + idists[832] = 16'h00_09; + idists[833] = 16'h00_09; + idists[834] = 16'h00_09; + idists[835] = 16'h00_09; + idists[836] = 16'h00_09; + idists[837] = 16'h00_09; + idists[838] = 16'h00_09; + idists[839] = 16'h00_09; + idists[840] = 16'h00_09; + idists[841] = 16'h00_09; + idists[842] = 16'h00_09; + idists[843] = 16'h00_09; + idists[844] = 16'h00_09; + idists[845] = 16'h00_09; + idists[846] = 16'h00_09; + idists[847] = 16'h00_09; + idists[848] = 16'h00_09; + idists[849] = 16'h00_09; + idists[850] = 16'h00_09; + idists[851] = 16'h00_09; + idists[852] = 16'h00_09; + idists[853] = 16'h00_09; + idists[854] = 16'h00_09; + idists[855] = 16'h00_09; + idists[856] = 16'h00_09; + idists[857] = 16'h00_09; + idists[858] = 16'h00_09; + idists[859] = 16'h00_09; + idists[860] = 16'h00_09; + idists[861] = 16'h00_09; + idists[862] = 16'h00_09; + idists[863] = 16'h00_09; + idists[864] = 16'h00_09; + idists[865] = 16'h00_09; + idists[866] = 16'h00_09; + idists[867] = 16'h00_09; + idists[868] = 16'h00_09; + idists[869] = 16'h00_09; + idists[870] = 16'h00_09; + idists[871] = 16'h00_09; + idists[872] = 16'h00_09; + idists[873] = 16'h00_09; + idists[874] = 16'h00_09; + idists[875] = 16'h00_09; + idists[876] = 16'h00_09; + idists[877] = 16'h00_09; + idists[878] = 16'h00_09; + idists[879] = 16'h00_09; + idists[880] = 16'h00_09; + idists[881] = 16'h00_09; + idists[882] = 16'h00_09; + idists[883] = 16'h00_09; + idists[884] = 16'h00_09; + idists[885] = 16'h00_09; + idists[886] = 16'h00_09; + idists[887] = 16'h00_09; + idists[888] = 16'h00_09; + idists[889] = 16'h00_09; + idists[890] = 16'h00_09; + idists[891] = 16'h00_09; + idists[892] = 16'h00_09; + idists[893] = 16'h00_09; + idists[894] = 16'h00_09; + idists[895] = 16'h00_09; + idists[896] = 16'h00_09; + idists[897] = 16'h00_09; + idists[898] = 16'h00_09; + idists[899] = 16'h00_09; + idists[900] = 16'h00_09; + idists[901] = 16'h00_09; + idists[902] = 16'h00_09; + idists[903] = 16'h00_09; + idists[904] = 16'h00_09; + idists[905] = 16'h00_09; + idists[906] = 16'h00_09; + idists[907] = 16'h00_09; + idists[908] = 16'h00_09; + idists[909] = 16'h00_09; + idists[910] = 16'h00_08; + idists[911] = 16'h00_08; + idists[912] = 16'h00_08; + idists[913] = 16'h00_08; + idists[914] = 16'h00_08; + idists[915] = 16'h00_08; + idists[916] = 16'h00_08; + idists[917] = 16'h00_08; + idists[918] = 16'h00_08; + idists[919] = 16'h00_08; + idists[920] = 16'h00_08; + idists[921] = 16'h00_08; + idists[922] = 16'h00_08; + idists[923] = 16'h00_08; + idists[924] = 16'h00_08; + idists[925] = 16'h00_08; + idists[926] = 16'h00_08; + idists[927] = 16'h00_08; + idists[928] = 16'h00_08; + idists[929] = 16'h00_08; + idists[930] = 16'h00_08; + idists[931] = 16'h00_08; + idists[932] = 16'h00_08; + idists[933] = 16'h00_08; + idists[934] = 16'h00_08; + idists[935] = 16'h00_08; + idists[936] = 16'h00_08; + idists[937] = 16'h00_08; + idists[938] = 16'h00_08; + idists[939] = 16'h00_08; + idists[940] = 16'h00_08; + idists[941] = 16'h00_08; + idists[942] = 16'h00_08; + idists[943] = 16'h00_08; + idists[944] = 16'h00_08; + idists[945] = 16'h00_08; + idists[946] = 16'h00_08; + idists[947] = 16'h00_08; + idists[948] = 16'h00_08; + idists[949] = 16'h00_08; + idists[950] = 16'h00_08; + idists[951] = 16'h00_08; + idists[952] = 16'h00_08; + idists[953] = 16'h00_08; + idists[954] = 16'h00_08; + idists[955] = 16'h00_08; + idists[956] = 16'h00_08; + idists[957] = 16'h00_08; + idists[958] = 16'h00_08; + idists[959] = 16'h00_08; + idists[960] = 16'h00_08; + idists[961] = 16'h00_08; + idists[962] = 16'h00_08; + idists[963] = 16'h00_08; + idists[964] = 16'h00_08; + idists[965] = 16'h00_08; + idists[966] = 16'h00_08; + idists[967] = 16'h00_08; + idists[968] = 16'h00_08; + idists[969] = 16'h00_08; + idists[970] = 16'h00_08; + idists[971] = 16'h00_08; + idists[972] = 16'h00_08; + idists[973] = 16'h00_08; + idists[974] = 16'h00_08; + idists[975] = 16'h00_08; + idists[976] = 16'h00_08; + idists[977] = 16'h00_08; + idists[978] = 16'h00_08; + idists[979] = 16'h00_08; + idists[980] = 16'h00_08; + idists[981] = 16'h00_08; + idists[982] = 16'h00_08; + idists[983] = 16'h00_08; + idists[984] = 16'h00_08; + idists[985] = 16'h00_08; + idists[986] = 16'h00_08; + idists[987] = 16'h00_08; + idists[988] = 16'h00_08; + idists[989] = 16'h00_08; + idists[990] = 16'h00_08; + idists[991] = 16'h00_08; + idists[992] = 16'h00_08; + idists[993] = 16'h00_08; + idists[994] = 16'h00_08; + idists[995] = 16'h00_08; + idists[996] = 16'h00_08; + idists[997] = 16'h00_08; + idists[998] = 16'h00_08; + idists[999] = 16'h00_08; + idists[1000] = 16'h00_08; + idists[1001] = 16'h00_08; + idists[1002] = 16'h00_08; + idists[1003] = 16'h00_08; + idists[1004] = 16'h00_08; + idists[1005] = 16'h00_08; + idists[1006] = 16'h00_08; + idists[1007] = 16'h00_08; + idists[1008] = 16'h00_08; + idists[1009] = 16'h00_08; + idists[1010] = 16'h00_08; + idists[1011] = 16'h00_08; + idists[1012] = 16'h00_08; + idists[1013] = 16'h00_08; + idists[1014] = 16'h00_08; + idists[1015] = 16'h00_08; + idists[1016] = 16'h00_08; + idists[1017] = 16'h00_08; + idists[1018] = 16'h00_08; + idists[1019] = 16'h00_08; + idists[1020] = 16'h00_08; + idists[1021] = 16'h00_08; + idists[1022] = 16'h00_08; + idists[1023] = 16'h00_08; diff --git a/src/idist_rom.v b/src/idist_rom.v new file mode 100644 index 0000000..5d283c2 --- /dev/null +++ b/src/idist_rom.v @@ -0,0 +1,28 @@ +module idist_rom ( + input clk, + input [9:0] addr, + output [15:0] idist // Q8.8 inverse distance + ); + +reg [15:0] idists [1023:0]; + +reg [15:0] idist_d, idist_q; + +assign idist = idist_q; + +initial begin +`include "idist.rom" +end + +always @(*) begin + if (addr < 10'd1023) + idist_d = idists[addr]; + else + idist_d = 16'd0; +end + +always @(posedge clk) begin + idist_q <= idist_d; +end + +endmodule diff --git a/src/iheight.rom b/src/iheight.rom new file mode 100644 index 0000000..18a8c7f --- /dev/null +++ b/src/iheight.rom @@ -0,0 +1,512 @@ + iheights[0] = 16'h20_00; + iheights[1] = 16'h20_00; + iheights[2] = 16'h10_00; + iheights[3] = 16'h0a_aa; + iheights[4] = 16'h08_00; + iheights[5] = 16'h06_66; + iheights[6] = 16'h05_55; + iheights[7] = 16'h04_92; + iheights[8] = 16'h04_00; + iheights[9] = 16'h03_8e; + iheights[10] = 16'h03_33; + iheights[11] = 16'h02_e8; + iheights[12] = 16'h02_aa; + iheights[13] = 16'h02_76; + iheights[14] = 16'h02_49; + iheights[15] = 16'h02_22; + iheights[16] = 16'h02_00; + iheights[17] = 16'h01_e1; + iheights[18] = 16'h01_c7; + iheights[19] = 16'h01_af; + iheights[20] = 16'h01_99; + iheights[21] = 16'h01_86; + iheights[22] = 16'h01_74; + iheights[23] = 16'h01_64; + iheights[24] = 16'h01_55; + iheights[25] = 16'h01_47; + iheights[26] = 16'h01_3b; + iheights[27] = 16'h01_2f; + iheights[28] = 16'h01_24; + iheights[29] = 16'h01_1a; + iheights[30] = 16'h01_11; + iheights[31] = 16'h01_08; + iheights[32] = 16'h01_00; + iheights[33] = 16'h00_f8; + iheights[34] = 16'h00_f0; + iheights[35] = 16'h00_ea; + iheights[36] = 16'h00_e3; + iheights[37] = 16'h00_dd; + iheights[38] = 16'h00_d7; + iheights[39] = 16'h00_d2; + iheights[40] = 16'h00_cc; + iheights[41] = 16'h00_c7; + iheights[42] = 16'h00_c3; + iheights[43] = 16'h00_be; + iheights[44] = 16'h00_ba; + iheights[45] = 16'h00_b6; + iheights[46] = 16'h00_b2; + iheights[47] = 16'h00_ae; + iheights[48] = 16'h00_aa; + iheights[49] = 16'h00_a7; + iheights[50] = 16'h00_a3; + iheights[51] = 16'h00_a0; + iheights[52] = 16'h00_9d; + iheights[53] = 16'h00_9a; + iheights[54] = 16'h00_97; + iheights[55] = 16'h00_94; + iheights[56] = 16'h00_92; + iheights[57] = 16'h00_8f; + iheights[58] = 16'h00_8d; + iheights[59] = 16'h00_8a; + iheights[60] = 16'h00_88; + iheights[61] = 16'h00_86; + iheights[62] = 16'h00_84; + iheights[63] = 16'h00_82; + iheights[64] = 16'h00_80; + iheights[65] = 16'h00_7e; + iheights[66] = 16'h00_7c; + iheights[67] = 16'h00_7a; + iheights[68] = 16'h00_78; + iheights[69] = 16'h00_76; + iheights[70] = 16'h00_75; + iheights[71] = 16'h00_73; + iheights[72] = 16'h00_71; + iheights[73] = 16'h00_70; + iheights[74] = 16'h00_6e; + iheights[75] = 16'h00_6d; + iheights[76] = 16'h00_6b; + iheights[77] = 16'h00_6a; + iheights[78] = 16'h00_69; + iheights[79] = 16'h00_67; + iheights[80] = 16'h00_66; + iheights[81] = 16'h00_65; + iheights[82] = 16'h00_63; + iheights[83] = 16'h00_62; + iheights[84] = 16'h00_61; + iheights[85] = 16'h00_60; + iheights[86] = 16'h00_5f; + iheights[87] = 16'h00_5e; + iheights[88] = 16'h00_5d; + iheights[89] = 16'h00_5c; + iheights[90] = 16'h00_5b; + iheights[91] = 16'h00_5a; + iheights[92] = 16'h00_59; + iheights[93] = 16'h00_58; + iheights[94] = 16'h00_57; + iheights[95] = 16'h00_56; + iheights[96] = 16'h00_55; + iheights[97] = 16'h00_54; + iheights[98] = 16'h00_53; + iheights[99] = 16'h00_52; + iheights[100] = 16'h00_51; + iheights[101] = 16'h00_51; + iheights[102] = 16'h00_50; + iheights[103] = 16'h00_4f; + iheights[104] = 16'h00_4e; + iheights[105] = 16'h00_4e; + iheights[106] = 16'h00_4d; + iheights[107] = 16'h00_4c; + iheights[108] = 16'h00_4b; + iheights[109] = 16'h00_4b; + iheights[110] = 16'h00_4a; + iheights[111] = 16'h00_49; + iheights[112] = 16'h00_49; + iheights[113] = 16'h00_48; + iheights[114] = 16'h00_47; + iheights[115] = 16'h00_47; + iheights[116] = 16'h00_46; + iheights[117] = 16'h00_46; + iheights[118] = 16'h00_45; + iheights[119] = 16'h00_44; + iheights[120] = 16'h00_44; + iheights[121] = 16'h00_43; + iheights[122] = 16'h00_43; + iheights[123] = 16'h00_42; + iheights[124] = 16'h00_42; + iheights[125] = 16'h00_41; + iheights[126] = 16'h00_41; + iheights[127] = 16'h00_40; + iheights[128] = 16'h00_40; + iheights[129] = 16'h00_3f; + iheights[130] = 16'h00_3f; + iheights[131] = 16'h00_3e; + iheights[132] = 16'h00_3e; + iheights[133] = 16'h00_3d; + iheights[134] = 16'h00_3d; + iheights[135] = 16'h00_3c; + iheights[136] = 16'h00_3c; + iheights[137] = 16'h00_3b; + iheights[138] = 16'h00_3b; + iheights[139] = 16'h00_3a; + iheights[140] = 16'h00_3a; + iheights[141] = 16'h00_3a; + iheights[142] = 16'h00_39; + iheights[143] = 16'h00_39; + iheights[144] = 16'h00_38; + iheights[145] = 16'h00_38; + iheights[146] = 16'h00_38; + iheights[147] = 16'h00_37; + iheights[148] = 16'h00_37; + iheights[149] = 16'h00_36; + iheights[150] = 16'h00_36; + iheights[151] = 16'h00_36; + iheights[152] = 16'h00_35; + iheights[153] = 16'h00_35; + iheights[154] = 16'h00_35; + iheights[155] = 16'h00_34; + iheights[156] = 16'h00_34; + iheights[157] = 16'h00_34; + iheights[158] = 16'h00_33; + iheights[159] = 16'h00_33; + iheights[160] = 16'h00_33; + iheights[161] = 16'h00_32; + iheights[162] = 16'h00_32; + iheights[163] = 16'h00_32; + iheights[164] = 16'h00_31; + iheights[165] = 16'h00_31; + iheights[166] = 16'h00_31; + iheights[167] = 16'h00_31; + iheights[168] = 16'h00_30; + iheights[169] = 16'h00_30; + iheights[170] = 16'h00_30; + iheights[171] = 16'h00_2f; + iheights[172] = 16'h00_2f; + iheights[173] = 16'h00_2f; + iheights[174] = 16'h00_2f; + iheights[175] = 16'h00_2e; + iheights[176] = 16'h00_2e; + iheights[177] = 16'h00_2e; + iheights[178] = 16'h00_2e; + iheights[179] = 16'h00_2d; + iheights[180] = 16'h00_2d; + iheights[181] = 16'h00_2d; + iheights[182] = 16'h00_2d; + iheights[183] = 16'h00_2c; + iheights[184] = 16'h00_2c; + iheights[185] = 16'h00_2c; + iheights[186] = 16'h00_2c; + iheights[187] = 16'h00_2b; + iheights[188] = 16'h00_2b; + iheights[189] = 16'h00_2b; + iheights[190] = 16'h00_2b; + iheights[191] = 16'h00_2a; + iheights[192] = 16'h00_2a; + iheights[193] = 16'h00_2a; + iheights[194] = 16'h00_2a; + iheights[195] = 16'h00_2a; + iheights[196] = 16'h00_29; + iheights[197] = 16'h00_29; + iheights[198] = 16'h00_29; + iheights[199] = 16'h00_29; + iheights[200] = 16'h00_28; + iheights[201] = 16'h00_28; + iheights[202] = 16'h00_28; + iheights[203] = 16'h00_28; + iheights[204] = 16'h00_28; + iheights[205] = 16'h00_27; + iheights[206] = 16'h00_27; + iheights[207] = 16'h00_27; + iheights[208] = 16'h00_27; + iheights[209] = 16'h00_27; + iheights[210] = 16'h00_27; + iheights[211] = 16'h00_26; + iheights[212] = 16'h00_26; + iheights[213] = 16'h00_26; + iheights[214] = 16'h00_26; + iheights[215] = 16'h00_26; + iheights[216] = 16'h00_25; + iheights[217] = 16'h00_25; + iheights[218] = 16'h00_25; + iheights[219] = 16'h00_25; + iheights[220] = 16'h00_25; + iheights[221] = 16'h00_25; + iheights[222] = 16'h00_24; + iheights[223] = 16'h00_24; + iheights[224] = 16'h00_24; + iheights[225] = 16'h00_24; + iheights[226] = 16'h00_24; + iheights[227] = 16'h00_24; + iheights[228] = 16'h00_23; + iheights[229] = 16'h00_23; + iheights[230] = 16'h00_23; + iheights[231] = 16'h00_23; + iheights[232] = 16'h00_23; + iheights[233] = 16'h00_23; + iheights[234] = 16'h00_23; + iheights[235] = 16'h00_22; + iheights[236] = 16'h00_22; + iheights[237] = 16'h00_22; + iheights[238] = 16'h00_22; + iheights[239] = 16'h00_22; + iheights[240] = 16'h00_22; + iheights[241] = 16'h00_21; + iheights[242] = 16'h00_21; + iheights[243] = 16'h00_21; + iheights[244] = 16'h00_21; + iheights[245] = 16'h00_21; + iheights[246] = 16'h00_21; + iheights[247] = 16'h00_21; + iheights[248] = 16'h00_21; + iheights[249] = 16'h00_20; + iheights[250] = 16'h00_20; + iheights[251] = 16'h00_20; + iheights[252] = 16'h00_20; + iheights[253] = 16'h00_20; + iheights[254] = 16'h00_20; + iheights[255] = 16'h00_20; + iheights[256] = 16'h00_20; + iheights[257] = 16'h00_1f; + iheights[258] = 16'h00_1f; + iheights[259] = 16'h00_1f; + iheights[260] = 16'h00_1f; + iheights[261] = 16'h00_1f; + iheights[262] = 16'h00_1f; + iheights[263] = 16'h00_1f; + iheights[264] = 16'h00_1f; + iheights[265] = 16'h00_1e; + iheights[266] = 16'h00_1e; + iheights[267] = 16'h00_1e; + iheights[268] = 16'h00_1e; + iheights[269] = 16'h00_1e; + iheights[270] = 16'h00_1e; + iheights[271] = 16'h00_1e; + iheights[272] = 16'h00_1e; + iheights[273] = 16'h00_1e; + iheights[274] = 16'h00_1d; + iheights[275] = 16'h00_1d; + iheights[276] = 16'h00_1d; + iheights[277] = 16'h00_1d; + iheights[278] = 16'h00_1d; + iheights[279] = 16'h00_1d; + iheights[280] = 16'h00_1d; + iheights[281] = 16'h00_1d; + iheights[282] = 16'h00_1d; + iheights[283] = 16'h00_1c; + iheights[284] = 16'h00_1c; + iheights[285] = 16'h00_1c; + iheights[286] = 16'h00_1c; + iheights[287] = 16'h00_1c; + iheights[288] = 16'h00_1c; + iheights[289] = 16'h00_1c; + iheights[290] = 16'h00_1c; + iheights[291] = 16'h00_1c; + iheights[292] = 16'h00_1c; + iheights[293] = 16'h00_1b; + iheights[294] = 16'h00_1b; + iheights[295] = 16'h00_1b; + iheights[296] = 16'h00_1b; + iheights[297] = 16'h00_1b; + iheights[298] = 16'h00_1b; + iheights[299] = 16'h00_1b; + iheights[300] = 16'h00_1b; + iheights[301] = 16'h00_1b; + iheights[302] = 16'h00_1b; + iheights[303] = 16'h00_1b; + iheights[304] = 16'h00_1a; + iheights[305] = 16'h00_1a; + iheights[306] = 16'h00_1a; + iheights[307] = 16'h00_1a; + iheights[308] = 16'h00_1a; + iheights[309] = 16'h00_1a; + iheights[310] = 16'h00_1a; + iheights[311] = 16'h00_1a; + iheights[312] = 16'h00_1a; + iheights[313] = 16'h00_1a; + iheights[314] = 16'h00_1a; + iheights[315] = 16'h00_1a; + iheights[316] = 16'h00_19; + iheights[317] = 16'h00_19; + iheights[318] = 16'h00_19; + iheights[319] = 16'h00_19; + iheights[320] = 16'h00_19; + iheights[321] = 16'h00_19; + iheights[322] = 16'h00_19; + iheights[323] = 16'h00_19; + iheights[324] = 16'h00_19; + iheights[325] = 16'h00_19; + iheights[326] = 16'h00_19; + iheights[327] = 16'h00_19; + iheights[328] = 16'h00_18; + iheights[329] = 16'h00_18; + iheights[330] = 16'h00_18; + iheights[331] = 16'h00_18; + iheights[332] = 16'h00_18; + iheights[333] = 16'h00_18; + iheights[334] = 16'h00_18; + iheights[335] = 16'h00_18; + iheights[336] = 16'h00_18; + iheights[337] = 16'h00_18; + iheights[338] = 16'h00_18; + iheights[339] = 16'h00_18; + iheights[340] = 16'h00_18; + iheights[341] = 16'h00_18; + iheights[342] = 16'h00_17; + iheights[343] = 16'h00_17; + iheights[344] = 16'h00_17; + iheights[345] = 16'h00_17; + iheights[346] = 16'h00_17; + iheights[347] = 16'h00_17; + iheights[348] = 16'h00_17; + iheights[349] = 16'h00_17; + iheights[350] = 16'h00_17; + iheights[351] = 16'h00_17; + iheights[352] = 16'h00_17; + iheights[353] = 16'h00_17; + iheights[354] = 16'h00_17; + iheights[355] = 16'h00_17; + iheights[356] = 16'h00_17; + iheights[357] = 16'h00_16; + iheights[358] = 16'h00_16; + iheights[359] = 16'h00_16; + iheights[360] = 16'h00_16; + iheights[361] = 16'h00_16; + iheights[362] = 16'h00_16; + iheights[363] = 16'h00_16; + iheights[364] = 16'h00_16; + iheights[365] = 16'h00_16; + iheights[366] = 16'h00_16; + iheights[367] = 16'h00_16; + iheights[368] = 16'h00_16; + iheights[369] = 16'h00_16; + iheights[370] = 16'h00_16; + iheights[371] = 16'h00_16; + iheights[372] = 16'h00_16; + iheights[373] = 16'h00_15; + iheights[374] = 16'h00_15; + iheights[375] = 16'h00_15; + iheights[376] = 16'h00_15; + iheights[377] = 16'h00_15; + iheights[378] = 16'h00_15; + iheights[379] = 16'h00_15; + iheights[380] = 16'h00_15; + iheights[381] = 16'h00_15; + iheights[382] = 16'h00_15; + iheights[383] = 16'h00_15; + iheights[384] = 16'h00_15; + iheights[385] = 16'h00_15; + iheights[386] = 16'h00_15; + iheights[387] = 16'h00_15; + iheights[388] = 16'h00_15; + iheights[389] = 16'h00_15; + iheights[390] = 16'h00_15; + iheights[391] = 16'h00_14; + iheights[392] = 16'h00_14; + iheights[393] = 16'h00_14; + iheights[394] = 16'h00_14; + iheights[395] = 16'h00_14; + iheights[396] = 16'h00_14; + iheights[397] = 16'h00_14; + iheights[398] = 16'h00_14; + iheights[399] = 16'h00_14; + iheights[400] = 16'h00_14; + iheights[401] = 16'h00_14; + iheights[402] = 16'h00_14; + iheights[403] = 16'h00_14; + iheights[404] = 16'h00_14; + iheights[405] = 16'h00_14; + iheights[406] = 16'h00_14; + iheights[407] = 16'h00_14; + iheights[408] = 16'h00_14; + iheights[409] = 16'h00_14; + iheights[410] = 16'h00_13; + iheights[411] = 16'h00_13; + iheights[412] = 16'h00_13; + iheights[413] = 16'h00_13; + iheights[414] = 16'h00_13; + iheights[415] = 16'h00_13; + iheights[416] = 16'h00_13; + iheights[417] = 16'h00_13; + iheights[418] = 16'h00_13; + iheights[419] = 16'h00_13; + iheights[420] = 16'h00_13; + iheights[421] = 16'h00_13; + iheights[422] = 16'h00_13; + iheights[423] = 16'h00_13; + iheights[424] = 16'h00_13; + iheights[425] = 16'h00_13; + iheights[426] = 16'h00_13; + iheights[427] = 16'h00_13; + iheights[428] = 16'h00_13; + iheights[429] = 16'h00_13; + iheights[430] = 16'h00_13; + iheights[431] = 16'h00_13; + iheights[432] = 16'h00_12; + iheights[433] = 16'h00_12; + iheights[434] = 16'h00_12; + iheights[435] = 16'h00_12; + iheights[436] = 16'h00_12; + iheights[437] = 16'h00_12; + iheights[438] = 16'h00_12; + iheights[439] = 16'h00_12; + iheights[440] = 16'h00_12; + iheights[441] = 16'h00_12; + iheights[442] = 16'h00_12; + iheights[443] = 16'h00_12; + iheights[444] = 16'h00_12; + iheights[445] = 16'h00_12; + iheights[446] = 16'h00_12; + iheights[447] = 16'h00_12; + iheights[448] = 16'h00_12; + iheights[449] = 16'h00_12; + iheights[450] = 16'h00_12; + iheights[451] = 16'h00_12; + iheights[452] = 16'h00_12; + iheights[453] = 16'h00_12; + iheights[454] = 16'h00_12; + iheights[455] = 16'h00_12; + iheights[456] = 16'h00_11; + iheights[457] = 16'h00_11; + iheights[458] = 16'h00_11; + iheights[459] = 16'h00_11; + iheights[460] = 16'h00_11; + iheights[461] = 16'h00_11; + iheights[462] = 16'h00_11; + iheights[463] = 16'h00_11; + iheights[464] = 16'h00_11; + iheights[465] = 16'h00_11; + iheights[466] = 16'h00_11; + iheights[467] = 16'h00_11; + iheights[468] = 16'h00_11; + iheights[469] = 16'h00_11; + iheights[470] = 16'h00_11; + iheights[471] = 16'h00_11; + iheights[472] = 16'h00_11; + iheights[473] = 16'h00_11; + iheights[474] = 16'h00_11; + iheights[475] = 16'h00_11; + iheights[476] = 16'h00_11; + iheights[477] = 16'h00_11; + iheights[478] = 16'h00_11; + iheights[479] = 16'h00_11; + iheights[480] = 16'h00_11; + iheights[481] = 16'h00_11; + iheights[482] = 16'h00_10; + iheights[483] = 16'h00_10; + iheights[484] = 16'h00_10; + iheights[485] = 16'h00_10; + iheights[486] = 16'h00_10; + iheights[487] = 16'h00_10; + iheights[488] = 16'h00_10; + iheights[489] = 16'h00_10; + iheights[490] = 16'h00_10; + iheights[491] = 16'h00_10; + iheights[492] = 16'h00_10; + iheights[493] = 16'h00_10; + iheights[494] = 16'h00_10; + iheights[495] = 16'h00_10; + iheights[496] = 16'h00_10; + iheights[497] = 16'h00_10; + iheights[498] = 16'h00_10; + iheights[499] = 16'h00_10; + iheights[500] = 16'h00_10; + iheights[501] = 16'h00_10; + iheights[502] = 16'h00_10; + iheights[503] = 16'h00_10; + iheights[504] = 16'h00_10; + iheights[505] = 16'h00_10; + iheights[506] = 16'h00_10; + iheights[507] = 16'h00_10; + iheights[508] = 16'h00_10; + iheights[509] = 16'h00_10; + iheights[510] = 16'h00_10; + iheights[511] = 16'h00_10; diff --git a/src/iheight_rom.v b/src/iheight_rom.v new file mode 100644 index 0000000..ab2656c --- /dev/null +++ b/src/iheight_rom.v @@ -0,0 +1,25 @@ +module iheight_rom ( + input clk, + input [8:0] addr, + output [15:0] iheight // Q8.8 texture / height + ); + +reg [15:0] iheights [1023:0]; + +reg [15:0] iheight_d, iheight_q; + +assign iheight = iheight_q; + +initial begin +`include "iheight.rom" +end + +always @(*) begin + iheight_d = iheights[addr]; +end + +always @(posedge clk) begin + iheight_q <= iheight_d; +end + +endmodule diff --git a/src/lcd_driver.v b/src/lcd_driver.v new file mode 100644 index 0000000..bbb531f --- /dev/null +++ b/src/lcd_driver.v @@ -0,0 +1,107 @@ +// the actual SPI driver for the LCD runs in a separate clock domain, so we +// need to use the task_crossdomain module to safely signal to the SPI and +// back. This adds a few cycles of delay on either side. +// Further improvements could queue the next byte and ensure the SPI stays +// fed. +module lcd_driver ( + input clk, + input fclk, // faster clock for SPI + input rst, + output lcd_sck, + output lcd_mosi, + output lcd_ss, + output lcd_dcx, // lo: data, hi: cmd + // TODO: backlight and reset. + input [7:0] data_in, // data to write out + input data_dcx, // lo: data, hi: cmd + input start, + output busy, + output reg done // done executing transfer. +); + +localparam STATE_SIZE = 2; +localparam IDLE = 0, + START_TRANSFER = 1, + WAIT_TRANSFER = 2; + +reg [STATE_SIZE-1:0] state_d, state_q; + +reg [7:0] data_d, data_q; + +wire spi_busy; +reg spi_start; +wire spi_start_l, spi_done_l; +reg data_dcx_d, data_dcx_q; + +assign lcd_dcx = data_dcx_q; +assign busy = state_q != IDLE; + +task_crossdomain task_crossdomain( + .clka(clk), // external (slow) clock domain + .taskstart_clka(spi_start), + .taskbusy_clka(spi_busy), + .taskdone_clka(), + .clkb(fclk), // internal (fast) clock domain + .taskstart_clkb(spi_start_l), + .taskbusy_clkb(), + .taskdone_clkb(spi_done_l) +); + +spi #(.CLK_DIV(2)) lcd_spi ( + .clk(fclk), + .rst(rst), + .mosi(lcd_mosi), + .miso(), + .sck(lcd_sck), + .start(spi_start_l), + .ss(lcd_ss), + .data_in(data_q), + .data_out(), + .busy(), + .new_data(spi_done_l) +); + +always @(*) begin + data_dcx_d = data_dcx_q; + data_d = data_q; + spi_start = 1'b0; + done = 1'b0; + state_d = state_q; + + case (state_q) + IDLE: begin + if (start) begin + data_dcx_d = data_dcx; + data_d = data_in; + state_d = START_TRANSFER; + end + end + START_TRANSFER: begin + if (!spi_busy) begin + spi_start = 1'b1; + state_d = WAIT_TRANSFER; + end + end + WAIT_TRANSFER: begin + if (!spi_busy) begin + done = 1'b1; + state_d = IDLE; + end + end + default: state_d = IDLE; + endcase +end + +always @(posedge clk) begin + if (rst) begin + state_q <= IDLE; + data_dcx_q <= 0; + data_q <= 0; + end else begin + state_q <= state_d; + data_dcx_q <= data_dcx_d; + data_q <= data_d; + end +end + +endmodule diff --git a/src/line_writer.v b/src/line_writer.v new file mode 100644 index 0000000..5001b15 --- /dev/null +++ b/src/line_writer.v @@ -0,0 +1,494 @@ +// This module writes lines into a memory buffer, later to be blit to the +// screen. +// It was originally very simple; floors, ceilings, and sprites complicate it +// significantly. +// A few speedups and simplifications are possible: +// 1) mirror floor and ceiling writes (split the RAM into two modules for top +// and bottom half) +// 2) skip floor/ceiling calculations when drawing the wall :P +// 3) move some of the sprite logic (ie; x calculation) out into +// sprite_scanline. +module line_writer ( + input clk, + input rst, + + input start, + input [8:0] x, + input [7:0] pixel, // color, now texture ID. + input [39:0] height, // 39:32 height. 31:16 Q8.8 tex scale. 15:0 inverse dist + input [6:0] tex_x, // texture X offset. + input [15:0] floor_x, + input [15:0] floor_y, + input [15:0] pos_x, + input [15:0] pos_y, + + // signal to ray module whether we're ready to run another line. + output reg rdy, + output reg done, + + // external LCD write reads from memory. + input [RAM_ASIZE:0] ram_raddr, + output [15:0] ram_read_data, + + // external mmap interface loads texture memory. + input [13:0] tram_waddr, + input [3:0] tram_write_data, + input tram_write_en, + // external mmap interface also loads texture palettes. + input [7:0] tpram_waddr, + input [15:0] tpram_write_data, + input tpram_write_en, + // sprites + output reg sprscan_start, + input sprscan_done, + output reg [2:0] sprite_addr, + input [119:0] sprite_meta, + input [2:0] sprite_count +); + +// TODO: Should be a configuration wire. +localparam HALF_HEIGHT = 8'd120; +localparam HEIGHT_MAX = 8'd239; +localparam RAM_ASIZE = 8; +localparam TEX_WIDTH = 32; +localparam TEX_SIZE = 11'd1024; // 32 * 32 +localparam PAL_SIZE = 15; // should be 16 if I skip alpha channel for textures. +localparam FLOOR_OFFSET = 6144; +localparam CEILING_OFFSET = 7168; +localparam FLOOR_PAL = 90; +localparam CEILING_PAL = 105; + +reg [3:0] state_d, state_q; +reg [7:0] count_d, count_q; // number of pixels filled +reg [7:0] color_d, color_q; // hold onto color value +reg [15:0] floor_x_d, floor_x_q; +reg [15:0] floor_y_d, floor_y_q; +reg [15:0] pos_x_d, pos_x_q; +reg [15:0] pos_y_d, pos_y_q; +reg [8:0] camera_x_d, camera_x_q; + +// TODO: these lines are at most 8 bits (240 height) +// there's no reason to not also pre-calc the start/end values into the line +// height table, since the line height is never used. +reg [7:0] draw_start_d, draw_start_q; +reg [7:0] draw_end_d, draw_end_q; +reg [15:0] scale_d, scale_q; +reg [15:0] distwall_d, distwall_q; +reg [21:0] tex_offset_d, tex_offset_q; // Q13.8 -> 20:8 used for TRAM index. +reg [7:0] texp_offset_d, texp_offset_q; +reg [15:0] weight_d, weight_q; +reg [15:0] cfloor_x_d, cfloor_x_q; +reg [15:0] cfloor_y_d, cfloor_y_q; + +// sprites +reg spr_rdy_d, spr_rdy_q; +reg [7:0] spr_texid_d, spr_texid_q; +reg signed [15:0] spr_screenx_d, spr_screenx_q; +reg signed [15:0] spr_height_d, spr_height_q; +reg signed [15:0] spr_starty_d, spr_starty_q; +reg signed [15:0] spr_endy_d, spr_endy_q; +reg signed [15:0] spr_idx_d, spr_idx_q; +reg signed [31:0] spr_iheight_d, spr_iheight_q; +// Q16.16 because I'm an idiot and it always should've been. +reg signed [31:0] spr_tex_x_d, spr_tex_x_q; +// whether an alpha pixel was found. +reg alpha_d, alpha_q; + +// line RAM +reg [RAM_ASIZE:0] waddr_base_d, waddr_base_q; +reg [RAM_ASIZE:0] ram_waddr; +reg [15:0] ram_write_data; +reg ram_write_en; + +// texture RAM +reg [13:0] tram_holdr_d, tram_holdr_q; // extra indirection for sprite writer. +wire [3:0] tram_read_data; +reg [13:0] tram_raddr; +wire [15:0] tpram_read_data; +reg [7:0] tpram_raddr; + +simple_dual_ram #(.SIZE(16), .DEPTH((HEIGHT_MAX+1)*2)) line_ram ( + .wclk(clk), + .waddr(ram_waddr), + .write_data(ram_write_data), + .write_en(ram_write_en), + // read + .rclk(clk), + .raddr(ram_raddr), + .read_data(ram_read_data) +); + +// texture RAM module. holds 32x32 textures with up to 4 bit color. +// would be one fewer wire if mmap owned it, but harder to test bench. +// TODO: simple_dual_ram has equal sized read/write ports. mmap interface can +// write four bytes at once, but to avoid excess logic we're only loading +// one per command. + +simple_dual_ram #(.SIZE(4), .DEPTH(16384)) texture_ram ( + .wclk(clk), + .waddr(tram_waddr), + .write_data(tram_write_data), + .write_en(tram_write_en), + // read + .rclk(clk), + .raddr(tram_raddr), + .read_data(tram_read_data) +); + +simple_dual_ram #(.SIZE(16), .DEPTH(256)) texture_pal_ram ( + .wclk(clk), + .waddr(tpram_waddr), + .write_data(tpram_write_data), + .write_en(tpram_write_en), + // read + .rclk(clk), + .raddr(tpram_raddr), + .read_data(tpram_read_data) +); + +// floor dist precalcs +reg [8:0] fd_addr; +wire [15:0] floordist; +floordist_rom floordist_rom ( + .clk(clk), + .addr(fd_addr), + .floordist(floordist) +); + +// inverse sprite height +reg [8:0] iheight_addr; +wire[15:0] iheight; +iheight_rom iheight_rom ( + .clk(clk), + .addr(iheight_addr), + .iheight(iheight) +); + +localparam IDLE = 0, + FILLING = 1, + FILL_PRECALC = 2, + FILL_PRECALC2 = 3, + FILL_PRECALC3 = 4, + CHECK_PAL = 5, + SPRITE_START = 6, + SPRITE_DRAW = 7, + SPRITE_CALCX = 8, + SPRITE_CALCX2 = 9, + SPRITE_FINDPIXEL = 10, + SPRITE_LOOKUP = 11, + SPRITE_PAL = 12, + SPRITE_FILL = 13, + FINISH = 14; + +initial begin + draw_end_q = 16'd0; + draw_start_q = 16'd0; + color_q = 8'd0; + count_q = 8'd0; +end + +always @(*) begin + state_d = state_q; + count_d = count_q; + camera_x_d = camera_x_q; + draw_start_d = draw_start_q; + draw_end_d = draw_end_q; + scale_d = scale_q; + tex_offset_d = tex_offset_q; + waddr_base_d = waddr_base_q; + ram_waddr = count_q + waddr_base_q; + ram_write_en = 1'b0; + ram_write_data = 8'd0; + rdy = 0; + done = 0; + color_d = color_q; + tram_raddr = tex_offset_q[21:8]; + tpram_raddr = 0; + fd_addr = count_q; + floor_x_d = floor_x_q; + floor_y_d = floor_y_q; + pos_x_d = pos_x_q; + pos_y_d = pos_y_q; + distwall_d = distwall_q; + weight_d = weight_q; + cfloor_x_d = cfloor_x_q; + cfloor_y_d = cfloor_y_q; + texp_offset_d = texp_offset_q; + // sprites + sprscan_start = 1'b0; + spr_rdy_d = spr_rdy_q; + sprite_addr = 3'b0; + iheight_addr = 9'd0; + spr_texid_d = spr_texid_q; + spr_screenx_d = spr_screenx_q; + spr_height_d = spr_height_q; + spr_starty_d = spr_starty_q; + spr_endy_d = spr_endy_q; + spr_iheight_d = spr_iheight_q; + spr_tex_x_d = spr_tex_x_q; + spr_idx_d = spr_idx_q; + alpha_d = alpha_q; + tram_holdr_d = tram_holdr_q; + + // can happen anytime, so log it outside of the state machine. + if (sprscan_done) begin + spr_rdy_d = 1'b1; + end + + case (state_q) + IDLE: begin + if (start) begin + state_d = FILL_PRECALC; + count_d = 0; + color_d = pixel; + /* + * drawStart = -height / 2 + HALF_HEIGHT; + * drawEnd = height / 2 + HALF_HEIGHT + * min(start, 0) + * max(end, HEIGHT) + */ + draw_start_d = ( (~(height[39:32] >> 1)) + 8'd1 ) + HALF_HEIGHT; + draw_end_d = ( height[39:32] >> 1 ) + HALF_HEIGHT; + scale_d = height[31:16]; + distwall_d = height[15:0]; + floor_x_d = floor_x; + floor_y_d = floor_y; + pos_x_d = pos_x; + pos_y_d = pos_y; + // always start with the bottom texture pixel. + // replace the TEX_SIZE "mul" which is getting turned into + // a shift anyway. + tex_offset_d[21:8] = TEX_SIZE * (pixel[3:0] - 1'b1) + (tex_x << 5); + tex_offset_d[7:0] = 8'd0; + texp_offset_d = PAL_SIZE * (pixel[3:0] - 1'b1); + // kick off sprite sorting while we do the wall. + spr_rdy_d = 1'b0; + sprscan_start = 1'b1; + camera_x_d = x - 1'b1; + end else begin + rdy = 1'b1; + end + end + FILL_PRECALC: begin + weight_d = trunc_fixed_mul(floordist * distwall_q); + state_d = FILL_PRECALC2; + end + FILL_PRECALC2: begin + // bits 7:3 are the final texture coordinates + cfloor_x_d = trunc_fixed_mul(weight_q * floor_x_q) + trunc_fixed_mul((16'h01_00 - weight_q) * pos_x_q); + cfloor_y_d = trunc_fixed_mul(weight_q * floor_y_q) + trunc_fixed_mul((16'h01_00 - weight_q) * pos_y_q); + state_d = FILL_PRECALC3; + end + FILL_PRECALC3: begin + // FIXME: Can remove this cycle if adding a bit more to previous + // cycles and filling tram_raddr above. + if (count_q < draw_start_q) begin + tram_raddr = CEILING_OFFSET + (cfloor_x_q[7:3] << 5) + cfloor_y_q[7:3]; + end else if (count_q > draw_end_q) begin + // override the texture RAM lookup if we're casting to the + // floor. + tram_raddr = FLOOR_OFFSET + (cfloor_x_q[7:3] << 5) + cfloor_y_q[7:3]; + end + state_d = CHECK_PAL; + end + CHECK_PAL: begin + tpram_raddr = texp_offset_q + tram_read_data; + if (count_q < draw_start_q) begin + tpram_raddr = CEILING_PAL + tram_read_data; + end else if (count_q > draw_end_q) begin + tpram_raddr = FLOOR_PAL + tram_read_data; + end + state_d = FILLING; + end + FILLING: begin + count_d = count_q + 1'b1; + if (count_q < draw_start_q) begin + // ceiling gets normal color. + ram_write_data = tpram_read_data; + end else if (count_q >= draw_start_q && count_q <= draw_end_q) begin + // if "side", darken the color + // RGB 565 + // FIXME: function. + if (color_q[7]) begin + ram_write_data[15:11] = tpram_read_data[15:11] >> 1; + ram_write_data[10:5] = tpram_read_data[10:5] >> 1; + ram_write_data[4:0] = tpram_read_data[4:0] >> 1; + end else begin + ram_write_data = tpram_read_data; + end + tex_offset_d = tex_offset_q + scale_q; + end else if (count_q > draw_end_q) begin + // floor, darken color. + ram_write_data[15:11] = tpram_read_data[15:11] >> 1; + ram_write_data[10:5] = tpram_read_data[10:5] >> 1; + ram_write_data[4:0] = tpram_read_data[4:0] >> 1; + end + ram_write_en = 1'b1; + + if (count_q == 239) begin + state_d = SPRITE_START; + end else begin + count_d = count_q + 1'b1; + state_d = FILL_PRECALC; + end + end + SPRITE_START: begin + if (spr_rdy_q) begin + if (sprite_count != 3'd0) begin + state_d = SPRITE_DRAW; + end else begin + state_d = FINISH; + end + end + end + SPRITE_DRAW: begin + // 1) load in relevant sprite meta + spr_texid_d = sprite_meta[119:112]; + spr_screenx_d = sprite_meta[95:80]; + spr_height_d = sprite_meta[79:64]; + spr_starty_d = sprite_meta[63:48]; + spr_endy_d = sprite_meta[47:32]; + iheight_addr = spr_height_d[8:0]; + // test data + /*spr_texid_d = 8'd8; + spr_screenx_d = 16'd120; + spr_height_d = 16'd60; + spr_starty_d = 16'd90; + spr_endy_d = 16'd150; + iheight_addr = 16'd60;*/ + + state_d = SPRITE_CALCX; + end + SPRITE_CALCX: begin + // 2) calculate tex_x + spr_tex_x_d = ((spr_height_q >> 1) - (spr_screenx_q - camera_x_q)) << 16; + // Q8.8 - need to convert to Q16.16 + spr_iheight_d = iheight << 8; + state_d = SPRITE_CALCX2; + end + SPRITE_CALCX2: begin + // we only need Q5.0 out of here + spr_tex_x_d = trunc_fixed_mul32(spr_tex_x_q * spr_iheight_q); + // 3) seed tex_offset_d and texp_offset_d + tex_offset_d[21:8] = (spr_texid_q << 10) + (spr_tex_x_d[20:16] << 5); + tex_offset_d[7:0] = 8'd0; + // FIXME: lookup table. (or round it to 16 and shift) + texp_offset_d = PAL_SIZE * spr_texid_q; + // 4) adjust draw boundaries + // seed counter + if (spr_starty_q < 0) begin + spr_starty_d = 0; + // how far we've indexed into the "scaled" sprite. + spr_idx_d = (~spr_starty_q) + 1'b1; + count_d = 0; + end else begin + spr_idx_d = 0; + count_d = spr_starty_q; + end + if (spr_endy_q > HEIGHT_MAX-1) begin + spr_endy_d = HEIGHT_MAX-1; + end + // switch to draw state + state_d = SPRITE_FINDPIXEL; + end + SPRITE_FINDPIXEL: begin + // draaaaaaaaaaaaaaaaawwww + // sadly the Q16.16 multiplication is so large this violates + // timing, so we add the extra cycle of indirection. + // this could be removed if we pre-multiply to find the bottom of + // the sprite and then add the scale offset the same way as + // scaling a wall texture. + tram_holdr_d = (trunc_fixed_mul32((spr_idx_q << 16) * spr_iheight_q) >> 16) + tex_offset_q[21:8]; + state_d = SPRITE_LOOKUP; + end + SPRITE_LOOKUP: begin + tram_raddr = tram_holdr_q; + state_d = SPRITE_PAL; + end + SPRITE_PAL: begin + if (tram_read_data == 4'd15) begin + alpha_d = 1'b1; + end else begin + alpha_d = 1'b0; + tpram_raddr = texp_offset_q + tram_read_data; + end + state_d = SPRITE_FILL; + end + SPRITE_FILL: begin + count_d = count_q + 1'b1; + spr_idx_d = spr_idx_q + 1'b1; + // alpha test. skip transparent sprite pixels. + if (!alpha_q) begin + ram_write_data = tpram_read_data; + ram_write_en = 1'b1; + end + if (count_q == spr_endy_q) begin + state_d = FINISH; + end else begin + state_d = SPRITE_FINDPIXEL; + end + end + FINISH: begin + done = 1'b1; + if (waddr_base_q == 9'd0) begin + waddr_base_d = 9'd240; + end else begin + waddr_base_d = 9'd0; + end + state_d = IDLE; + end + endcase +end + +always @(posedge clk) begin + if (rst) begin + state_q = IDLE; + count_q <= 0; + draw_start_q <= 0; + draw_end_q <= 0; + color_q <= 0; + tex_offset_q <= 0; + waddr_base_q <= 0; + end else begin + state_q = state_d; + count_q <= count_d; + draw_start_q <= draw_start_d; + draw_end_q <= draw_end_d; + color_q <= color_d; + tex_offset_q <= tex_offset_d; + waddr_base_q <= waddr_base_d; + end + + scale_q <= scale_d; + floor_x_q <= floor_x_d; + floor_y_q <= floor_y_d; + pos_x_q <= pos_x_d; + pos_y_q <= pos_y_d; + distwall_q <= distwall_d; + weight_q <= weight_d; + cfloor_x_q <= cfloor_x_d; + cfloor_y_q <= cfloor_y_d; + texp_offset_q <= texp_offset_d; + spr_rdy_q <= spr_rdy_d; + camera_x_q <= camera_x_d; + spr_texid_q <= spr_texid_d; + spr_screenx_q <= spr_screenx_d; + spr_height_q <= spr_height_d; + spr_starty_q <= spr_starty_d; + spr_endy_q <= spr_endy_d; + spr_tex_x_q <= spr_tex_x_d; + spr_iheight_q <= spr_iheight_d; + spr_idx_q <= spr_idx_d; + alpha_q <= alpha_d; + tram_holdr_q <= tram_holdr_d; +end + +function signed [15:0] trunc_fixed_mul(input signed [31:0] mulres); + trunc_fixed_mul = mulres[23:8]; +endfunction + +function signed [31:0] trunc_fixed_mul32(input signed [63:0] mulres); + trunc_fixed_mul32 = mulres[47:16]; +endfunction + +endmodule diff --git a/src/line_writer_tb.v b/src/line_writer_tb.v new file mode 100644 index 0000000..a019e3a --- /dev/null +++ b/src/line_writer_tb.v @@ -0,0 +1,58 @@ +`timescale 1ns / 1ps + +module line_writer_tb( + ); + +reg clk; +reg rst; + +reg start; +reg [7:0] pixel; +reg [23:0] height; +reg [6:0] tex_x; +reg [$clog2(240)-1:0] ram_raddr; +wire [7:0] ram_read_data; + +reg [12:0] tram_waddr; +reg [7:0] tram_write_data; +reg tram_write_en; + +line_writer DUT ( + .clk(clk), + .rst(rst), + .start(start), + .pixel(pixel), + .height(height), + .tex_x(tex_x), + .rdy(rdy), + .ram_raddr(ram_raddr), + .ram_read_data(ram_read_data) +); + + initial begin + clk = 0; + forever #10 clk = ~clk; + end + + initial begin + rst = 1'b1; + repeat(6) @(posedge clk); + rst = 1'b0; + repeat(2) @(posedge clk); + start = 1'b1; + pixel = 8'd1; + height = 24'hee_00_22; + tex_x = 7'd15; + @(posedge clk); + start = 1'b0; + ram_raddr = 8'd100; + repeat(400) @(posedge clk); + #5000 + $finish; + end + + initial begin + #500000000 + $finish; + end +endmodule diff --git a/src/map b/src/map new file mode 100644 index 0000000..364f942 --- /dev/null +++ b/src/map @@ -0,0 +1,25 @@ + {1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1}, + {1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, + {1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, + {1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, + {1,0,0,0,0,0,2,2,2,2,2,0,0,0,0,6,0,7,0,8,0,0,0,1}, + {1,0,0,0,0,0,2,0,0,0,2,0,0,0,0,0,0,0,0,0,0,0,0,1}, + {1,0,0,0,0,0,2,0,0,0,2,0,0,0,0,4,0,0,0,5,0,0,0,1}, + {1,0,0,0,0,0,2,0,0,0,2,0,0,0,0,0,0,0,0,0,0,0,0,1}, + {1,0,0,0,0,0,2,2,0,2,2,0,0,0,0,1,0,2,0,3,0,0,0,1}, + {1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, + {1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, + {1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, + {1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, + {1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, + {1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, + {1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, + {1,4,4,4,4,4,4,4,4,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, + {1,4,0,4,0,0,0,0,4,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, + {1,4,0,0,0,0,5,0,4,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, + {1,4,0,4,0,0,0,0,4,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, + {1,4,0,4,4,4,4,4,4,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, + {1,4,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, + {1,4,4,4,4,4,4,4,4,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, + {1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1}, + diff --git a/src/map.pl b/src/map.pl new file mode 100755 index 0000000..1269d85 --- /dev/null +++ b/src/map.pl @@ -0,0 +1,22 @@ +#!/usr/bin/perl + +use warnings; +use strict; + +my $mfile = $ARGV[0]; + +open(my $fh, "< $mfile") or die "boop: $!"; +my $x = 0; +while (my $l = <$fh>) { + chomp $l; + my $y = 0; + $l =~ s/^\s+//; + $l =~ s/,$//; + $l =~ s/[{}]//g; + for my $col (split(/,/, $l)) { + print " map[$x][$y] = 4'd$col;\n"; + $y++; + } + $x++; +} +close($fh); diff --git a/src/map.rom b/src/map.rom new file mode 100644 index 0000000..fbfcdab --- /dev/null +++ b/src/map.rom @@ -0,0 +1,576 @@ + map[0][0] = 4'd1; + map[0][1] = 4'd1; + map[0][2] = 4'd1; + map[0][3] = 4'd1; + map[0][4] = 4'd1; + map[0][5] = 4'd1; + map[0][6] = 4'd1; + map[0][7] = 4'd1; + map[0][8] = 4'd1; + map[0][9] = 4'd1; + map[0][10] = 4'd1; + map[0][11] = 4'd1; + map[0][12] = 4'd1; + map[0][13] = 4'd1; + map[0][14] = 4'd1; + map[0][15] = 4'd1; + map[0][16] = 4'd1; + map[0][17] = 4'd1; + map[0][18] = 4'd1; + map[0][19] = 4'd1; + map[0][20] = 4'd1; + map[0][21] = 4'd1; + map[0][22] = 4'd1; + map[0][23] = 4'd1; + map[1][0] = 4'd1; + map[1][1] = 4'd0; + map[1][2] = 4'd0; + map[1][3] = 4'd0; + map[1][4] = 4'd0; + map[1][5] = 4'd0; + map[1][6] = 4'd0; + map[1][7] = 4'd0; + map[1][8] = 4'd0; + map[1][9] = 4'd0; + map[1][10] = 4'd0; + map[1][11] = 4'd0; + map[1][12] = 4'd0; + map[1][13] = 4'd0; + map[1][14] = 4'd0; + map[1][15] = 4'd0; + map[1][16] = 4'd0; + map[1][17] = 4'd0; + map[1][18] = 4'd0; + map[1][19] = 4'd0; + map[1][20] = 4'd0; + map[1][21] = 4'd0; + map[1][22] = 4'd0; + map[1][23] = 4'd1; + map[2][0] = 4'd1; + map[2][1] = 4'd0; + map[2][2] = 4'd0; + map[2][3] = 4'd0; + map[2][4] = 4'd0; + map[2][5] = 4'd0; + map[2][6] = 4'd0; + map[2][7] = 4'd0; + map[2][8] = 4'd0; + map[2][9] = 4'd0; + map[2][10] = 4'd0; + map[2][11] = 4'd0; + map[2][12] = 4'd0; + map[2][13] = 4'd0; + map[2][14] = 4'd0; + map[2][15] = 4'd0; + map[2][16] = 4'd0; + map[2][17] = 4'd0; + map[2][18] = 4'd0; + map[2][19] = 4'd0; + map[2][20] = 4'd0; + map[2][21] = 4'd0; + map[2][22] = 4'd0; + map[2][23] = 4'd1; + map[3][0] = 4'd1; + map[3][1] = 4'd0; + map[3][2] = 4'd0; + map[3][3] = 4'd0; + map[3][4] = 4'd0; + map[3][5] = 4'd0; + map[3][6] = 4'd0; + map[3][7] = 4'd0; + map[3][8] = 4'd0; + map[3][9] = 4'd0; + map[3][10] = 4'd0; + map[3][11] = 4'd0; + map[3][12] = 4'd0; + map[3][13] = 4'd0; + map[3][14] = 4'd0; + map[3][15] = 4'd0; + map[3][16] = 4'd0; + map[3][17] = 4'd0; + map[3][18] = 4'd0; + map[3][19] = 4'd0; + map[3][20] = 4'd0; + map[3][21] = 4'd0; + map[3][22] = 4'd0; + map[3][23] = 4'd1; + map[4][0] = 4'd1; + map[4][1] = 4'd0; + map[4][2] = 4'd0; + map[4][3] = 4'd0; + map[4][4] = 4'd0; + map[4][5] = 4'd0; + map[4][6] = 4'd2; + map[4][7] = 4'd2; + map[4][8] = 4'd2; + map[4][9] = 4'd2; + map[4][10] = 4'd2; + map[4][11] = 4'd0; + map[4][12] = 4'd0; + map[4][13] = 4'd0; + map[4][14] = 4'd0; + map[4][15] = 4'd6; + map[4][16] = 4'd0; + map[4][17] = 4'd7; + map[4][18] = 4'd0; + map[4][19] = 4'd8; + map[4][20] = 4'd0; + map[4][21] = 4'd0; + map[4][22] = 4'd0; + map[4][23] = 4'd1; + map[5][0] = 4'd1; + map[5][1] = 4'd0; + map[5][2] = 4'd0; + map[5][3] = 4'd0; + map[5][4] = 4'd0; + map[5][5] = 4'd0; + map[5][6] = 4'd2; + map[5][7] = 4'd0; + map[5][8] = 4'd0; + map[5][9] = 4'd0; + map[5][10] = 4'd2; + map[5][11] = 4'd0; + map[5][12] = 4'd0; + map[5][13] = 4'd0; + map[5][14] = 4'd0; + map[5][15] = 4'd0; + map[5][16] = 4'd0; + map[5][17] = 4'd0; + map[5][18] = 4'd0; + map[5][19] = 4'd0; + map[5][20] = 4'd0; + map[5][21] = 4'd0; + map[5][22] = 4'd0; + map[5][23] = 4'd1; + map[6][0] = 4'd1; + map[6][1] = 4'd0; + map[6][2] = 4'd0; + map[6][3] = 4'd0; + map[6][4] = 4'd0; + map[6][5] = 4'd0; + map[6][6] = 4'd2; + map[6][7] = 4'd0; + map[6][8] = 4'd0; + map[6][9] = 4'd0; + map[6][10] = 4'd2; + map[6][11] = 4'd0; + map[6][12] = 4'd0; + map[6][13] = 4'd0; + map[6][14] = 4'd0; + map[6][15] = 4'd4; + map[6][16] = 4'd0; + map[6][17] = 4'd0; + map[6][18] = 4'd0; + map[6][19] = 4'd5; + map[6][20] = 4'd0; + map[6][21] = 4'd0; + map[6][22] = 4'd0; + map[6][23] = 4'd1; + map[7][0] = 4'd1; + map[7][1] = 4'd0; + map[7][2] = 4'd0; + map[7][3] = 4'd0; + map[7][4] = 4'd0; + map[7][5] = 4'd0; + map[7][6] = 4'd2; + map[7][7] = 4'd0; + map[7][8] = 4'd0; + map[7][9] = 4'd0; + map[7][10] = 4'd2; + map[7][11] = 4'd0; + map[7][12] = 4'd0; + map[7][13] = 4'd0; + map[7][14] = 4'd0; + map[7][15] = 4'd0; + map[7][16] = 4'd0; + map[7][17] = 4'd0; + map[7][18] = 4'd0; + map[7][19] = 4'd0; + map[7][20] = 4'd0; + map[7][21] = 4'd0; + map[7][22] = 4'd0; + map[7][23] = 4'd1; + map[8][0] = 4'd1; + map[8][1] = 4'd0; + map[8][2] = 4'd0; + map[8][3] = 4'd0; + map[8][4] = 4'd0; + map[8][5] = 4'd0; + map[8][6] = 4'd0; + map[8][7] = 4'd0; + map[8][8] = 4'd0; + map[8][9] = 4'd0; + map[8][10] = 4'd0; + map[8][11] = 4'd0; + map[8][12] = 4'd0; + map[8][13] = 4'd0; + map[8][14] = 4'd0; + map[8][15] = 4'd1; + map[8][16] = 4'd0; + map[8][17] = 4'd2; + map[8][18] = 4'd0; + map[8][19] = 4'd3; + map[8][20] = 4'd0; + map[8][21] = 4'd0; + map[8][22] = 4'd0; + map[8][23] = 4'd1; + map[9][0] = 4'd1; + map[9][1] = 4'd0; + map[9][2] = 4'd0; + map[9][3] = 4'd0; + map[9][4] = 4'd0; + map[9][5] = 4'd0; + map[9][6] = 4'd0; + map[9][7] = 4'd0; + map[9][8] = 4'd0; + map[9][9] = 4'd0; + map[9][10] = 4'd0; + map[9][11] = 4'd0; + map[9][12] = 4'd0; + map[9][13] = 4'd0; + map[9][14] = 4'd0; + map[9][15] = 4'd0; + map[9][16] = 4'd0; + map[9][17] = 4'd0; + map[9][18] = 4'd0; + map[9][19] = 4'd0; + map[9][20] = 4'd0; + map[9][21] = 4'd0; + map[9][22] = 4'd0; + map[9][23] = 4'd1; + map[10][0] = 4'd1; + map[10][1] = 4'd0; + map[10][2] = 4'd0; + map[10][3] = 4'd0; + map[10][4] = 4'd0; + map[10][5] = 4'd0; + map[10][6] = 4'd0; + map[10][7] = 4'd0; + map[10][8] = 4'd0; + map[10][9] = 4'd0; + map[10][10] = 4'd0; + map[10][11] = 4'd0; + map[10][12] = 4'd0; + map[10][13] = 4'd0; + map[10][14] = 4'd0; + map[10][15] = 4'd0; + map[10][16] = 4'd0; + map[10][17] = 4'd0; + map[10][18] = 4'd0; + map[10][19] = 4'd0; + map[10][20] = 4'd0; + map[10][21] = 4'd0; + map[10][22] = 4'd0; + map[10][23] = 4'd1; + map[11][0] = 4'd1; + map[11][1] = 4'd0; + map[11][2] = 4'd0; + map[11][3] = 4'd0; + map[11][4] = 4'd0; + map[11][5] = 4'd0; + map[11][6] = 4'd0; + map[11][7] = 4'd0; + map[11][8] = 4'd0; + map[11][9] = 4'd0; + map[11][10] = 4'd0; + map[11][11] = 4'd0; + map[11][12] = 4'd0; + map[11][13] = 4'd0; + map[11][14] = 4'd0; + map[11][15] = 4'd0; + map[11][16] = 4'd0; + map[11][17] = 4'd0; + map[11][18] = 4'd0; + map[11][19] = 4'd0; + map[11][20] = 4'd0; + map[11][21] = 4'd0; + map[11][22] = 4'd0; + map[11][23] = 4'd1; + map[12][0] = 4'd1; + map[12][1] = 4'd0; + map[12][2] = 4'd0; + map[12][3] = 4'd0; + map[12][4] = 4'd0; + map[12][5] = 4'd0; + map[12][6] = 4'd0; + map[12][7] = 4'd0; + map[12][8] = 4'd0; + map[12][9] = 4'd0; + map[12][10] = 4'd0; + map[12][11] = 4'd0; + map[12][12] = 4'd0; + map[12][13] = 4'd0; + map[12][14] = 4'd0; + map[12][15] = 4'd0; + map[12][16] = 4'd0; + map[12][17] = 4'd0; + map[12][18] = 4'd0; + map[12][19] = 4'd0; + map[12][20] = 4'd0; + map[12][21] = 4'd0; + map[12][22] = 4'd0; + map[12][23] = 4'd1; + map[13][0] = 4'd1; + map[13][1] = 4'd0; + map[13][2] = 4'd0; + map[13][3] = 4'd0; + map[13][4] = 4'd0; + map[13][5] = 4'd0; + map[13][6] = 4'd0; + map[13][7] = 4'd0; + map[13][8] = 4'd0; + map[13][9] = 4'd0; + map[13][10] = 4'd0; + map[13][11] = 4'd0; + map[13][12] = 4'd0; + map[13][13] = 4'd0; + map[13][14] = 4'd0; + map[13][15] = 4'd0; + map[13][16] = 4'd0; + map[13][17] = 4'd0; + map[13][18] = 4'd0; + map[13][19] = 4'd0; + map[13][20] = 4'd0; + map[13][21] = 4'd0; + map[13][22] = 4'd0; + map[13][23] = 4'd1; + map[14][0] = 4'd1; + map[14][1] = 4'd0; + map[14][2] = 4'd0; + map[14][3] = 4'd0; + map[14][4] = 4'd0; + map[14][5] = 4'd0; + map[14][6] = 4'd0; + map[14][7] = 4'd0; + map[14][8] = 4'd0; + map[14][9] = 4'd0; + map[14][10] = 4'd0; + map[14][11] = 4'd0; + map[14][12] = 4'd0; + map[14][13] = 4'd0; + map[14][14] = 4'd0; + map[14][15] = 4'd0; + map[14][16] = 4'd0; + map[14][17] = 4'd0; + map[14][18] = 4'd0; + map[14][19] = 4'd0; + map[14][20] = 4'd0; + map[14][21] = 4'd0; + map[14][22] = 4'd0; + map[14][23] = 4'd1; + map[15][0] = 4'd1; + map[15][1] = 4'd0; + map[15][2] = 4'd0; + map[15][3] = 4'd0; + map[15][4] = 4'd0; + map[15][5] = 4'd0; + map[15][6] = 4'd0; + map[15][7] = 4'd0; + map[15][8] = 4'd0; + map[15][9] = 4'd0; + map[15][10] = 4'd0; + map[15][11] = 4'd0; + map[15][12] = 4'd0; + map[15][13] = 4'd0; + map[15][14] = 4'd0; + map[15][15] = 4'd0; + map[15][16] = 4'd0; + map[15][17] = 4'd0; + map[15][18] = 4'd0; + map[15][19] = 4'd0; + map[15][20] = 4'd0; + map[15][21] = 4'd0; + map[15][22] = 4'd0; + map[15][23] = 4'd1; + map[16][0] = 4'd1; + map[16][1] = 4'd4; + map[16][2] = 4'd4; + map[16][3] = 4'd4; + map[16][4] = 4'd4; + map[16][5] = 4'd4; + map[16][6] = 4'd4; + map[16][7] = 4'd4; + map[16][8] = 4'd4; + map[16][9] = 4'd0; + map[16][10] = 4'd0; + map[16][11] = 4'd0; + map[16][12] = 4'd0; + map[16][13] = 4'd0; + map[16][14] = 4'd0; + map[16][15] = 4'd0; + map[16][16] = 4'd0; + map[16][17] = 4'd0; + map[16][18] = 4'd0; + map[16][19] = 4'd0; + map[16][20] = 4'd0; + map[16][21] = 4'd0; + map[16][22] = 4'd0; + map[16][23] = 4'd1; + map[17][0] = 4'd1; + map[17][1] = 4'd4; + map[17][2] = 4'd0; + map[17][3] = 4'd4; + map[17][4] = 4'd0; + map[17][5] = 4'd0; + map[17][6] = 4'd0; + map[17][7] = 4'd0; + map[17][8] = 4'd0; + map[17][9] = 4'd0; + map[17][10] = 4'd0; + map[17][11] = 4'd0; + map[17][12] = 4'd0; + map[17][13] = 4'd0; + map[17][14] = 4'd0; + map[17][15] = 4'd0; + map[17][16] = 4'd0; + map[17][17] = 4'd0; + map[17][18] = 4'd0; + map[17][19] = 4'd0; + map[17][20] = 4'd0; + map[17][21] = 4'd0; + map[17][22] = 4'd0; + map[17][23] = 4'd1; + map[18][0] = 4'd1; + map[18][1] = 4'd4; + map[18][2] = 4'd0; + map[18][3] = 4'd0; + map[18][4] = 4'd0; + map[18][5] = 4'd0; + map[18][6] = 4'd5; + map[18][7] = 4'd0; + map[18][8] = 4'd0; + map[18][9] = 4'd0; + map[18][10] = 4'd0; + map[18][11] = 4'd0; + map[18][12] = 4'd0; + map[18][13] = 4'd0; + map[18][14] = 4'd0; + map[18][15] = 4'd0; + map[18][16] = 4'd0; + map[18][17] = 4'd0; + map[18][18] = 4'd0; + map[18][19] = 4'd0; + map[18][20] = 4'd0; + map[18][21] = 4'd0; + map[18][22] = 4'd0; + map[18][23] = 4'd1; + map[19][0] = 4'd1; + map[19][1] = 4'd4; + map[19][2] = 4'd0; + map[19][3] = 4'd4; + map[19][4] = 4'd0; + map[19][5] = 4'd0; + map[19][6] = 4'd0; + map[19][7] = 4'd0; + map[19][8] = 4'd0; + map[19][9] = 4'd0; + map[19][10] = 4'd0; + map[19][11] = 4'd0; + map[19][12] = 4'd0; + map[19][13] = 4'd0; + map[19][14] = 4'd0; + map[19][15] = 4'd0; + map[19][16] = 4'd0; + map[19][17] = 4'd0; + map[19][18] = 4'd0; + map[19][19] = 4'd0; + map[19][20] = 4'd0; + map[19][21] = 4'd0; + map[19][22] = 4'd0; + map[19][23] = 4'd1; + map[20][0] = 4'd1; + map[20][1] = 4'd4; + map[20][2] = 4'd0; + map[20][3] = 4'd4; + map[20][4] = 4'd4; + map[20][5] = 4'd4; + map[20][6] = 4'd4; + map[20][7] = 4'd4; + map[20][8] = 4'd0; + map[20][9] = 4'd0; + map[20][10] = 4'd0; + map[20][11] = 4'd0; + map[20][12] = 4'd0; + map[20][13] = 4'd0; + map[20][14] = 4'd0; + map[20][15] = 4'd0; + map[20][16] = 4'd0; + map[20][17] = 4'd0; + map[20][18] = 4'd0; + map[20][19] = 4'd0; + map[20][20] = 4'd0; + map[20][21] = 4'd0; + map[20][22] = 4'd0; + map[20][23] = 4'd1; + map[21][0] = 4'd1; + map[21][1] = 4'd4; + map[21][2] = 4'd0; + map[21][3] = 4'd0; + map[21][4] = 4'd0; + map[21][5] = 4'd0; + map[21][6] = 4'd0; + map[21][7] = 4'd0; + map[21][8] = 4'd0; + map[21][9] = 4'd0; + map[21][10] = 4'd0; + map[21][11] = 4'd0; + map[21][12] = 4'd0; + map[21][13] = 4'd0; + map[21][14] = 4'd0; + map[21][15] = 4'd0; + map[21][16] = 4'd0; + map[21][17] = 4'd0; + map[21][18] = 4'd0; + map[21][19] = 4'd0; + map[21][20] = 4'd0; + map[21][21] = 4'd0; + map[21][22] = 4'd0; + map[21][23] = 4'd1; + map[22][0] = 4'd1; + map[22][1] = 4'd4; + map[22][2] = 4'd4; + map[22][3] = 4'd4; + map[22][4] = 4'd4; + map[22][5] = 4'd4; + map[22][6] = 4'd4; + map[22][7] = 4'd4; + map[22][8] = 4'd0; + map[22][9] = 4'd0; + map[22][10] = 4'd0; + map[22][11] = 4'd0; + map[22][12] = 4'd0; + map[22][13] = 4'd0; + map[22][14] = 4'd0; + map[22][15] = 4'd0; + map[22][16] = 4'd0; + map[22][17] = 4'd0; + map[22][18] = 4'd0; + map[22][19] = 4'd0; + map[22][20] = 4'd0; + map[22][21] = 4'd0; + map[22][22] = 4'd0; + map[22][23] = 4'd1; + map[23][0] = 4'd1; + map[23][1] = 4'd1; + map[23][2] = 4'd1; + map[23][3] = 4'd1; + map[23][4] = 4'd1; + map[23][5] = 4'd1; + map[23][6] = 4'd1; + map[23][7] = 4'd1; + map[23][8] = 4'd1; + map[23][9] = 4'd1; + map[23][10] = 4'd1; + map[23][11] = 4'd1; + map[23][12] = 4'd1; + map[23][13] = 4'd1; + map[23][14] = 4'd1; + map[23][15] = 4'd1; + map[23][16] = 4'd1; + map[23][17] = 4'd1; + map[23][18] = 4'd1; + map[23][19] = 4'd1; + map[23][20] = 4'd1; + map[23][21] = 4'd1; + map[23][22] = 4'd1; + map[23][23] = 4'd1; diff --git a/src/map2 b/src/map2 new file mode 100644 index 0000000..39393fc --- /dev/null +++ b/src/map2 @@ -0,0 +1,24 @@ + {8,8,8,8,8,8,8,8,8,8,8,4,4,6,4,4,6,4,6,4,4,4,6,4}, + {8,0,0,0,0,0,0,0,0,0,8,4,0,0,0,0,0,0,0,0,0,0,0,4}, + {8,0,3,3,0,0,0,0,0,8,8,4,0,0,0,0,0,0,0,0,0,0,0,6}, + {8,0,0,3,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,6}, + {8,0,3,3,0,0,0,0,0,8,8,4,0,0,0,0,0,0,0,0,0,0,0,4}, + {8,0,0,0,0,0,0,0,0,0,8,4,0,0,0,0,0,6,6,6,0,6,4,6}, + {8,8,8,8,0,8,8,8,8,8,8,4,4,4,4,4,4,6,0,0,0,0,0,6}, + {7,7,7,7,0,7,7,7,7,0,8,0,8,0,8,0,8,4,0,4,0,6,0,6}, + {7,7,0,0,0,0,0,0,7,8,0,8,0,8,0,8,8,6,0,0,0,0,0,6}, + {7,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,8,6,0,0,0,0,0,4}, + {7,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,8,6,0,6,0,6,0,6}, + {7,7,0,0,0,0,0,0,7,8,0,8,0,8,0,8,8,6,4,6,0,6,6,6}, + {7,7,7,7,0,7,7,7,7,8,8,4,0,6,8,4,8,3,3,3,0,3,3,3}, + {2,2,2,2,0,2,2,2,2,4,6,4,0,0,6,0,6,3,0,0,0,0,0,3}, + {2,2,0,0,0,0,0,2,2,4,0,0,0,0,0,0,4,3,0,0,0,0,0,3}, + {2,0,0,0,0,0,0,0,2,4,0,0,0,0,0,0,4,3,0,0,0,0,0,3}, + {1,0,0,0,0,0,0,0,1,4,4,4,4,4,6,0,6,3,3,0,0,0,3,3}, + {2,0,0,0,0,0,0,0,2,2,2,1,2,2,2,6,6,0,0,5,0,5,0,5}, + {2,2,0,0,0,0,0,2,2,2,0,0,0,2,2,0,5,0,5,0,0,0,5,5}, + {2,0,0,0,0,0,0,0,2,0,0,0,0,0,2,5,0,5,0,5,0,5,0,5}, + {1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,5}, + {2,0,0,0,0,0,0,0,2,0,0,0,0,0,2,5,0,5,0,5,0,5,0,5}, + {2,2,0,0,0,0,0,2,2,2,0,0,0,2,2,0,5,0,5,0,0,0,5,5}, + {2,2,2,2,1,2,2,2,2,2,2,1,2,2,2,5,5,5,5,5,5,5,5,5} diff --git a/src/map3 b/src/map3 new file mode 100644 index 0000000..04be3d1 --- /dev/null +++ b/src/map3 @@ -0,0 +1,25 @@ + {1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1}, + {1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, + {1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, + {1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, + {1,0,0,0,0,0,2,2,2,2,2,0,0,0,0,6,0,7,0,8,0,0,0,1}, + {1,0,0,0,0,0,2,0,0,0,2,0,0,0,0,0,0,0,0,0,0,0,0,1}, + {1,0,0,0,0,0,2,0,0,0,2,0,0,0,0,4,0,0,0,5,0,0,0,1}, + {1,0,0,0,0,0,2,0,0,0,2,0,0,0,0,0,0,0,0,0,0,0,0,1}, + {1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,2,0,3,0,0,0,1}, + {1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, + {1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, + {1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, + {1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, + {1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, + {1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, + {1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, + {1,4,4,4,4,4,4,4,4,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, + {1,4,0,4,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, + {1,4,0,0,0,0,5,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, + {1,4,0,4,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, + {1,4,0,4,4,4,4,4,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, + {1,4,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, + {1,4,4,4,4,4,4,4,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, + {1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1}, + diff --git a/src/map_rom.v b/src/map_rom.v new file mode 100644 index 0000000..ef51686 --- /dev/null +++ b/src/map_rom.v @@ -0,0 +1,20 @@ +module map_rom ( + input [7:0] x, + input [7:0] y, + output reg [3:0] point + ); + +reg [3:0] map [23:0][23:0]; + +initial begin +`include "map.rom" +end + +always @(*) begin + if (x < 24 && y < 24) + point = map[x][y]; + else + point = 4'd1; +end + +endmodule diff --git a/src/mmap.v b/src/mmap.v new file mode 100644 index 0000000..9378387 --- /dev/null +++ b/src/mmap.v @@ -0,0 +1,223 @@ +/* + This module adapted from reg_interface.luc from embedded micro. + // 1 CMD byte: + // 5:0 CMD - up to 64 different GPU commands + // 6 inc it + // 7 wr bit + // 16bit data packet count (could possibly encode) + // 32bit addr + // 32bit data [up to repeat count] + // is zero an acceptable count? + // NOTE: Not exposing the run count + // if inc -> addr += 4 per run + */ + +module mmap_protocol #( + parameter CLK_FREQ = 50000000 + )( + input clk, + input rst, + + // Serial RX + input [7:0] rx_data, + input new_rx_data, + + // Serial TX + output reg [7:0] tx_data, + output reg new_tx_data, + input tx_busy, + + // Master interface + output reg m_new_cmd, + output reg m_write, + output [5:0] m_cmd, + output [31:0] m_address, + output [31:0] m_data, + + // Slave interface + input [31:0] s_data, + input s_drdy +); + +localparam STATE_SIZE = 4; +localparam IDLE = 0, + GET_ADDR = 1, + WRITE = 2, + REQUEST_WRITE = 3, + REQUEST_READ = 4, + WAIT_READ = 5, + READ_RESULT = 6, + GET_PCOUNT = 7; + +reg [STATE_SIZE-1:0] state_d, state_q; + +reg [5:0] cmd_d, cmd_q; +reg [15:0] addr_ct_d, addr_ct_q; +reg [1:0] byte_ct_d, byte_ct_q; +reg inc_d, inc_q; // address increment bit +reg wr_d, wr_q; // write request bit +reg [$clog2(CLK_FREQ/2):0] timeout_d, timeout_q; // timeout counter +//reg [31:0] timeout; // timeout counter +reg [31:0] addr_d, addr_q; // saved address +reg [31:0] data_d, data_q; // saved data +//reg [1:0] delay; // hmm + +assign m_data = data_q; +assign m_cmd = cmd_q; +assign m_address = addr_q; + +always @(*) begin + // incremnt timeout, or reset if new data is avilable. + timeout_d = timeout_q + 1'b1; + if (new_rx_data) + timeout_d = 0; + + // defaults. + m_new_cmd = 0; + m_write = 0; + tx_data = 7'bx; + wr_d = wr_q; + inc_d = inc_q; + state_d = state_q; + byte_ct_d = byte_ct_q; + data_d = data_q; + addr_d = addr_q; + addr_ct_d = addr_ct_q; + cmd_d = cmd_q; + new_tx_data = 0; + + case (state_q) + IDLE: begin + timeout_d = 0; + byte_ct_d = 0; + + if (new_rx_data) begin + wr_d = rx_data[7]; + inc_d = rx_data[6]; + cmd_d = rx_data[5:0]; + state_d = GET_PCOUNT; + end + end + GET_PCOUNT: begin + // number of four byte data packets to read + if (new_rx_data) begin + addr_ct_d = {rx_data, addr_ct_q[15-:8]}; + byte_ct_d = byte_ct_q + 1'b1; + if (byte_ct_q == 2'd1) begin + byte_ct_d = 2'd0; + state_d = GET_ADDR; + end + end + end + GET_ADDR: begin + if (new_rx_data) begin + addr_d = {rx_data, addr_q[31-:24]}; // shift in a byte + byte_ct_d = byte_ct_q + 1'b1; + if (byte_ct_q == 2'd3) begin + if (wr_q) begin + state_d = WRITE; + end else begin + state_d = REQUEST_READ; + end + end + end + end + WRITE: begin + if (new_rx_data) begin + data_d = {rx_data, data_q[31-:24]}; + byte_ct_d = byte_ct_q + 1'b1; + if (byte_ct_q == 2'd3) begin + state_d = REQUEST_WRITE; + end + end + end + REQUEST_WRITE: begin + m_new_cmd = 1'b1; + m_write = 1'b1; + addr_ct_d = addr_ct_q - 1'b1; + if (addr_ct_q == 1'b0) begin + state_d = IDLE; + end else begin + state_d = WRITE; + if (inc_q) begin + addr_d = addr_q + 1'd1; + end + end + end + REQUEST_READ: begin + m_new_cmd = 1'b1; + m_write = 0; + //delay <= {2{1'b1}}; + if (s_drdy) begin + byte_ct_d = 2'd0; + data_d = s_data; + state_d = READ_RESULT; + end else begin + state_d = WAIT_READ; + end + end + WAIT_READ: begin + if (s_drdy) begin + byte_ct_d = 2'd0; + data_d = s_data; + state_d = READ_RESULT; + end + end + READ_RESULT: begin + timeout_d = 0; + //delay <= delay - 1'b1; + //if (!tx_busy && delay == {2{1'b0}}) begin + if (!tx_busy) begin + //delay <= {2{1'b1}}; + tx_data = data_q[7:0]; + data_d = data_q >> 8; + new_tx_data = 1'b1; + byte_ct_d = byte_ct_q + 1'b1; + if (byte_ct_q == 2'd3) begin + addr_ct_d = addr_ct_q - 1'b1; + if (addr_ct_q == 0) begin + state_d = IDLE; + end else begin + state_d = REQUEST_READ; + if (inc_q) begin + addr_d = addr_q + 1'd1; + end + end + end + end + end + default: state_d = IDLE; + endcase + + if (&timeout_q) begin + state_d = IDLE; + end +end + +always @(posedge clk) begin + if (rst) begin + state_q <= IDLE; + addr_ct_q <= 0; + byte_ct_q <= 0; + inc_q <= 0; + wr_q <= 0; + data_q <= 0; + addr_q <= 0; + cmd_q <= 0; + //delay_q <= 0; + end else begin + timeout_q <= timeout_d; + //m_new_cmd_q <= m_new_cmd_d; + //m_write_q <= m_write_d; + cmd_q <= cmd_d; + wr_q <= wr_d; + inc_q <= inc_d; + state_q <= state_d; + data_q <= data_d; + addr_q <= addr_d; + byte_ct_q <= byte_ct_d; + addr_ct_q <= addr_ct_d; + end +end + +endmodule diff --git a/src/mmap_leds.v b/src/mmap_leds.v new file mode 100644 index 0000000..e6c97a9 --- /dev/null +++ b/src/mmap_leds.v @@ -0,0 +1,460 @@ +// ignore the file being called _leds.v :P +// this central interface consumes the memory mapped protocol and controls the +// rest of the design, including rendering. +module mmap_interface ( + input clk, + input rst, + + output [2:0] leds, + output flush_busy, + + // Master interface + input m_new_cmd, + input m_write, + input [5:0] m_cmd, + input [31:0] m_address, + input [31:0] m_data, + + // Slave interface + output [31:0] s_data, + output s_drdy, + + // share output angle to other modules + output [79:0] angle, + + // ray caster wires + output reg [8:0] cast_x, + output [15:0] map_pos_x, + output [15:0] map_pos_y, + output reg cast_start, + input cast_busy, + input cast_done, + + // line writer + input [39:0] line_height, // observed line height + input line_write_ready, + input line_write_done, + output reg line_write_start, + output [8:0] line_ram_raddr, + input [15:0] line_ram_read_data, + // line writer texture memory. + output reg [13:0] tram_waddr, + output reg [3:0] tram_write_data, + output reg tram_write_en, + output reg [7:0] tpram_waddr, + output reg [15:0] tpram_write_data, + output reg tpram_write_en, + + // sprite metadata memory + output reg [6:0] smeta_waddr, + output reg [39:0] smeta_write_data, + output reg smeta_write_en, + output reg sprite_start, + input sprite_done, + + // LCD driver + output reg [7:0] lcd_data_in, + output reg lcd_data_dcx, // low: data, hi: cmd + output reg lcd_start, + output lcd_rst, + input lcd_done +); + +// FIXME: reorg states and commands +localparam CMD_LEDS = 0, + CMD_TEXP_LOAD = 1, + CMD_TEX_LOAD = 3, + CMD_CAST_FB = 4, + CMD_LCD = 5, + CMD_SPRITE_META = 6; + +reg [2:0] led_d, led_q; +reg [31:0] data_d, data_q; +reg drdy_d, drdy_q; + +assign leds = led_q; +assign s_data = data_q; +assign s_drdy = drdy_q; +assign lcd_rst = lcd_rst_q; +assign flush_busy = lcdstate_q != LCDIDLE; + +// FSM for SDRAM read/writes. +localparam IDLE = 0, + WAIT_DUMP = 4, + WAIT_LCD = 5, + WAIT_FOR_CAST = 6, + WAIT_FOR_LINE = 7, + CAST_FB = 8, + CAST_FB_START = 9; + +localparam LCDIDLE= 0, + LCD_FB_DUMP = 2, + LCD_FB_READRAM_RES = 3, + LCD_FB_SPLIT = 4, + LCD_FB_SPLIT_WAIT = 5, + LCD_FB_DUMP_START = 6; + +reg [4:0] state_d, state_q; +reg [4:0] lcdstate_d, lcdstate_q; + +// turn angle ROM. data shared between ray caster and sprite scaler (at least) +reg [6:0] angle_addr; +angle_rom angle_rom ( + .clk(clk), + .addr(angle_addr), + .angle(angle) // 4x Q8.8: dirX, dirY, planeX, planeY +); + +// ray caster positional data +reg [15:0] map_pos_x_d, map_pos_x_q; +reg [15:0] map_pos_y_d, map_pos_y_q; +reg [6:0] turn_addr_d, turn_addr_q; // angle lookup table index + +// caster +assign map_pos_x = map_pos_x_q; +assign map_pos_y = map_pos_y_q; +reg [8:0] lw_raddr_d, lw_raddr_q; // line writer +reg [8:0] lw_base_raddr_d, lw_base_raddr_q; // line RAM bank +assign line_ram_raddr = lw_raddr_q + lw_base_raddr_q; + +// screen casting. +localparam WIDTH = 320, + HEIGHT = 240; +reg [8:0] camera_x_d, camera_x_q; +reg dump_ready_d, dump_ready_q; +reg line_go_d, line_go_q; +reg lcd_go_d, lcd_go_q; +reg lcd_ready_d, lcd_ready_q; +reg lcd_done_d, lcd_done_q; // FIXME: weird. +// FIXME: come up with more clear logic for determining when rendering is +// complete. +// this workaround waits for the "done" condition to be held for a while. +reg [8:0] pipe_done_d, pipe_done_q; + +// lcd +reg lcd_rst_d, lcd_rst_q; +reg lcd_bcnt_d, lcd_bcnt_q; + +// frame render time tracker +reg [31:0] frame_cycle_d, frame_cycle_q; +reg [31:0] lframe_cycle_d, lframe_cycle_q; + +initial begin + lcd_rst_q = 1'b0; + camera_x_q = 9'd0; + turn_addr_q = 7'd0; + lframe_cycle_q = 0; +end + +// writing to SDRAM requires more states, but m_new_cmd/etc aren't held. +// - what happens if m_new_cmd comes high while we're in an FSM waiting for +// SDRAM? +// the read request shit queues but... do we lose serial transactions if we +// block too long? I think so. +// serial is slow enough that we might be fine for now. +// worst case we connect a couple RAM FIFO's, which I think we're intending on +// doing anyway. + +always @(*) begin + state_d = state_q; + lcdstate_d = lcdstate_q; + led_d = led_q; + data_d = data_q; + drdy_d = 0; + line_write_start = 1'b0; + lw_raddr_d = lw_raddr_q; + lw_base_raddr_d = lw_base_raddr_q; + dump_ready_d = dump_ready_q; + line_go_d = line_go_q; + lcd_go_d = lcd_go_q; + lcd_ready_d = lcd_ready_q; + lcd_done_d = lcd_done_q; + pipe_done_d = pipe_done_q; + frame_cycle_d = frame_cycle_q + 1'b1; + lframe_cycle_d = lframe_cycle_q; + // ray caster + camera_x_d = camera_x_q; + map_pos_x_d = map_pos_x_q; + map_pos_y_d = map_pos_y_q; + turn_addr_d = turn_addr_q; + cast_x = camera_x_q; + // ensure the angle is loaded + angle_addr = turn_addr_q; + cast_start = 1'b0; + // LCD regs + lcd_data_in = 8'd0; + lcd_data_dcx = 1'b0; + lcd_start = 1'b0; + lcd_rst_d = lcd_rst_q; + lcd_bcnt_d = lcd_bcnt_q; + // line texture memory. + tram_waddr = 13'd0; + tram_write_data = 8'd0; + tram_write_en = 1'b0; + tpram_waddr = 13'd0; + tpram_write_data = 8'd0; + tpram_write_en = 1'b0; + // sprite metadata memory. + smeta_waddr = 7'd0; + smeta_write_data = 39'd0; + smeta_write_en = 1'b0; + sprite_start = 1'b0; + + case (lcdstate_q) + LCDIDLE: begin + + end + LCD_FB_DUMP: begin + if (lw_raddr_q != 8'd240) begin + lcdstate_d = LCD_FB_READRAM_RES; + end else begin + lcd_done_d = 1'b1; + lcdstate_d = LCDIDLE; + // flip RAM line read bank. + if (lw_base_raddr_q == 9'd0) begin + lw_base_raddr_d = 9'd240; + end else begin + lw_base_raddr_d = 9'd0; + end + end + end + LCD_FB_READRAM_RES: begin + data_d[15:0] = line_ram_read_data; + lcd_bcnt_d = 1'b0; + lcdstate_d = LCD_FB_SPLIT; + end + LCD_FB_SPLIT: begin + // for each byte, send each half to SPI. + lcd_bcnt_d = ~lcd_bcnt_q; + if (!lcd_bcnt_q) begin + lcd_data_in = data_q[15:8]; + end else begin + lcd_data_in = data_q[7:0]; + end + + lcd_data_dcx = 1'b1; + lcd_start = 1'b1; + lcdstate_d = LCD_FB_SPLIT_WAIT; + end + LCD_FB_SPLIT_WAIT: begin + if (lcd_done) begin + if (!lcd_bcnt_q) begin // if we've flipped back to zero. + lw_raddr_d = lw_raddr_q + 1'b1; + lcdstate_d = LCD_FB_DUMP; + end else begin + lcdstate_d = LCD_FB_SPLIT; + end + end + end + default: lcdstate_d = LCDIDLE; + endcase + + case (state_q) + IDLE: begin + if (m_new_cmd) begin + led_d[0] = 1'b0; + case (m_cmd) + CMD_LEDS: begin + if (m_write) begin + led_d[2:0] = m_data[2:0]; + end else begin + data_d[7:0] = led_q; + drdy_d = 1'b1; + end + end + CMD_LCD: begin + // No read mode (until SD card interface?) + // FIXME: making an assumption about readiness :P + if (m_write) begin + state_d = WAIT_LCD; + lcd_data_in = m_data[7:0]; + lcd_data_dcx = m_data[8]; + lcd_start = 1'b1; + end else begin + // hack to allow RST toggling. + lcd_rst_d = m_address[0]; + drdy_d = 1'b1; + end + end + CMD_TEX_LOAD: begin + if (m_write) begin + tram_waddr = m_address[13:0]; + tram_write_data = m_data[3:0]; + tram_write_en = 1'b1; + end else begin + // no readback. + data_d = 32'd0; + drdy_d = 1'b1; + end + end + CMD_TEXP_LOAD: begin + if (m_write) begin + tpram_waddr = m_address[7:0]; + tpram_write_data = m_data[15:0]; + tpram_write_en = 1'b1; + end else begin + // no readback. + data_d = 32'd0; + drdy_d = 1'b1; + end + end + CMD_SPRITE_META: begin + if (m_write) begin + smeta_waddr = m_address[6:0]; + // texture ID is cuddled in the address. + smeta_write_data[39:32] = m_address[15:8]; + // x, y offsets in Q8.8 + smeta_write_data[31:0] = m_data; + smeta_write_en = 1'b1; + led_d[1] = 1'b1; + end else begin + // no readback. + data_d = 32'd0; + drdy_d = 1'b1; + end + end + CMD_CAST_FB: begin + if (m_write) begin + case (m_address) + 31'd0: begin + map_pos_x_d = m_data[31:16]; + map_pos_y_d = m_data[15:0]; + camera_x_d = 9'd0; + end + 31'd1: begin + turn_addr_d = m_data[6:0]; + state_d = CAST_FB_START; + lcd_data_dcx = 1'b0; + lcd_data_in = 8'h2C; // RAMWR + lcd_start = 1'b1; + // prep state + dump_ready_d = 1'b1; + lcd_ready_d = 1'b1; + line_go_d = 1'b0; + pipe_done_d = 10'd0; + // kick render chain + sprite_start = 1'b1; + frame_cycle_d = 32'd0; + end + endcase + end else begin + // return cycle count of previously rendered frame + data_d = lframe_cycle_q; + drdy_d = 1'b1; + end + end + endcase + end else begin + led_d[0] = 1'b1; + end + end + CAST_FB_START: begin + // wait for sprite transforms to complete. + if (sprite_done) begin + cast_start = 1'b1; + state_d = CAST_FB; + end + end + CAST_FB: begin + if (cast_done) begin + line_go_d = 1'b1; + camera_x_d = camera_x_q + 1'b1; + end + + if (line_go_q && dump_ready_q) begin + line_write_start = 1'b1; + line_go_d = 1'b0; + dump_ready_d = 1'b0; + // re-kick pipelined ray cast. + if (camera_x_q != WIDTH) begin + cast_start = 1'b1; + end + end + + if (line_write_done) begin + lcd_go_d = 1'b1; + end + + if (lcd_go_q && lcd_ready_q) begin + dump_ready_d = 1'b1; + lcd_go_d = 1'b0; + lcd_ready_d = 1'b0; + lw_raddr_d = 8'd0; + lcdstate_d = LCD_FB_DUMP; + end + + if (lcd_done_q) begin + lcd_ready_d = 1'b1; + lcd_done_d = 1'b0; + end + + // FIXME: race condition in this logic still, but I don't see it + // offhand. At lower frame rates it's easy to start another + // frame while the lcd writer is still going, which causes the + // frame to snap at an offset. + // at higher framerates + some delay here this doesn't seem to + // happen. + if (camera_x_q == WIDTH && !cast_busy && dump_ready_q && lcd_ready_q) begin + pipe_done_d = pipe_done_q + 1'b1; + if (&pipe_done_q) begin + lcd_data_dcx = 1'b0; + lcd_data_in = 8'h00; // NOP + lcd_start = 1'b1; + state_d = WAIT_LCD; + // hold timing of previous frame + lframe_cycle_d = frame_cycle_q; + end + end else begin + pipe_done_d = 10'd0; + end + end + WAIT_LCD: begin + if (lcd_done) begin + state_d = IDLE; + end + end + default: state_d = IDLE; + endcase +end + +always @(posedge clk) begin + if (rst) begin + led_q <= 0; + data_q <= 0; + drdy_q <= 0; + state_q = 0; + lcdstate_q = 0; + map_pos_x_q <= 0; + map_pos_y_q <= 0; + lw_raddr_q <= 0; + lw_base_raddr_q <= 0; + camera_x_q <= 0; + turn_addr_q <= 0; + lcd_bcnt_q <= 0; + end else begin + state_q = state_d; + lcdstate_q = lcdstate_d; + data_q <= data_d; + drdy_q <= drdy_d; + led_q <= led_d; + map_pos_x_q <= map_pos_x_d; + map_pos_y_q <= map_pos_y_d; + lw_raddr_q <= lw_raddr_d; + lw_base_raddr_q <= lw_base_raddr_d; + camera_x_q <= camera_x_d; + turn_addr_q <= turn_addr_d; + lcd_bcnt_q <= lcd_bcnt_d; + end + + lcd_rst_q <= lcd_rst_d; + dump_ready_q <= dump_ready_d; + line_go_q <= line_go_d; + lcd_done_q <= lcd_done_d; + lcd_go_q <= lcd_go_d; + lcd_ready_q <= lcd_ready_d; + pipe_done_q <= pipe_done_d; + frame_cycle_q <= frame_cycle_d; + lframe_cycle_q <= lframe_cycle_d; +end + +endmodule diff --git a/src/mmap_tb.v b/src/mmap_tb.v new file mode 100644 index 0000000..7a9d5b1 --- /dev/null +++ b/src/mmap_tb.v @@ -0,0 +1,117 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 00:29:36 10/21/2018 +// Design Name: +// Module Name: mmap_interface_tb +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module mmap_interface_tb( + ); + + reg clk; + reg rst; + + wire [7:0] tx_data; + wire new_tx_data; + reg tx_busy; + reg [7:0] rx_data; + reg new_rx_data; + +wire m_new_cmd; +wire m_write; +wire [5:0] m_cmd; +wire [31:0] m_address; +reg [31:0] s_data; +reg s_drdy; + + mmap_protocol DUT ( + .clk(clk), + .rst(rst), + .tx_data(tx_data), + .new_tx_data(new_tx_data), + .tx_busy(tx_busy), + .rx_data(rx_data), + .new_rx_data(new_rx_data), + .m_new_cmd(m_new_cmd), + .m_cmd(m_cmd), + .m_write(m_write), + .m_address(m_address), + .s_data(s_data), + .s_drdy(s_drdy) + ); + + // wait by delay for clocks rather than manually run them. + initial begin + clk = 0; + forever #10 clk = ~clk; + end + + initial begin + rst = 1'b1; + repeat(6) @(posedge clk); + rst = 1'b0; + repeat(2) @(posedge clk); + // command byte + new_rx_data = 1'b1; + rx_data = 8'b11000000; + @(posedge clk); + // "packet count" 16bit. + rx_data = 8'd0; + repeat(2) @(posedge clk); + // "address" bytes. hold open for four clocks. + rx_data = 8'b00000001; + repeat(4) @(posedge clk); + // "data" bytes. hold for another four clocks to load + rx_data = 8'b01111111; + repeat(4) @(posedge clk); + // command should be parsed by now. + new_rx_data = 1'b0; + rx_data = 8'd0; + repeat(8) @(posedge clk); + // NEXT: issue a read command + new_rx_data = 1'b1; + rx_data = 8'b00000001; + @(posedge clk); + // packet count 16bit + rx_data = 8'b00000000; + repeat(2) @(posedge clk); + // "address" bytes. four clocks to fill + rx_data = 8'b00010000; + repeat(4) @(posedge clk); + // m_new_cmd should be high + // m_write should be low. + // m_address should be full + new_rx_data = 1'b0; + @(posedge clk); + @(posedge clk); + //new_rx_data = 1'b1; + // reads request s_drdy and s_data to be set. + s_data = {16{2'b10}}; + s_drdy = 1'b1; + tx_busy = 1'b0; + @(posedge clk); + s_drdy = 1'b0; + // during next repetitions, tx_data, new_tx_data, etc should be flipped + repeat(25) @(posedge clk) + #5000 + $finish; + end + + initial begin + #500000000 + $finish; + end +endmodule diff --git a/src/mojo.ucf b/src/mojo.ucf new file mode 100644 index 0000000..8f93c6e --- /dev/null +++ b/src/mojo.ucf @@ -0,0 +1,38 @@ +#Created by Constraints Editor (xc6slx9-tqg144-3) - 2012/11/05 +NET "clk" TNM_NET = clk; +TIMESPEC TS_clk = PERIOD "clk" 50 MHz HIGH 50%; + +# PlanAhead Generated physical constraints +NET "clk" LOC = P56 | IOSTANDARD = LVTTL; +NET "rst_n" LOC = P38 | IOSTANDARD = LVTTL; + +NET "cclk" LOC = P70 | IOSTANDARD = LVTTL; + +NET "led<0>" LOC = P134 | IOSTANDARD = LVTTL; +NET "led<1>" LOC = P133 | IOSTANDARD = LVTTL; +NET "led<2>" LOC = P132 | IOSTANDARD = LVTTL; +NET "led<3>" LOC = P131 | IOSTANDARD = LVTTL; +NET "led<4>" LOC = P127 | IOSTANDARD = LVTTL; +NET "led<5>" LOC = P126 | IOSTANDARD = LVTTL; +NET "led<6>" LOC = P124 | IOSTANDARD = LVTTL; +NET "led<7>" LOC = P123 | IOSTANDARD = LVTTL; + +NET "spi_mosi" LOC = P44 | IOSTANDARD = LVTTL; +NET "spi_miso" LOC = P45 | IOSTANDARD = LVTTL; +NET "spi_ss" LOC = P48 | IOSTANDARD = LVTTL; +NET "spi_sck" LOC = P43 | IOSTANDARD = LVTTL; +NET "spi_channel<0>" LOC = P46 | IOSTANDARD = LVTTL; +NET "spi_channel<1>" LOC = P61 | IOSTANDARD = LVTTL; +NET "spi_channel<2>" LOC = P62 | IOSTANDARD = LVTTL; +NET "spi_channel<3>" LOC = P65 | IOSTANDARD = LVTTL; + +NET "avr_tx" LOC = P55 | IOSTANDARD = LVTTL; +NET "avr_rx" LOC = P59 | IOSTANDARD = LVTTL; +NET "avr_rx_busy" LOC = P39 | IOSTANDARD = LVTTL; + +NET "lcd_sck" LOC = P17 | IOSTANDARD = LVTTL; +NET "lcd_mosi" LOC = P16 | IOSTANDARD = LVTTL; +NET "lcd_ss" LOC = P15 | IOSTANDARD = LVTTL; +NET "lcd_dcx" LOC = P14 | IOSTANDARD = LVTTL; +NET "lcd_bl" LOC = P12 | IOSTANDARD = LVTTL; +NET "lcd_rst" LOC = P11 | IOSTANDARD = LVTTL; diff --git a/src/mojo_top.v b/src/mojo_top.v new file mode 100644 index 0000000..d3974dd --- /dev/null +++ b/src/mojo_top.v @@ -0,0 +1,305 @@ +module mojo_top( + // 50MHz clock input + input clk, + // Input from reset button (active low) + input rst_n, + // cclk input from AVR, high when AVR is ready + input cclk, + // Outputs to the 8 onboard LEDs + output[7:0]led, + // AVR SPI connections + output spi_miso, + input spi_ss, + input spi_mosi, + input spi_sck, + // AVR ADC channel select + output [3:0] spi_channel, + // Serial connections + input avr_tx, // AVR Tx => FPGA Rx + output avr_rx, // AVR Rx => FPGA Tx + input avr_rx_busy, // AVR Rx buffer full + // LCD SPI and control wires + output lcd_sck, + output lcd_mosi, + output lcd_ss, + output lcd_dcx, // hi: data, lo: cmd + output lcd_bl, // PWM'ed backlight + output lcd_rst // RST. LCD seems to hang sometimes. + ); + +wire rst = ~rst_n; // make reset active high +wire fclk, nclk; + +//assign led = 8'b0; + +// these signals should be high-z when not used +//assign spi_miso = 1'bz; +//assign avr_rx = 1'bz; +//assign spi_channel = 4'bzzzz; +wire [7:0] tx_data; +wire new_tx_data; +wire tx_busy; +wire [7:0] rx_data; +wire new_rx_data; + +// LCD wires +// TODO "LCD busy" wire for LED. +// LCD module wires +wire [7:0] lcd_data_in; +wire lcd_data_dcx; +wire lcd_start; +wire lcd_busy; +wire lcd_done; +// leave LCD backlight disconnected +assign lcd_bl = 1'bz; + +// mmap interface specifics +wire m_new_cmd; +wire m_write; +wire [5:0] m_cmd; +wire [31:0] m_address; +wire [31:0] m_data; +wire [31:0] s_data; +wire s_drdy; +wire flush_busy; + +wire [79:0] angle; + +// line writer wires +wire [39:0] line_height; +wire [6:0] line_tex_x; +wire [7:0] color; +wire [15:0] line_floor_x; +wire [15:0] line_floor_y; +wire [15:0] line_pos_x; +wire [15:0] line_pos_y; +wire line_write_ready, line_write_start, line_write_done; +wire [8:0] line_ram_raddr; +wire [15:0] line_ram_read_data; +wire [13:0] line_tram_waddr; +wire [3:0] line_tram_write_data; +wire line_tram_write_en; +wire [7:0] line_tpram_waddr; +wire [15:0] line_tpram_write_data; +wire line_tpram_write_en; + +// ray caster wires +wire cast_start; +wire cast_busy; +wire cast_done; +wire [8:0] cast_x; +wire [15:0] map_pos_x; +wire [15:0] map_pos_y; + +// sprite transform wires +wire sprite_start; +wire sprite_done; +wire [6:0] smeta_waddr; +wire [39:0] smeta_write_data; +wire smeta_write_en; +wire [6:0] stmeta_raddr; +wire [119:0] stmeta_read_data; + +// sprite scanline sorter +wire [15:0] wall_z; +wire [2:0] sprite_addr; +wire [119:0] sprite_meta; +wire sprscan_start; +wire sprscan_done; +wire [2:0] sprite_count; + +// LED indicators. +assign led[3] = sprite_count != 0; +assign led[4] = flush_busy; +assign led[5] = lcd_busy; +assign led[6] = ~line_write_ready; +assign led[7] = cast_busy; + +lcd_spi_clk lcd_spi_clk ( + .clk_in(clk), + .clk_fout(fclk), + .clk_nout(nclk) +); + +lcd_driver lcd_driver ( + .clk(nclk), + .fclk(fclk), + .rst(rst), + .lcd_sck(lcd_sck), + .lcd_mosi(lcd_mosi), + .lcd_ss(lcd_ss), + .lcd_dcx(lcd_dcx), + .data_in(lcd_data_in), + .data_dcx(lcd_data_dcx), + .start(lcd_start), + .busy(lcd_busy), + .done(lcd_done) +); + + avr_interface #(.CLK_RATE(50000000), .SERIAL_BAUD_RATE(500000)) avr_interface ( + .clk(nclk), + .rst(rst), + .cclk(cclk), + .spi_miso(spi_miso), + .spi_mosi(spi_mosi), + .spi_sck(spi_sck), + .spi_ss(spi_ss), + .spi_channel(spi_channel), + .tx(avr_rx), // FPGA tx goes to AVR rx + .rx(avr_tx), + .channel(4'd15), // invalid channel disables the ADC + .new_sample(), + .sample(), + .sample_channel(), + .tx_data(tx_data), + .new_tx_data(new_tx_data), + .tx_busy(tx_busy), + .tx_block(avr_rx_busy), + .rx_data(rx_data), + .new_rx_data(new_rx_data) + ); + +mmap_protocol mmap_protocol ( + .clk(nclk), + .rst(rst), + .tx_data(tx_data), + .new_tx_data(new_tx_data), + .tx_busy(tx_busy), + .rx_data(rx_data), + .new_rx_data(new_rx_data), + .m_new_cmd(m_new_cmd), + .m_cmd(m_cmd), + .m_write(m_write), + .m_address(m_address), + .m_data(m_data), + .s_data(s_data), + .s_drdy(s_drdy) + ); + +mmap_interface mmaped_interface ( + .clk(nclk), + .rst(rst), + .leds(led[2:0]), + .flush_busy(flush_busy), + // Protocol handler wires + .m_new_cmd(m_new_cmd), + .m_cmd(m_cmd), + .m_write(m_write), + .m_address(m_address), + .m_data(m_data), + .s_data(s_data), + .s_drdy(s_drdy), + .angle(angle), + // ray caster wires + .cast_x(cast_x), + .map_pos_x(map_pos_x), + .map_pos_y(map_pos_y), + .cast_start(cast_start), + .cast_busy(cast_busy), + .cast_done(cast_done), + // line writer wires + .line_height(line_height), + .line_write_ready(line_write_ready), + .line_write_start(line_write_start), + .line_write_done(line_write_done), + .line_ram_raddr(line_ram_raddr), + .line_ram_read_data(line_ram_read_data), + .tram_waddr(line_tram_waddr), + .tram_write_data(line_tram_write_data), + .tram_write_en(line_tram_write_en), + .tpram_waddr(line_tpram_waddr), + .tpram_write_data(line_tpram_write_data), + .tpram_write_en(line_tpram_write_en), + // sprite metadata wires + .smeta_waddr(smeta_waddr), + .smeta_write_data(smeta_write_data), + .smeta_write_en(smeta_write_en), + .sprite_start(sprite_start), + .sprite_done(sprite_done), + // LCD driver wires + .lcd_rst(lcd_rst), + .lcd_data_in(lcd_data_in), + .lcd_data_dcx(lcd_data_dcx), + .lcd_start(lcd_start), + .lcd_done(lcd_done) + ); + +line_writer line_writer ( + .clk(nclk), + .rst(rst), + .start(line_write_start), + .x(cast_x), + .pixel(color), + .height(line_height), + .tex_x(line_tex_x), + .floor_x(line_floor_x), + .floor_y(line_floor_y), + .pos_x(line_pos_x), + .pos_y(line_pos_y), + .rdy(line_write_ready), + .done(line_write_done), + .ram_raddr(line_ram_raddr), + .ram_read_data(line_ram_read_data), + .tram_waddr(line_tram_waddr), + .tram_write_data(line_tram_write_data), + .tram_write_en(line_tram_write_en), + .tpram_waddr(line_tpram_waddr), + .tpram_write_data(line_tpram_write_data), + .tpram_write_en(line_tpram_write_en), + .sprscan_start(sprscan_start), + .sprscan_done(sprscan_done), + .sprite_addr(sprite_addr), + .sprite_meta(sprite_meta), + .sprite_count(sprite_count) +); + +cast_ray cast_ray ( + .clk(nclk), + .rst(rst), + .x(cast_x), + .angle(angle), + .map_pos_x(map_pos_x), + .map_pos_y(map_pos_y), + .start(cast_start), + .busy(cast_busy), + .done(cast_done), + .line_height(line_height), + .line_tex_x(line_tex_x), + .line_color(color), + .line_floor_x(line_floor_x), + .line_floor_y(line_floor_y), + .line_pos_x(line_pos_x), + .line_pos_y(line_pos_y), + .wall_z(wall_z) +); + +sprite sprite ( + .clk(nclk), + .rst(rst), + .start(sprite_start), + .done(sprite_done), + .angle(angle), + .map_pos_x(map_pos_x), + .map_pos_y(map_pos_y), + .smeta_waddr(smeta_waddr), + .smeta_write_data(smeta_write_data), + .smeta_write_en(smeta_write_en), + .stmeta_raddr(stmeta_raddr), + .stmeta_read_data(stmeta_read_data) +); + +sprite_scanline sprite_scanline ( + .clk(nclk), + .rst(rst), + .start(sprscan_start), + .done(sprscan_done), + .x(cast_x), + .wall_z(wall_z), + .stmeta_raddr(stmeta_raddr), + .stmeta_read_data(stmeta_read_data), + .sprite_addr(sprite_addr), + .sprite_meta(sprite_meta), + .sprite_count(sprite_count) +); + +endmodule diff --git a/src/serial_rx.v b/src/serial_rx.v new file mode 100644 index 0000000..f0ffa45 --- /dev/null +++ b/src/serial_rx.v @@ -0,0 +1,95 @@ +// from embedded micro base project +module serial_rx #( + parameter CLK_PER_BIT = 50 + )( + input clk, + input rst, + input rx, + output [7:0] data, + output new_data + ); + + // clog2 is 'ceiling of log base 2' which gives you the number of bits needed to store a value + parameter CTR_SIZE = $clog2(CLK_PER_BIT); + + localparam STATE_SIZE = 2; + localparam IDLE = 2'd0, + WAIT_HALF = 2'd1, + WAIT_FULL = 2'd2, + WAIT_HIGH = 2'd3; + + reg [CTR_SIZE-1:0] ctr_d, ctr_q; + reg [2:0] bit_ctr_d, bit_ctr_q; + reg [7:0] data_d, data_q; + reg new_data_d, new_data_q; + reg [STATE_SIZE-1:0] state_d, state_q = IDLE; + reg rx_d, rx_q; + + assign new_data = new_data_q; + assign data = data_q; + + always @(*) begin + rx_d = rx; + state_d = state_q; + ctr_d = ctr_q; + bit_ctr_d = bit_ctr_q; + data_d = data_q; + new_data_d = 1'b0; + + case (state_q) + IDLE: begin + bit_ctr_d = 3'b0; + ctr_d = 1'b0; + if (rx_q == 1'b0) begin + state_d = WAIT_HALF; + end + end + WAIT_HALF: begin + ctr_d = ctr_q + 1'b1; + if (ctr_q == (CLK_PER_BIT >> 1)) begin + ctr_d = 1'b0; + state_d = WAIT_FULL; + end + end + WAIT_FULL: begin + ctr_d = ctr_q + 1'b1; + if (ctr_q == CLK_PER_BIT - 1) begin + data_d = {rx_q, data_q[7:1]}; + bit_ctr_d = bit_ctr_q + 1'b1; + ctr_d = 1'b0; + if (bit_ctr_q == 3'd7) begin + state_d = WAIT_HIGH; + new_data_d = 1'b1; + end + end + end + WAIT_HIGH: begin + if (rx_q == 1'b1) begin + state_d = IDLE; + end + end + default: begin + state_d = IDLE; + end + endcase + + end + + always @(posedge clk) begin + if (rst) begin + ctr_q <= 1'b0; + bit_ctr_q <= 3'b0; + new_data_q <= 1'b0; + state_q <= IDLE; + end else begin + ctr_q <= ctr_d; + bit_ctr_q <= bit_ctr_d; + new_data_q <= new_data_d; + state_q <= state_d; + end + + rx_q <= rx_d; + data_q <= data_d; + end + +endmodule diff --git a/src/serial_tx.v b/src/serial_tx.v new file mode 100644 index 0000000..5c37c4f --- /dev/null +++ b/src/serial_tx.v @@ -0,0 +1,110 @@ +// from embedded micro base project +module serial_tx #( + parameter CLK_PER_BIT = 50 + )( + input clk, + input rst, + output tx, + input block, + output busy, + input [7:0] data, + input new_data + ); + + // clog2 is 'ceiling of log base 2' which gives you the number of bits needed to store a value + parameter CTR_SIZE = $clog2(CLK_PER_BIT); + + localparam STATE_SIZE = 2; + localparam IDLE = 2'd0, + START_BIT = 2'd1, + DATA = 2'd2, + STOP_BIT = 2'd3; + + reg [CTR_SIZE-1:0] ctr_d, ctr_q; + reg [2:0] bit_ctr_d, bit_ctr_q; + reg [7:0] data_d, data_q; + reg [STATE_SIZE-1:0] state_d, state_q = IDLE; + reg tx_d, tx_q; + reg busy_d, busy_q; + reg block_d, block_q; + + assign tx = tx_q; + assign busy = busy_q; + + always @(*) begin + block_d = block; + ctr_d = ctr_q; + bit_ctr_d = bit_ctr_q; + data_d = data_q; + state_d = state_q; + busy_d = busy_q; + + case (state_q) + IDLE: begin + if (block_q) begin + busy_d = 1'b1; + tx_d = 1'b1; + end else begin + busy_d = 1'b0; + tx_d = 1'b1; + bit_ctr_d = 3'b0; + ctr_d = 1'b0; + if (new_data) begin + data_d = data; + state_d = START_BIT; + busy_d = 1'b1; + end + end + end + START_BIT: begin + busy_d = 1'b1; + ctr_d = ctr_q + 1'b1; + tx_d = 1'b0; + if (ctr_q == CLK_PER_BIT - 1) begin + ctr_d = 1'b0; + state_d = DATA; + end + end + DATA: begin + busy_d = 1'b1; + tx_d = data_q[bit_ctr_q]; + ctr_d = ctr_q + 1'b1; + if (ctr_q == CLK_PER_BIT - 1) begin + ctr_d = 1'b0; + bit_ctr_d = bit_ctr_q + 1'b1; + if (bit_ctr_q == 7) begin + state_d = STOP_BIT; + end + end + end + STOP_BIT: begin + busy_d = 1'b1; + tx_d = 1'b1; + ctr_d = ctr_q + 1'b1; + if (ctr_q == CLK_PER_BIT - 1) begin + state_d = IDLE; + end + end + default: begin + state_d = IDLE; + end + endcase + end + + always @(posedge clk) begin + if (rst) begin + state_q <= IDLE; + tx_q <= 1'b1; + end else begin + state_q <= state_d; + tx_q <= tx_d; + end + + block_q <= block_d; + data_q <= data_d; + bit_ctr_q <= bit_ctr_d; + ctr_q <= ctr_d; + busy_q <= busy_d; + end + +endmodule diff --git a/src/simple_dual_ram.v b/src/simple_dual_ram.v new file mode 100644 index 0000000..77dbd0c --- /dev/null +++ b/src/simple_dual_ram.v @@ -0,0 +1,76 @@ +/****************************************************************************** + + The MIT License (MIT) + + Copyright (c) 2015 Embedded Micro + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + THE SOFTWARE. + + ***************************************************************************** + + This module is a simple dual port RAM. This RAM is implemented in such a + way that Xilinx's tools will recognize it as a RAM and implement large + instances in block RAM instead of flip-flops. + + The parameter SIZE is used to specify the word size. That is the size of + each entry in the RAM. + + The parameter DEPTH is used to specify how many entries are in the RAM. + + read_data outputs the value of the entry pointed to by raddr in the previous + clock cycle. That means to read address 10, you would set address to be 10 + and wait one cycle for its value to show up. The RAM is always reading whatever + address is. If you don't need to read, just ignore this value. + + To write, set write_en to 1, write_data to the value to write, and waddr to + the address you want to write. + + You should avoid reading and writing to the same address simultaneously. +*/ + +module simple_dual_ram #( + parameter SIZE = 32, // size of each entry + parameter DEPTH = 320 // number of entries + )( + // write interface + input wclk, // write clock + input [$clog2(DEPTH)-1:0] waddr, // write address + input [SIZE-1:0] write_data, // write data + input write_en, // write enable (1 = write) + + // read interface + input rclk, // read clock + input [$clog2(DEPTH)-1:0] raddr, // read address + output reg [SIZE-1:0] read_data // read data + ); + + reg [SIZE-1:0] mem [DEPTH-1:0]; // memory array + + // write clock domain + always @(posedge wclk) begin + if (write_en) // if write enable + mem[waddr] <= write_data; // write memory + end + + // read clock domain + always @(posedge rclk) begin + read_data <= mem[raddr]; // read memory + end + +endmodule diff --git a/src/spi.v b/src/spi.v new file mode 100644 index 0000000..d1d15ea --- /dev/null +++ b/src/spi.v @@ -0,0 +1,105 @@ +// (modified) from mojo example source code. +// (same MIT license) + +module spi #(parameter CLK_DIV = 2)( + input clk, + input rst, + input miso, + output mosi, + output sck, + input start, + output reg ss, // lcd_ss + input[7:0] data_in, + output[7:0] data_out, + output busy, + output new_data +); + +localparam STATE_SIZE = 2; +localparam IDLE = 2'd0, + WAIT_HALF = 2'd1, + TRANSFER = 2'd2; + +reg [STATE_SIZE-1:0] state_d, state_q; + +reg [7:0] data_d, data_q; +reg [CLK_DIV-1:0] sck_d, sck_q; +reg mosi_d, mosi_q; +reg [2:0] ctr_d, ctr_q; +reg new_data_d, new_data_q; +reg [7:0] data_out_d, data_out_q; + +assign mosi = mosi_q; +// CPHA = 1 +//assign sck = (~sck_q[CLK_DIV-1]) & (state_q == TRANSFER); +assign sck = (sck_q[CLK_DIV-1]) & (state_q == TRANSFER); // CPHA = 0 +assign busy = state_q != IDLE; +assign data_out = data_out_q; +assign new_data = new_data_q; + +always @(*) begin + sck_d = sck_q; + data_d = data_q; + mosi_d = mosi_q; + ctr_d = ctr_q; + new_data_d = 1'b0; + data_out_d = data_out_q; + state_d = state_q; + ss = 1'b1; // ss high when idle. + + case (state_q) + IDLE: begin + sck_d = 4'b0; + ctr_d = 3'b0; + if (start == 1'b1) begin + data_d = data_in; + state_d = WAIT_HALF; + end + end + WAIT_HALF: begin + sck_d = sck_q + 1'b1; + if (sck_q == {CLK_DIV-1{1'b1}}) begin + sck_d = 1'b0; + state_d = TRANSFER; + end + end + TRANSFER: begin + sck_d = sck_q + 1'b1; + ss = 1'b0; // low when active. + if (sck_q == 4'b0000) begin + mosi_d = data_q[7]; + end else if (sck_q == {CLK_DIV-1{1'b1}}) begin + data_d = {data_q[6:0], miso}; + end else if (sck_q == {CLK_DIV{1'b1}}) begin + ctr_d = ctr_q + 1'b1; + if (ctr_q == 3'b111) begin + state_d = IDLE; + data_out_d = data_q; + new_data_d = 1'b1; + end + end + end + endcase +end + +always @(posedge clk) begin + if (rst) begin + ctr_q <= 3'b0; + data_q <= 8'b0; + sck_q <= 4'b0; + mosi_q <= 1'b0; + state_q <= IDLE; + data_out_q <= 8'b0; + new_data_q <= 1'b0; + end else begin + ctr_q <= ctr_d; + data_q <= data_d; + sck_q <= sck_d; + mosi_q <= mosi_d; + state_q <= state_d; + data_out_q <= data_out_d; + new_data_q <= new_data_d; + end +end + +endmodule diff --git a/src/spi_slave.v b/src/spi_slave.v new file mode 100644 index 0000000..3cba2c9 --- /dev/null +++ b/src/spi_slave.v @@ -0,0 +1,79 @@ +module spi_slave( + input clk, + input rst, + input ss, + input mosi, + output miso, + input sck, + output done, + input [7:0] din, + output [7:0] dout + ); + +reg mosi_d, mosi_q; +reg ss_d, ss_q; +reg sck_d, sck_q; +reg sck_old_d, sck_old_q; +reg [7:0] data_d, data_q; +reg done_d, done_q; +reg [2:0] bit_ct_d, bit_ct_q; +reg [7:0] dout_d, dout_q; +reg miso_d, miso_q; + +assign miso = miso_q; +assign done = done_q; +assign dout = dout_q; + +always @(*) begin + ss_d = ss; + mosi_d = mosi; + miso_d = miso_q; + sck_d = sck; + sck_old_d = sck_q; + data_d = data_q; + done_d = 1'b0; + bit_ct_d = bit_ct_q; + dout_d = dout_q; + + if (ss_q) begin + bit_ct_d = 3'b0; + data_d = din; + miso_d = data_q[7]; + end else begin + if (!sck_old_q && sck_q) begin // rising edge + data_d = {data_q[6:0], mosi_q}; + bit_ct_d = bit_ct_q + 1'b1; + if (bit_ct_q == 3'b111) begin + dout_d = {data_q[6:0], mosi_q}; + done_d = 1'b1; + data_d = din; + end + end else if (sck_old_q && !sck_q) begin // falling edge + miso_d = data_q[7]; + end + end +end + +always @(posedge clk) begin + if (rst) begin + done_q <= 1'b0; + bit_ct_q <= 3'b0; + dout_q <= 8'b0; + miso_q <= 1'b1; + end else begin + done_q <= done_d; + bit_ct_q <= bit_ct_d; + dout_q <= dout_d; + miso_q <= miso_d; + end + + sck_q <= sck_d; + mosi_q <= mosi_d; + ss_q <= ss_d; + data_q <= data_d; + sck_old_q <= sck_old_d; + +end + + +endmodule diff --git a/src/sprite.v b/src/sprite.v new file mode 100644 index 0000000..0425903 --- /dev/null +++ b/src/sprite.v @@ -0,0 +1,385 @@ +// sprite transformation pre-pass module. +// at the start of a frame, walks each sprite meta and writes out data +// transformed to the camera view. +// not exactly optimized; walks *all* sprites vs ones just available in frame. +// a much better algo would be to organize sprites into linked list buckets +// per map square. Then take a log of visited tiles during the ray cast and +// use that to index into squares. +// +// however, linked lists in raw verilog are time consuming for me to write, so +// I will do that as an optimization pass later (perhaps for a different +// engine). + +// This module operates in Q16.16, though most lookup tables are some form of +// 16bit (Q8.8, Q4.12, etc). Otherwise a lot of the math doesn't work out. +module sprite ( + input clk, + input rst, + + input start, + output reg done, + // turn data + input [79:0] angle, + input [15:0] map_pos_x, + input [15:0] map_pos_y, + + // mmap_interface writes sprite metadata + input [6:0] smeta_waddr, + input [39:0] smeta_write_data, + input smeta_write_en, + // sprite scanline culler reads transformed data. + input [6:0] stmeta_raddr, + output [119:0] stmeta_read_data +); + +localparam HEIGHT = 240, + WIDTH = 320, + HALF_HEIGHT = 120, + HALF_WIDTH = 160, + SPRITE_COUNT = 128; + +// RAM module for x/y/tex meta +reg [6:0] smeta_raddr; +wire [39:0] smeta_read_data; + +// 8bit sprite texture, x, y 16bit +simple_dual_ram #(.SIZE(40), .DEPTH(SPRITE_COUNT)) smeta_ram ( + .wclk(clk), + .waddr(smeta_waddr), + .write_data(smeta_write_data), + .write_en(smeta_write_en), + // read + .rclk(clk), + .raddr(smeta_raddr), + .read_data(smeta_read_data) +); + +// RAM module for transformed meta +reg [6:0] stmeta_waddr; +reg [119:0] stmeta_write_data; +reg stmeta_write_en; +// read wires? + +simple_dual_ram #(.SIZE(120), .DEPTH(SPRITE_COUNT)) stmeta_ram ( + .wclk(clk), + .waddr(stmeta_waddr), + .write_data(stmeta_write_data), + .write_en(stmeta_write_en), + // read + .rclk(clk), + .raddr(stmeta_raddr), + .read_data(stmeta_read_data) +); + +// inverse distance rom (for transformY) +reg [9:0] idist_addr; +wire [15:0] idist; +idist_rom idist_rom ( + .clk(clk), + .addr(idist_addr), + .idist(idist) +); + +reg [4:0] state_d, state_q; +reg [4:0] next_state_d, next_state_q; +localparam IDLE = 0, + MULTIPLY = 1, + TRANSFORM_START = 2, + TRANSFORMX_1 = 3, + TRANSFORMX_2 = 4, + TRANSFORMX_3 = 5, + TRANSFORMX_4 = 6, + TRANSFORMY_1 = 7, + TRANSFORMY_2 = 8, + TRANSFORMY_3 = 9, + SPRITE_SCREENX = 10, + SPRITE_SCREENX_2 = 11, + SPRITE_SCREENX_3 = 12, + SPRITE_HEIGHT = 13, + SPRITE_DRAWBOUNDS = 14, + SAVE_TRANSFORMS = 15; + +// shared multiplier +reg signed [31:0] mul_res_d, mul_res_q; +reg signed [31:0] mul_arg1_d, mul_arg1_q; +reg signed [31:0] mul_arg2_d, mul_arg2_q; +reg signed [31:0] math_hold_d, math_hold_q; + +// turn angle data +reg signed [31:0] dirx_d, dirx_q; +reg signed [31:0] diry_d, diry_q; +reg signed [31:0] planex_d, planex_q; +reg signed [31:0] planey_d, planey_q; +reg signed [31:0] invdet_d, invdet_q; + +reg signed [31:0] map_posx_d, map_posx_q; +reg signed [31:0] map_posy_d, map_posy_q; + +// registers for temp sprite transform meta +reg signed [31:0] spritex_d, spritex_q; +reg signed [31:0] spritey_d, spritey_q; +reg signed [31:0] transformx_d, transformx_q; +reg signed [31:0] transformy_d, transformy_q; +reg signed [15:0] sprite_screenx_d, sprite_screenx_q; +reg signed [15:0] sprite_height_d, sprite_height_q; +reg signed [15:0] draw_starty_d, draw_starty_q; +reg signed [15:0] draw_endy_d, draw_endy_q; +reg signed [15:0] draw_startx_d, draw_startx_q; +reg signed [15:0] draw_endx_d, draw_endx_q; + +reg [6:0] count_d, count_q; + +always @(*) begin + state_d = state_q; + next_state_d = next_state_q; + count_d = count_q; + smeta_raddr = count_q; + stmeta_waddr = count_q; + stmeta_write_data = 120'd0; + stmeta_write_en = 1'b0; + idist_addr = 0; + done = 1'b0; + // multiplier + mul_res_d = mul_res_q; + mul_arg1_d = mul_arg1_q; + mul_arg2_d = mul_arg2_q; + math_hold_d = math_hold_q; + next_state_d = next_state_q; + // angle data + dirx_d = dirx_q; + diry_d = diry_q; + planex_d = planex_q; + planey_d = planey_q; + invdet_d = invdet_q; + map_posx_d = map_posx_q; + map_posy_d = map_posy_q; + // temp sprite metadata. + spritex_d = spritex_q; + spritey_d = spritey_q; + transformx_d = transformx_q; + transformy_d = transformy_q; + sprite_screenx_d = sprite_screenx_q; + sprite_height_d = sprite_height_q; + draw_starty_d = draw_starty_q; + draw_endy_d = draw_endy_q; + draw_startx_d = draw_startx_q; + draw_endx_d = draw_endx_q; + + case (state_q) + IDLE: begin + if (start) begin + // hold angle data. convert Q8.8 -> Q16.16 + // FIXME: fucking up the sign extension! + // dirx_d is becoming a huge number instead of -1 + dirx_d[31:16] = angle[79:64]; + dirx_d[15:0] = 0; + diry_d[31:16] = angle[63:48]; + diry_d[15:0] = 0; + planex_d[31:16] = angle[47:32]; + planex_d[15:0] = 0; + planey_d[31:16] = angle[31:16]; + planey_d[15:0] = 0; + invdet_d[31:16] = angle[15:0]; + invdet_d[15:0] = 0; + + map_posx_d = map_pos_x <<< 8; + map_posy_d = map_pos_y <<< 8; + count_d = 0; + + state_d = TRANSFORM_START; + end + // ensure smeta_ram is ready with the first value on start + smeta_raddr = 0; + end + MULTIPLY: begin + mul_res_d = trunc_fixed_mul(mul_arg1_q * mul_arg2_q); + state_d = next_state_q; + end + // for each sprite, find its X/Y positions, as well as + // height/width. + TRANSFORM_START: begin + // Finish transforming signed Q8.8's to Q16.16 + dirx_d = dirx_q >>> 8; + diry_d = diry_q >>> 8; + planex_d = planex_q >>> 8; + planey_d = planey_q >>> 8; + invdet_d = invdet_q >>> 8; + + // sprite position relative to camera. + spritex_d = (smeta_read_data[31:16] << 8) - map_posx_q; + spritey_d = (smeta_read_data[15:0] << 8) - map_posy_q; + // rest of smeta is the sprite texture id. we'll simply write + // directly from smeta_read_data when done with the transform. + // also, could seed the multiplier here, but lets keep the code + // more clear. + state_d = TRANSFORMX_1; + end + TRANSFORMX_1: begin + // transformX = invDet * (dirY * spriteX - dirX * spriteY); + // need to set up several multiplications, bouncing through shared + // logic. + mul_arg1_d = diry_q; + mul_arg2_d = spritex_q; + next_state_d = TRANSFORMX_2; + state_d = MULTIPLY; + end + TRANSFORMX_2: begin + // effectively registers :) + math_hold_d = mul_res_q; + mul_arg1_d = dirx_q; + mul_arg2_d = spritey_q; + next_state_d = TRANSFORMX_3; + state_d = MULTIPLY; + end + TRANSFORMX_3: begin + // this is pretty much "bizarro assembler". + // final multiplication for tX is invdet * (stuff so far) + mul_arg1_d = invdet_q; + mul_arg2_d = math_hold_q - mul_res_q; + next_state_d = TRANSFORMX_4; + state_d = MULTIPLY; + end + TRANSFORMX_4: begin + // I did create a tiny cpu core, assembler, etc which I'd intended + // to use here to avoid exploding logic and reuse a multiplier. + transformx_d = mul_res_q; + // now again for tY! + mul_arg1_d = ((~planey_q) + 1'b1); // negate + mul_arg2_d = spritex_q; + next_state_d = TRANSFORMY_1; + state_d = MULTIPLY; + end + TRANSFORMY_1: begin + // The core used a lot of LUT's, even after aggressive area + // optimization. Compared to simply sharing the multiplier, the + // logic here wasn't long enough to justify using it. + math_hold_d = mul_res_q; + mul_arg1_d = planex_q; + mul_arg2_d = spritey_q; + next_state_d = TRANSFORMY_2; + state_d = MULTIPLY; + end + TRANSFORMY_2: begin + // It's also (surprisingly) a lot more clear to read what this is + // doing vs jumping around with an amateur assembly file. + // If it gets too complex, there are enough resources to use a few + // more multipliers an simplify it again. + mul_arg1_d = invdet_q; + mul_arg2_d = math_hold_q + mul_res_q; + next_state_d = TRANSFORMY_3; + state_d = MULTIPLY; + end + TRANSFORMY_3: begin + // using two multipliers would cut these states in half, for + // example. since this isn't too long and I'd like to port this + // engine to smaller FPGA's, we'll try to stick with this. + transformy_d = mul_res_q; + // next up: spriteScreenX = int((w / 2) * (1 + transformX / transformY)) + // to avoid the division, we have a Q4.12 inversion of transformY. + // taken from a Q5.5 out of transformY. + idist_addr = mul_res_q[21:10]; + state_d = SPRITE_SCREENX; + end + SPRITE_SCREENX: begin + mul_arg1_d = transformx_q; + mul_arg2_d = idist << 8; // lookup table stored Q8.8 + next_state_d = SPRITE_SCREENX_2; + state_d = MULTIPLY; + end + SPRITE_SCREENX_2: begin + mul_arg1_d = HALF_WIDTH << 16; + // Add a Q16.16 1.0 to the previous result. + mul_arg2_d = 31'h0001_0000 + mul_res_q; + next_state_d = SPRITE_SCREENX_3; + state_d = MULTIPLY; + // we need the inverse distance again to find sprite height. + math_hold_d = mul_arg2_q; + end + SPRITE_SCREENX_3: begin + sprite_screenx_d = mul_res_q >>> 16; + // next up is sprite height: + // spriteHeight = abs(int(h / (transformY))) + mul_arg1_d = HEIGHT << 16; + mul_arg2_d = math_hold_q; + next_state_d = SPRITE_HEIGHT; + state_d = MULTIPLY; + end + SPRITE_HEIGHT: begin + // invert if negative. + // convert back to normal 16bit signed integer. + if (mul_res_q[31]) begin + sprite_height_d = (~mul_res_q) + 1'b1 >> 16; + end else begin + sprite_height_d = mul_res_q >> 16; + end + // width and height are identical; stick to one register. + state_d = SPRITE_DRAWBOUNDS; + end + SPRITE_DRAWBOUNDS: begin + // find the bounds, but we don't actually want to use them + // out of screen range (< 0 or > WIDTH) + draw_starty_d = (~(sprite_height_q >> 1)) + 1'b1 + HALF_HEIGHT; + draw_endy_d = (sprite_height_q >> 1) + HALF_HEIGHT; + draw_startx_d = (~(sprite_height_q >> 1)) + 1'b1 + sprite_screenx_q; + draw_endx_d = (sprite_height_q >> 1) + sprite_screenx_q; + state_d = SAVE_TRANSFORMS; + end + SAVE_TRANSFORMS: begin + // could have done this in the previous cycle, but less clear. + stmeta_write_data = {smeta_read_data[39:32], transformy_q[23:8], sprite_screenx_q, sprite_height_q, draw_starty_q, draw_endy_q, draw_startx_q, draw_endx_q}; + stmeta_write_en = 1'b1; + count_d = count_q + 1'b1; + if (count_q == SPRITE_COUNT-1) begin + done = 1'b1; + state_d = IDLE; + end else begin + // FIXME: REVERT AFTER TESTING! + state_d = TRANSFORM_START; + //state_d = IDLE; + end + end + endcase +end + +always @(posedge clk) begin + if (rst) begin + state_q <= IDLE; + end else begin + state_q <= state_d; + end + + count_q <= count_d; + // multiplier + mul_res_q <= mul_res_d; + mul_arg1_q <= mul_arg1_d; + mul_arg2_q <= mul_arg2_d; + math_hold_q <= math_hold_d; + next_state_q <= next_state_d; + // angle data + dirx_q <= dirx_d; + diry_q <= diry_d; + planex_q <= planex_d; + planey_q <= planey_d; + invdet_q <= invdet_d; + map_posx_q <= map_posx_d; + map_posy_q <= map_posy_d; + // temp sprite metadata. + spritex_q <= spritex_d; + spritey_q <= spritey_d; + transformx_q <= transformx_d; + transformy_q <= transformy_d; + sprite_screenx_q <= sprite_screenx_d; + sprite_height_q <= sprite_height_d; + draw_starty_q <= draw_starty_d; + draw_endy_q <= draw_endy_d; + draw_startx_q <= draw_startx_d; + draw_endx_q <= draw_endx_d; +end + +// see cast_ray.v +// multiplies out to 64bit, then returns Q16.16 middle. +function signed [31:0] trunc_fixed_mul(input signed [63:0] mulres); + trunc_fixed_mul = mulres[47:16]; +endfunction + +endmodule diff --git a/src/sprite_scanline.v b/src/sprite_scanline.v new file mode 100644 index 0000000..b5e91d6 --- /dev/null +++ b/src/sprite_scanline.v @@ -0,0 +1,123 @@ +// module for culling and sorting sprites to be displayed on a particular +// scanline. + +// This uses the pre-transformed sprite data to determine if a sprite scanline +// exists on the current line or not. +// It caches data for up to N sprites, which is then read by the line writer +// during the display routine. +// This module gets kicked off while the walls are being drawn. + +// Note how this isn't generally optimized: this has to scan every possible +// sprite once per scanline, then sort, which is only consistently faster than +// the wall draw if there're < 128 sprites in a level. +// +// However, this is fine for this implementation since each sprite cull test +// can be done within a single cycle! +// A better one, and more closely matching the wolf3D engine, would have the +// sprite pre-transform sort sprites into map squares. The raycaster then logs +// which tiles it sees for each ray, which is used to more quickly cull +// sprites. It can also be used to improve ordering since map tiles can be +// examined from near-to-far, so you only have to sort sprites within +// a particular tile. + +module sprite_scanline ( + input clk, + input rst, + + input start, + output reg done, + + input [8:0] x, // camera X position + input [15:0] wall_z, // z buffer of casted wall + + // transformed sprite metadata + output reg [6:0] stmeta_raddr, + input [119:0] stmeta_read_data, + + // hook sorted registers into line writer + input [2:0] sprite_addr, + output reg [119:0] sprite_meta, + output reg [2:0] sprite_count +); + +localparam WIDTH = 320; + +localparam IDLE = 0, + CULL_FETCH = 1, + CULL = 2; +reg [3:0] state_d, state_q; + +reg [6:0] count_d, count_q; +reg [2:0] scount_d, scount_q; +// add an extra bit so we can do signed comparisons. +reg signed [15:0] camera_x_d, camera_x_q; + +// FIXME: use pointers instead and serve from stmeta_raddr. +reg [119:0] sprites [2:0]; + +reg save_meta; + +always @(*) begin + state_d = state_q; + count_d = count_q; + stmeta_raddr = count_q; + camera_x_d = camera_x_q; + save_meta = 1'b0; + sprite_count = scount_q; + scount_d = scount_q; + done = 1'b0; + + case (state_q) + IDLE: begin + count_d = 0; + if (start) begin + state_d = CULL_FETCH; + camera_x_d = x - 1'b1; + scount_d = 3'd0; + end + end + CULL_FETCH: begin + // load the metadata from RAM + // can remove this step once tested/understood better. + state_d = CULL; + end + CULL: begin + // First test is the wall Z depth cull. + // Then, if camera X is within sprite X draw boundaries + if ($signed(stmeta_read_data[111:96]) < wall_z + && $signed(stmeta_read_data[111:96]) > 0 + && $signed(stmeta_read_data[31:16]) <= camera_x_q + && $signed(stmeta_read_data[15:0]) >= camera_x_q + ) begin + // save the sprite info if it's visible + save_meta = 1'b1; + scount_d = scount_q + 1'b1; + end + count_d = count_q + 1'b1; + if (count_q == 127 || scount_d == 8) begin + done = 1'b1; + state_d = IDLE; + end else begin + state_d = CULL_FETCH; + end + end + endcase +end + +always @(posedge clk) begin + if (rst) begin + state_q <= IDLE; + end else begin + state_q <= state_d; + end + + count_q <= count_d; + camera_x_q <= camera_x_d; + scount_q <= scount_d; + if (save_meta) begin + sprites[count_q] <= stmeta_read_data; + end + sprite_meta <= sprites[sprite_addr]; +end + +endmodule diff --git a/src/sprite_tb.v b/src/sprite_tb.v new file mode 100644 index 0000000..f5dd6d4 --- /dev/null +++ b/src/sprite_tb.v @@ -0,0 +1,77 @@ +`timescale 1ns / 1ps + +module sprite_tb( + ); + +reg clk; +reg rst; + +reg start; +wire done; +//reg [79:0] angle; +reg [15:0] map_pos_x; +reg [15:0] map_pos_y; + +reg [6:0] smeta_waddr; +reg [39:0] smeta_write_data; +reg smeta_write_en; +reg [6:0] stmeta_raddr; +wire [119:0] stmeta_read_data; + +reg [6:0] angle_addr; +wire [79:0] angle; +angle_rom angle_rom ( + .clk(clk), + .addr(angle_addr), + .angle(angle) // 4x Q8.8: dirX, dirY, planeX, planeY +); + +sprite DUT ( + .clk(clk), + .rst(rst), + .start(start), + .done(done), + .angle(angle), + .map_pos_x(map_pos_x), + .map_pos_y(map_pos_y), + .smeta_waddr(smeta_waddr), + .smeta_write_data(smeta_write_data), + .smeta_write_en(smeta_write_en), + .stmeta_raddr(stmeta_raddr), + .stmeta_read_data(stmeta_read_data) +); + + initial begin + clk = 0; + forever #10 clk = ~clk; + end + + initial begin + rst = 1'b1; + repeat(6) @(posedge clk); + rst = 1'b0; + repeat(2) @(posedge clk); + smeta_waddr = 0; + // texture 1, map pos h12, h12. + smeta_write_data = 40'h01_1200_1200; + smeta_write_en = 1'b1; + angle_addr = 0; + repeat(1) @(posedge clk); + smeta_write_en = 1'b0; + //angle = 80'hff_00_00_00_00_00_00_a8_02_f0; + //angle = 80'hff_00_00_00_00_00_00_a8_01_83; + map_pos_x = 16'h13_00; + map_pos_y = 16'h13_00; + start = 1'b1; + repeat(1) @(posedge clk); + start = 1'b0; + repeat(400) @(posedge clk); + #5000 + $finish; + end + + initial begin + #500000000 + $finish; + end +endmodule diff --git a/src/task_crossdomain.v b/src/task_crossdomain.v new file mode 100644 index 0000000..6f61df5 --- /dev/null +++ b/src/task_crossdomain.v @@ -0,0 +1,31 @@ +// taken from: https://www.fpga4fun.com/CrossClockDomain3.html +// copyrighted fpga4fun.com & KNJN LLC. + +module task_crossdomain( + input clka, + input taskstart_clka, + output taskbusy_clka, taskdone_clka, + + input clkb, + output taskstart_clkb, taskbusy_clkb, + input taskdone_clkb +); + +reg FlagToggle_clkA = 0; +reg FlagToggle_clkB = 0; +reg Busyhold_clkB = 0; +reg [2:0] SyncA_clkB = 0; +reg [2:0] SyncB_clkA = 0; + +always @(posedge clka) FlagToggle_clkA <= FlagToggle_clkA ^ (taskstart_clka & ~taskbusy_clka); + +always @(posedge clkb) SyncA_clkB <= {SyncA_clkB[1:0], FlagToggle_clkA}; +assign taskstart_clkb = (SyncA_clkB[2] ^ SyncA_clkB[1]); +assign taskbusy_clkb = taskstart_clkb | Busyhold_clkB; +always @(posedge clkb) Busyhold_clkB <= ~taskdone_clkb & taskbusy_clkb; +always @(posedge clkb) if(taskbusy_clkb & taskdone_clkb) FlagToggle_clkB <= FlagToggle_clkA; + +always @(posedge clka) SyncB_clkA <= {SyncB_clkA[1:0], FlagToggle_clkB}; +assign taskbusy_clka = FlagToggle_clkA ^ SyncB_clkA[2]; +assign taskdone_clka = SyncB_clkA[2] ^ SyncB_clkA[1]; +endmodule diff --git a/syn/.gitignore b/syn/.gitignore new file mode 100644 index 0000000..86d0cb2 --- /dev/null +++ b/syn/.gitignore @@ -0,0 +1,4 @@ +# Ignore everything in this directory +* +# Except this file +!.gitignore \ No newline at end of file diff --git a/texture/LAB/door/door0.png b/texture/LAB/door/door0.png new file mode 100644 index 0000000000000000000000000000000000000000..ab6be01a76f236d873c83daeb25661e2e204949e GIT binary patch literal 712 zcmV;(0yq7MP)00006bW%=J0RI30 z0RM@=FOUEL0)0tDK~#90?OHKw+%Ob=E*iQ7yj(FH0aLuiL*ZyWWNFBCO2)#q(4jxz zAl)v|j2SXyNVh_VKq=H2yP4Eo1KDo44h5wMOsa7YJlObp@}_F<2Acrj9PQKF3~q+$oRLXi8|?6Aa?gK+ z0O00007SNklz+U2M5k% zId1(=15TE92X_(SvWkGs%rt}O2WKnT&c?d$6Sqt=Msxo0J?_x@ut{8r+; zzx6D%`EotBA=wMr6Sn6?fiZ-9CPoqiDk*K0_}p~ZL&$AoF1u007(!^n9S^e$Vx7es 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+CHANGE LOG for LogiCORE Clocking Wizard V3.6 
+
+                    Release Date: June 19, 2013
+--------------------------------------------------------------------------------
+
+Table of Contents
+
+1. INTRODUCTION 
+2. DEVICE SUPPORT    
+3. NEW FEATURE HISTORY   
+4. RESOLVED ISSUES 
+5. KNOWN ISSUES & LIMITATIONS 
+6. TECHNICAL SUPPORT & FEEDBACK
+7. CORE RELEASE HISTORY 
+8. LEGAL DISCLAIMER 
+
+--------------------------------------------------------------------------------
+
+
+1. INTRODUCTION
+
+For installation instructions for this release, please go to:
+
+  www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
+
+For system requirements:
+
+   www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
+
+This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.6
+solution. For the latest core updates, see the product page at:
+
+   www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/
+
+................................................................................
+
+2. DEVICE SUPPORT
+
+
+  2.1 ISE 
+   
+  
+  The following device families are supported by the core for this release.
+  
+  All 7 Series devices
+
+
+  Zynq-7000 devices
+    Zynq-7000
+    Defense Grade Zynq-7000Q (XQ)
+
+
+  All Virtex-6 devices
+  
+  
+  All Spartan-6 devices
+  
+  
+................................................................................
+
+3. NEW FEATURE HISTORY 
+
+
+  3.1 ISE 
+  
+    - Spread Spectrum support for 7 series MMCME2
+
+    - ISE 14.2 software support
+
+................................................................................
+
+4. RESOLVED ISSUES
+
+
+  4.1 ISE 
+  
+      Resolved issue with example design becoming core top in planAhead
+
+      Resolved issue with Virtex6 MMCM instantiation for VHDL project
+      Please refer to AR 50719 - www.xilinx.com/support/answers/50719.htm
+
+................................................................................
+
+5. KNOWN ISSUES & LIMITATIONS
+
+
+  5.1 ISE 
+  
+  
+  The most recent information, including known issues, workarounds, and
+  resolutions for this version is provided in the IP Release Notes Guide
+  located at
+
+   www.xilinx.com/support/documentation/user_guides/xtp025.pdf
+  
+  
+................................................................................
+
+6. TECHNICAL SUPPORT & FEEDBACK
+
+
+To obtain technical support, create a WebCase at www.xilinx.com/support.
+Questions are routed to a team with expertise using this product.
+
+Xilinx provides technical support for use of this product when used
+according to the guidelines described in the core documentation, and
+cannot guarantee timing, functionality, or support of this product for
+designs that do not follow specified guidelines.
+
+
+................................................................................
+
+7. CORE RELEASE HISTORY
+
+
+Date        By            Version      Description
+================================================================================
+06/19/2013  Xilinx, Inc.  3.6(Rev3)    ISE 14.6 support
+10/16/2012  Xilinx, Inc.  3.6(Rev2)    ISE 14.3 support
+07/25/2012  Xilinx, Inc.  3.6          ISE 14.2 support
+04/24/2012  Xilinx, Inc.  3.5          ISE 14.1 support
+01/18/2012  Xilinx, Inc.  3.3          ISE 13.4 support
+06/22/2011  Xilinx, Inc.  3.2          ISE 13.2 support
+03/01/2011  Xilinx, Inc.  3.1          ISE 13.1 support
+12/14/2010  Xilinx, Inc.  1.8          ISE 12.4 support
+09/21/2010  Xilinx, Inc.  1.7          ISE 12.3 support
+07/23/2010  Xilinx, Inc.  1.6          ISE 12.2 support
+04/19/2010  Xilinx, Inc.  1.5          ISE 12.1 support
+12/02/2009  Xilinx, Inc.  1.4          ISE 11.4 support
+09/16/2009  Xilinx, Inc.  1.3          ISE 11.3 support
+06/24/2009  Xilinx, Inc.  1.2          ISE 11.2 support
+04/24/2009  Xilinx, Inc.  1.1          Initial release; 11.1 support
+================================================================================
+                          
+................................................................................
+
+8. LEGAL DISCLAIMER
+
+(c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
+
+This file contains confidential and proprietary information
+of Xilinx, Inc. and is protected under U.S. and
+international copyright and other intellectual property
+laws.
+
+DISCLAIMER
+This disclaimer is not a license and does not grant any
+rights to the materials distributed herewith. Except as
+otherwise provided in a valid license issued to you by
+Xilinx, and to the maximum extent permitted by applicable
+law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+(2) Xilinx shall not be liable (whether in contract or tort,
+including negligence, or under any other theory of
+liability) for any loss or damage of any kind or nature
+related to, arising under or in connection with these
+materials, including for any direct, or any indirect,
+special, incidental, or consequential loss or damage
+(including loss of data, profits, goodwill, or any type of
+loss or damage suffered as a result of any action brought
+by a third party) even if such damage or loss was
+reasonably foreseeable or Xilinx had been advised of the
+possibility of the same.
+
+CRITICAL APPLICATIONS
+Xilinx products are not designed or intended to be fail-
+safe, or for use in any application requiring fail-safe
+performance, such as life-support or safety devices or
+systems, Class III medical devices, nuclear facilities,
+applications related to the deployment of airbags, or any
+other applications that could lead to death, personal
+injury, or severe property or environmental damage
+(individually and collectively, "Critical
+Applications"). Customer assumes the sole risk and
+liability of any use of Xilinx products in Critical
+Applications, subject only to applicable laws and
+regulations governing limitations on product liability.
+
+THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+PART OF THIS FILE AT ALL TIMES.
+
+
+