From 4bb61ab722113d810b65629397c1f9d64fc38fcd Mon Sep 17 00:00:00 2001 From: sfencevma <15155930562@163.com> Date: Tue, 7 Jan 2025 13:53:34 +0800 Subject: [PATCH] fix(LoadUnit): s3_mmio_req use RegNext instead of RegEnable --- src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala b/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala index e1955819a1..01ef2d9d63 100644 --- a/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala +++ b/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala @@ -1484,7 +1484,7 @@ class LoadUnit(implicit p: Parameters) extends XSModule val s3_vec_alignedType = RegEnable(s2_out.alignedType, s2_fire) val s3_vec_mBIndex = RegEnable(s2_out.mbIndex, s2_fire) val s3_frm_mabuf = s3_in.isFrmMisAlignBuf - val s3_mmio_req = RegEnable(s2_mmio_req, s2_mmio_req.valid) + val s3_mmio_req = RegNext(s2_mmio_req) val s3_pdest = RegEnable(Mux(s2_valid, s2_out.uop.pdest, s2_mmio_req.bits.uop.pdest), s2_fire) val s3_data_select = RegEnable(s2_data_select, 0.U(s2_data_select.getWidth.W), s2_fire) val s3_data_select_by_offset = RegEnable(s2_data_select_by_offset, 0.U.asTypeOf(s2_data_select_by_offset), s2_fire)